{"action":"created","comment":{"url":"https://api.github.com/repos/dmlc/tvm/pulls/comments/195897325","pull_request_review_id":129357465,"id":195897325,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDE5NTg5NzMyNQ==","diff_hunk":"@@ -0,0 +1,46 @@\n+import tvm\n+import numpy as np\n+import os\n+\n+os.environ[\"XCL_EMULATION_MODE\"] = \"1\"\n+\n+@tvm.register_func\n+def tvm_callback_vhls_postproc(code):\n+    \"\"\"Hook to inspect the Vivado HLS code before actually run it\"\"\"\n+    print(code)\n+    return code\n+\n+def test_exp():\n+    # graph\n+    n = tvm.convert(1024)\n+    A = tvm.placeholder((n,), name='A')\n+    B = tvm.compute(A.shape, lambda *i: tvm.exp(A(*i)), name='B')\n+    s = tvm.create_schedule(B.op)\n+    # create iter var and assign them tags.\n+    px, x = s[B].split(B.op.axis[0], nparts=1)\n+    s[B].bind(px, tvm.thread_axis(\"pipeline\"))\n+\n+    # one line to build the function.\n+    def check_device(device, host=\"stackvm\"):\n+        if not tvm.module.enabled(host):\n+            return\n+        ctx = tvm.context(device, 0)\n+        if not ctx.exist:\n+            return\n+        fexp = tvm.build(s, [A, B],\n+                         device, host,\n+                         name=\"myexp\")\n+        ctx = tvm.context(device, 0)\n+        # launch the kernel.\n+        n = 1024\n+        a = tvm.nd.array(np.random.uniform(size=n).astype(A.dtype), ctx)\n+        b = tvm.nd.array(np.zeros(n, dtype=B.dtype), ctx)\n+        fexp(a, b)\n+        np.testing.assert_allclose(\n+            b.asnumpy(), np.exp(a.asnumpy()), rtol=1e-5)\n+\n+    check_device(\"sdaccel\")","path":"tests/python/integration/test_ewise_fpga.py","position":42,"original_position":42,"commit_id":"b1d760a548e959da8119b405f807ed66adfc4bd7","original_commit_id":"b1d760a548e959da8119b405f807ed66adfc4bd7","user":{"login":"kazum","id":812126,"node_id":"MDQ6VXNlcjgxMjEyNg==","avatar_url":"https://avatars2.githubusercontent.com/u/812126?v=4","gravatar_id":"","url":"https://api.github.com/users/kazum","html_url":"https://github.com/kazum","followers_url":"https://api.github.com/users/kazum/followers","following_url":"https://api.github.com/users/kazum/following{/other_user}","gists_url":"https://api.github.com/users/kazum/gists{/gist_id}","starred_url":"https://api.github.com/users/kazum/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/kazum/subscriptions","organizations_url":"https://api.github.com/users/kazum/orgs","repos_url":"https://api.github.com/users/kazum/repos","events_url":"https://api.github.com/users/kazum/events{/privacy}","received_events_url":"https://api.github.com/users/kazum/received_events","type":"User","site_admin":false},"body":"I think the Jenkins environment of this community doesn't have SDAccel, so the test is not run via CI.  I checked the test works on my AWS F1 instance:\r\n```\r\n$ python -m nose -vs tests/python/integration/test_ewise_fpga.py\r\ntest_ewise_fpga.test_exp ... [07:37:36] /home/centos/src/project_data/tvm/src/runtime/opencl/opencl_device_api.cc:232: Initialize OpenCL platform 'Xilinx'\r\n[07:37:36] /home/centos/src/project_data/tvm/src/runtime/opencl/opencl_device_api.cc:259: opencl(0)='xilinx_aws-vu9p-f1_dynamic_5_0' cl_device_id=0x1ad7ef0\r\n#include <ap_int.h>\r\n\r\nextern \"C\" void myexp_kernel0( float* B,  float* A) {\r\n#pragma HLS INTERFACE m_axi port=B  offset=slave bundle=gmem\r\n#pragma HLS INTERFACE s_axilite port=B bundle=control\r\n#pragma HLS INTERFACE m_axi port=A  offset=slave bundle=gmem\r\n#pragma HLS INTERFACE s_axilite port=A bundle=control\r\n#pragma HLS INTERFACE s_axilite port=return bundle=control\r\n\r\n  for (int i0_inner = 0; i0_inner < 1024; ++i0_inner) {\r\n    B[i0_inner] = expf(A[i0_inner]);\r\n  }\r\n}\r\n\r\n\r\n\r\n****** xocc v2017.4 (64-bit)\r\n  **** SW Build 2193837 on Tue Apr 10 18:06:59 MDT 2018\r\n    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\r\n\r\nAttempting to get a license: ap_opencl\r\nFeature available: ap_opencl\r\nINFO: [XOCC 60-585] Compiling for software emulation target\r\n\r\n(snip)\r\n\r\nINFO: [XOCC 60-586] Created /tmp/tmpc5uk9a/output.xclbin\r\nINFO: [XOCC 60-791] Total elapsed time: 0h 0m 11s\r\nok\r\n\r\n----------------------------------------------------------------------\r\nRan 1 test in 61.040s\r\n\r\nOK\r\n```\r\n\r\nI set the environment variable XCL_EMULATION_MODE in the python test file, so SDAccel doesn't generate a bitstream but run in software emulation mode - it works like a mock.\r\n\r\nLet me know if I'm missing something.","created_at":"2018-06-16T07:53:23Z","updated_at":"2018-06-16T07:53:23Z","html_url":"https://github.com/dmlc/tvm/pull/1278#discussion_r195897325","pull_request_url":"https://api.github.com/repos/dmlc/tvm/pulls/1278","author_association":"CONTRIBUTOR","_links":{"self":{"href":"https://api.github.com/repos/dmlc/tvm/pulls/comments/195897325"},"html":{"href":"https://github.com/dmlc/tvm/pull/1278#discussion_r195897325"},"pull_request":{"href":"https://api.github.com/repos/dmlc/tvm/pulls/1278"}},"in_reply_to_id":195893770},"pull_request":{"url":"https://api.github.com/repos/dmlc/tvm/pulls/1278","id":194706612,"node_id":"MDExOlB1bGxSZXF1ZXN0MTk0NzA2NjEy","html_url":"https://github.com/dmlc/tvm/pull/1278","diff_url":"https://github.com/dmlc/tvm/pull/1278.diff","patch_url":"https://github.com/dmlc/tvm/pull/1278.patch","issue_url":"https://api.github.com/repos/dmlc/tvm/issues/1278","number":1278,"state":"open","locked":false,"title":"Add support for Xilinx FPGA board with SDAccel","user":{"login":"kazum","id":812126,"node_id":"MDQ6VXNlcjgxMjEyNg==","avatar_url":"https://avatars2.githubusercontent.com/u/812126?v=4","gravatar_id":"","url":"https://api.github.com/users/kazum","html_url":"https://github.com/kazum","followers_url":"https://api.github.com/users/kazum/followers","following_url":"https://api.github.com/users/kazum/following{/other_user}","gists_url":"https://api.github.com/users/kazum/gists{/gist_id}","starred_url":"https://api.github.com/users/kazum/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/kazum/subscriptions","organizations_url":"https://api.github.com/users/kazum/orgs","repos_url":"https://api.github.com/users/kazum/repos","events_url":"https://api.github.com/users/kazum/events{/privacy}","received_events_url":"https://api.github.com/users/kazum/received_events","type":"User","site_admin":false},"body":"This PR adds initial support for Xilinx FPGA boards with SDAccel.  The following are included:\r\n - SDAccel backend based on OpenCL runtime\r\n - Vivado HLS code generation\r\n - Tutorial to deploy TVM on AWS F1 instance\r\n\r\nThis PR is only preliminary implementation, but would be a good start point for FPGA supports, I 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