{"push_id":2552156024,"size":13,"distinct_size":13,"ref":"refs/heads/master","head":"6889537ce7bd0ac5a1042634a15e75473b3b3f75","before":"4581920e46733ada7bbf5c32bd436504394cf70e","commits":[{"sha":"35d3d7ee6fe9f210f777418c865d19e77aa59be2","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86] Fix Broadwell's Shuffle256 schedule classes load latency values.\n\nAllows us to remove some unnecessary InstRW overrides.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331913 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/35d3d7ee6fe9f210f777418c865d19e77aa59be2"},{"sha":"c7ccc04824de7bef29f1467088263fe93f711afd","author":{"name":"Matt Arsenault","email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com"},"message":"AMDGPU: Partially shrink 64-bit shifts if reduced to 16-bit\n\nThis is an extension of an existing combine to reduce wider\nshls if the result fits in the final result type. This\nintroduces the same combine, but reduces the shift to a middle\nsized type to avoid the slow 64-bit shift.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331916 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/c7ccc04824de7bef29f1467088263fe93f711afd"},{"sha":"5d4101dba497813ce1a21df3736f42c50f62c1be","author":{"name":"Matt Arsenault","email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com"},"message":"AMDGPU: Handle partial shift reduction for variable shifts\n\nIf the variable shift amount has known bits, we can still reduce\nthe shift.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331917 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/5d4101dba497813ce1a21df3736f42c50f62c1be"},{"sha":"3a2083a2cd8c7a1c19c7925f423572fb8798cd48","author":{"name":"Krzysztof Parzyszek","email":"c75c6ffbe1757b9a0c4a980ebbd301c4f55ecd30@codeaurora.org"},"message":"[Hexagon] Add patterns for vector shift-and-accumulate\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331918 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/3a2083a2cd8c7a1c19c7925f423572fb8798cd48"},{"sha":"c31fde08240578bfb5fdc2d8058a52f5d8a161f5","author":{"name":"Matt Arsenault","email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com"},"message":"AMDGPU: Ignore any_extend in mul24 combine\n\nIf a multiply is truncated, SimplifyDemandedBits\nsometimes turns a zero_extend of the inputs into an\nany_extend, which makes the known bits computation unhelpful.\nIgnore these and compute known bits for the underlying value,\nsince we insert the correct extend type after.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331919 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/c31fde08240578bfb5fdc2d8058a52f5d8a161f5"},{"sha":"030b9437a70e7d502c76733cad8f1cd4d1605176","author":{"name":"Farhana Aleen","email":"6f3c4fc3a36a36c78c831ff1ac5f3ce9ef337418@gmail.com"},"message":"[AMDGPU] Support horizontal vectorization of min/max.\n\nAuthor: FarhanaAleen\n\nReviewed By: rampitec\n\nSubscribers: AMDGPU\n\nDifferential Revision: https://reviews.llvm.org/D46604\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331920 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/030b9437a70e7d502c76733cad8f1cd4d1605176"},{"sha":"dd5a608d8b677a64d70b7026f9ae8c2d3b990225","author":{"name":"Paul Semel","email":"e3e0e96728d8016e88bce48ed9ec9751ba671429@gmail.com"},"message":"[llvm-objcopy] Add --strip-symbol (-N) option\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331924 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/dd5a608d8b677a64d70b7026f9ae8c2d3b990225"},{"sha":"051da15b1e7c2740c8cafb9d7a1539fc7abdabea","author":{"name":"Roman Tereshin","email":"9f5605aa7534078ac143ef848e29fbf210f38d66@apple.com"},"message":"[GlobalISel][Legalizer] Widening the second src op of shifts bug fix\n\nThe second source operand of G_SHL, G_ASHR, and G_LSHR must preserve its\nvalue as a (small) unsigned integer, therefore its incorrect to widen it\nin any way but by zero extending it.\n\nG_SHL was using G_ANYEXT and G_ASHR - G_SEXT (which is correct for their\ndestination and first source operands, but not the \"number of bits to\nshift\" operand).\n\nGenerally, shifts aren't as similar to regular binary operations as it\nmight seem, for instance, they aren't commutative nor associative and\nthe second source operand usually requires a special treatment.\n\nReviewers: bogner, javed.absar, aivchenk, rovka\n\nReviewed By: bogner\n\nSubscribers: igorb, kristof.beyls, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D46413\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331926 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/051da15b1e7c2740c8cafb9d7a1539fc7abdabea"},{"sha":"0f4cc99891330a993cf9c5e23cc54bd386346c74","author":{"name":"Amaury Sechet","email":"0e504717262715831a4568194b28f33dfb77b110@gmail.com"},"message":"[ARM] Add support for SETCCCARRY instead of SETCCE\n\nSummary: As per title. SETCCE is deprecated and will eventually be removed.\n\nReviewers: rogfer01, efriedma, rengolin, javed.absar\n\nSubscribers: kristof.beyls, chrib, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D46512\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331929 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/0f4cc99891330a993cf9c5e23cc54bd386346c74"},{"sha":"c1c66c0705123847792fe63294234c81b409c483","author":{"name":"Benjamin Kramer","email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com"},"message":"[InstCombine] Teach SimplifyDemandedBits that udiv doesn't demand low dividend bits that are zero in the divisor\n\nThis is safe as long as the udiv is not exact. The pattern is not common in\nC++ code, but comes up all the time in code generated by XLA's GPU backend.\n\nDifferential Revision: https://reviews.llvm.org/D46647\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331933 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/c1c66c0705123847792fe63294234c81b409c483"},{"sha":"eb0a966870309dfba470d1486fbadd5087be03b2","author":{"name":"Philip Reames","email":"1a6d70c497b881333962fb40612e3f3827d7c1cd@philipreames.com"},"message":"[InstCombine] Widen guards with conditions between\n\nThe previous handling for guard widening in InstCombine was extremely restrictive. In particular, it didn't handle the common case where we had two guards separated by a single icmp. Handle this by scanning through a small fixed window of instructions to find the next guard if needed.\n\nDifferential Revision: https://reviews.llvm.org/D46203\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331935 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/eb0a966870309dfba470d1486fbadd5087be03b2"},{"sha":"1e84bc6951c3ff3e2442a2a3a2d1bb006ae65322","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[AggressiveInstCombine] convert a chain of 'and-shift' bits into masked compare\n\nThis is a follow-up to D45986. As suggested there, we should match the \"all-bits-set\" \npattern in addition to \"any-bits-set\".\n\nThis was a little more complicated than I thought it would be initially because the \n\"and 1\" instruction can be anywhere in the chain. Hopefully, the code comments make \nthat logic understandable, but if you see a way to simplify or improve that, it's \nmost appreciated.\n\nThis transforms patterns that emerge from bitfield tests as seen in PR37098:\nhttps://bugs.llvm.org/show_bug.cgi?id=37098\n\nI think it would also help reduce the large test from:\nD46336\nD46595 \nbut we need something to reassociate that case to the forms we're expecting here first.\n\nDifferential Revision: https://reviews.llvm.org/D46649\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331937 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/1e84bc6951c3ff3e2442a2a3a2d1bb006ae65322"},{"sha":"6889537ce7bd0ac5a1042634a15e75473b3b3f75","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[PhaseOrdering] remove stale comments; NFC\n\nForgot to update this with rL331937.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331939 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/6889537ce7bd0ac5a1042634a15e75473b3b3f75"}]}
{"actor":{"display_login":"kraj"}}