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One problem is blackboxes (plusarg_reader.v in particular!). Rocket's build system knows to look in `vsrc/` for extra verilog sources and `csrc/` for extra C/C++ sources, but if you are using rocket as an sbt dependency you need to do some extra bookkeeping to make sure the right blackboxes are included in your own build system.\r\n\r\nChisel has a mechanism that is intended to help resolve the general problem of chisel libraries that have blackboxes- `HasBlackBoxResource`. You can include the blackboxes in the library's jar and then pass an annotation to firrtl telling it to emit the blackboxes along with the generated verilog. I would consider [the implementation of simulation-only floating point in the dsptools library](https://github.com/ucb-bar/dsptools/blob/53f6ce7f2b559f1a2bbbbcfa59bbb1d3cd50f73b/src/main/scala/dsptools/numbers/blackbox_compatibility/DspRealVerilatorBB.scala) a good example of why you'd want this and how to use it. #1217 discussed this somewhat as well (this closes #1217).\r\n\r\nThis PR adds the trait `HasBlackBoxResource` to blackboxes in rocket and adds the contents of the `vsrc/` and `csrc/` directories to `rocketchip.jar`. When running firrtl, the blackboxes will be put in `generated-src/`. However, I haven't modified the build system at all, so they won't be used- the originals in `vsrc/` and `csrc/` will be used instead. However, people using rocket as a library for other projects (like me) will be able to use components from rocket without worrying about maintaining separate copies `vsrc/` and `csrc/`.\r\n\r\nI also made some small changes to the `build.sbt` file that make rocket suitable for publishing on something like sonatype. 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