{"push_id":2318860669,"size":224,"distinct_size":53,"ref":"refs/heads/master","head":"f1517df8701c9f12dae9ce7f43a5d300a6917619","before":"581e400ff935d34d95811258586128bf11baef15","commits":[{"sha":"f9fc049ef1e05da3e3d2a45d098ec89b89bf687e","author":{"name":"Gary R Hook","email":"0495c4ee8514403de90bea3f50dee5846886dede@amd.com"},"message":"iommu/amd - Record more information about unknown events\n\nWhen an unknown type event occurs, the default information written to\nthe syslog should dump raw event data. This could provide insight into\nthe event that occurred.\n\nSigned-off-by: Gary R Hook <gary.hook@amd.com>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/f9fc049ef1e05da3e3d2a45d098ec89b89bf687e"},{"sha":"ff18c4e598de13af6503d6adb66f3ad768b6a53e","author":{"name":"Gary R Hook","email":"0495c4ee8514403de90bea3f50dee5846886dede@amd.com"},"message":"iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices\n\nThe AMD IOMMU specification Rev 3.00 (December 2016) introduces a\nnew Enhanced PPR Handling Support (EPHSup) bit in the MMIO register\noffset 0030h (IOMMU Extended Feature Register).\n\nWhen EPHSup=1, the IOMMU hardware requires the PPR bit of the\ndevice table entry (DTE) to be set in order to support PPR for a\nparticular endpoint device.\n\nPlease see https://support.amd.com/TechDocs/48882_IOMMU.pdf for\nthis revision of the AMD IOMMU specification.\n\nSigned-off-by: Gary R Hook <gary.hook@amd.com>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/ff18c4e598de13af6503d6adb66f3ad768b6a53e"},{"sha":"ca84eaeb3e0520555ee031b5ed26ce1b4b1bbd84","author":{"name":"Magnus Damm","email":"770671937655f6712e0974c9ba989695d507d4c3@opensource.se"},"message":"iommu/ipmmu-vmsa: Add r8a7796 DT binding\n\nUpdate the IPMMU DT binding documentation to include the r8a7796 compat\nstring for R-Car M3-W.\n\nSigned-off-by: Magnus Damm <damm+renesas@opensource.se>\nAcked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nAcked-by: Rob Herring <robh@kernel.org>\nAcked-by: Simon Horman <horms+renesas@verge.net.au>\nAcked-by: Geert Uytterhoeven <geert+renesas@glider.be>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/ca84eaeb3e0520555ee031b5ed26ce1b4b1bbd84"},{"sha":"9327b810bb7e1f3322fe8ed862a62fe0f2c9f14b","author":{"name":"Simon Horman","email":"6794a6886a01c3e0703587f01250d8dad41b4a90@verge.net.au"},"message":"iommu/ipmmu-vmsa: Add r8a779(70|95) DT bindings\n\nUpdate the IPMMU DT binding documentation to include the\nr8a77970 (R-Car V3M) and r8a77995 (R-Car D3) compat strings.\n\nBased on work for r8a7796 by Magnus Damm.\n\nSigned-off-by: Simon Horman <horms+renesas@verge.net.au>\nReviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/9327b810bb7e1f3322fe8ed862a62fe0f2c9f14b"},{"sha":"9ae9df035c274c89b7fe3dbc74cbe2fa63386668","author":{"name":"Jordan Crouse","email":"703f4140ed82505f102ff92fc200ee731864895f@codeaurora.org"},"message":"iommu: Check the result of iommu_group_get() for NULL\n\nThe result of iommu_group_get() was being blindly used in both\nattach and detach which results in a dereference when trying\nto work with an unknown device.\n\nSigned-off-by: Jordan Crouse <jcrouse@codeaurora.org>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/9ae9df035c274c89b7fe3dbc74cbe2fa63386668"},{"sha":"72d548113881dd32bf7f0b221d031e6586468437","author":{"name":"Jerry Snitselaar","email":"29e12eca1df3514e990c4139c41803d17a47fbef@redhat.com"},"message":"iommu/vt-d: clean up pr_irq if request_threaded_irq fails\n\nIt is unlikely request_threaded_irq will fail, but if it does for some\nreason we should clear iommu->pr_irq in the error path. Also\nintel_svm_finish_prq shouldn't try to clean up the page request\ninterrupt if pr_irq is 0. Without these, if request_threaded_irq were\nto fail the following occurs:\n\nfail with no fixes:\n\n[    0.683147] ------------[ cut here ]------------\n[    0.683148] NULL pointer, cannot free irq\n[    0.683158] WARNING: CPU: 1 PID: 1 at kernel/irq/irqdomain.c:1632 irq_domain_free_irqs+0x126/0x140\n[    0.683160] Modules linked in:\n[    0.683163] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc2 #3\n[    0.683165] Hardware name:                  /NUC7i3BNB, BIOS BNKBL357.86A.0036.2017.0105.1112 01/05/2017\n[    0.683168] RIP: 0010:irq_domain_free_irqs+0x126/0x140\n[    0.683169] RSP: 0000:ffffc90000037ce8 EFLAGS: 00010292\n[    0.683171] RAX: 000000000000001d RBX: ffff880276283c00 RCX: ffffffff81c5e5e8\n[    0.683172] RDX: 0000000000000001 RSI: 0000000000000096 RDI: 0000000000000246\n[    0.683174] RBP: ffff880276283c00 R08: 0000000000000000 R09: 000000000000023c\n[    0.683175] R10: 0000000000000007 R11: 0000000000000000 R12: 000000000000007a\n[    0.683176] R13: 0000000000000001 R14: 0000000000000000 R15: 0000010010000000\n[    0.683178] FS:  0000000000000000(0000) GS:ffff88027ec80000(0000) knlGS:0000000000000000\n[    0.683180] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033\n[    0.683181] CR2: 0000000000000000 CR3: 0000000001c09001 CR4: 00000000003606e0\n[    0.683182] Call Trace:\n[    0.683189]  intel_svm_finish_prq+0x3c/0x60\n[    0.683191]  free_dmar_iommu+0x1ac/0x1b0\n[    0.683195]  init_dmars+0xaaa/0xaea\n[    0.683200]  ? klist_next+0x19/0xc0\n[    0.683203]  ? pci_do_find_bus+0x50/0x50\n[    0.683205]  ? pci_get_dev_by_id+0x52/0x70\n[    0.683208]  intel_iommu_init+0x498/0x5c7\n[    0.683211]  pci_iommu_init+0x13/0x3c\n[    0.683214]  ? e820__memblock_setup+0x61/0x61\n[    0.683217]  do_one_initcall+0x4d/0x1a0\n[    0.683220]  kernel_init_freeable+0x186/0x20e\n[    0.683222]  ? set_debug_rodata+0x11/0x11\n[    0.683225]  ? rest_init+0xb0/0xb0\n[    0.683226]  kernel_init+0xa/0xff\n[    0.683229]  ret_from_fork+0x1f/0x30\n[    0.683259] Code: 89 ee 44 89 e7 e8 3b e8 ff ff 5b 5d 44 89 e7 44 89 ee 41 5c 41 5d 41 5e e9 a8 84 ff ff 48 c7 c7 a8 71 a7 81 31 c0 e8 6a d3 f9 ff <0f> ff 5b 5d 41 5c 41 5d 41 5\ne c3 0f 1f 44 00 00 66 2e 0f 1f 84\n[    0.683285] ---[ end trace f7650e42792627ca ]---\n\nwith iommu->pr_irq = 0, but no check in intel_svm_finish_prq:\n\n[    0.669561] ------------[ cut here ]------------\n[    0.669563] Trying to free already-free IRQ 0\n[    0.669573] WARNING: CPU: 3 PID: 1 at kernel/irq/manage.c:1546 __free_irq+0xa4/0x2c0\n[    0.669574] Modules linked in:\n[    0.669577] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc2 #4\n[    0.669579] Hardware name:                  /NUC7i3BNB, BIOS BNKBL357.86A.0036.2017.0105.1112 01/05/2017\n[    0.669581] RIP: 0010:__free_irq+0xa4/0x2c0\n[    0.669582] RSP: 0000:ffffc90000037cc0 EFLAGS: 00010082\n[    0.669584] RAX: 0000000000000021 RBX: 0000000000000000 RCX: ffffffff81c5e5e8\n[    0.669585] RDX: 0000000000000001 RSI: 0000000000000086 RDI: 0000000000000046\n[    0.669587] RBP: 0000000000000000 R08: 0000000000000000 R09: 000000000000023c\n[    0.669588] R10: 0000000000000007 R11: 0000000000000000 R12: ffff880276253960\n[    0.669589] R13: ffff8802762538a4 R14: ffff880276253800 R15: ffff880276283600\n[    0.669593] FS:  0000000000000000(0000) GS:ffff88027ed80000(0000) knlGS:0000000000000000\n[    0.669594] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033\n[    0.669596] CR2: 0000000000000000 CR3: 0000000001c09001 CR4: 00000000003606e0\n[    0.669602] Call Trace:\n[    0.669616]  free_irq+0x30/0x60\n[    0.669620]  intel_svm_finish_prq+0x34/0x60\n[    0.669623]  free_dmar_iommu+0x1ac/0x1b0\n[    0.669627]  init_dmars+0xaaa/0xaea\n[    0.669631]  ? klist_next+0x19/0xc0\n[    0.669634]  ? pci_do_find_bus+0x50/0x50\n[    0.669637]  ? pci_get_dev_by_id+0x52/0x70\n[    0.669639]  intel_iommu_init+0x498/0x5c7\n[    0.669642]  pci_iommu_init+0x13/0x3c\n[    0.669645]  ? e820__memblock_setup+0x61/0x61\n[    0.669648]  do_one_initcall+0x4d/0x1a0\n[    0.669651]  kernel_init_freeable+0x186/0x20e\n[    0.669653]  ? set_debug_rodata+0x11/0x11\n[    0.669656]  ? rest_init+0xb0/0xb0\n[    0.669658]  kernel_init+0xa/0xff\n[    0.669661]  ret_from_fork+0x1f/0x30\n[    0.669662] Code: 7a 08 75 0e e9 c3 01 00 00 4c 39 7b 08 74 57 48 89 da 48 8b 5a 18 48 85 db 75 ee 89 ee 48 c7 c7 78 67 a7 81 31 c0 e8 4c 37 fa ff <0f> ff 48 8b 34 24 4c 89 ef e\n8 0e 4c 68 00 49 8b 46 40 48 8b 80\n[    0.669688] ---[ end trace 58a470248700f2fc ]---\n\nCc: Alex Williamson <alex.williamson@redhat.com>\nCc: Joerg Roedel <joro@8bytes.org>\nCc: Ashok Raj <ashok.raj@intel.com>\nSigned-off-by: Jerry Snitselaar <jsnitsel@redhat.com>\nReviewed-by: Ashok Raj <ashok.raj@intel.com>\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/72d548113881dd32bf7f0b221d031e6586468437"},{"sha":"be819f7b66031c4a21fdc8edc47a3ecd4cac635d","author":{"name":"Elena Reshetova","email":"ca7615e45606e9fb8cfe3ab86d8005547b5535f5@intel.com"},"message":"lockd: convert nsm_handle.sm_count from atomic_t to refcount_t\n\natomic_t variables are currently used to implement reference\ncounters with the following properties:\n - counter is initialized to 1 using atomic_set()\n - a resource is freed upon counter reaching zero\n - once counter reaches zero, its further\n   increments aren't allowed\n - counter schema uses basic atomic operations\n   (set, inc, inc_not_zero, dec_and_test, etc.)\n\nSuch atomic variables should be converted to a newly provided\nrefcount_t type and API that prevents accidental counter overflows\nand underflows. This is important since overflows and underflows\ncan lead to use-after-free situation and be exploitable.\n\nThe variable nsm_handle.sm_count is used as pure reference counter.\nConvert it to refcount_t and fix up the operations.\n\n**Important note for maintainers:\n\nSome functions from refcount_t API defined in lib/refcount.c\nhave different memory ordering guarantees than their atomic\ncounterparts.\nThe full comparison can be seen in\nhttps://lkml.org/lkml/2017/11/15/57 and it is hopefully soon\nin state to be merged to the documentation tree.\nNormally the differences should not matter since refcount_t provides\nenough guarantees to satisfy the refcounting use cases, but in\nsome rare cases it might matter.\nPlease double check that you don't have some undocumented\nmemory guarantees for this variable usage.\n\nFor the nsm_handle.sm_count it might make a difference\nin following places:\n - nsm_release(): decrement in refcount_dec_and_lock() only\n   provides RELEASE ordering, control dependency on success\n   and holds a spin lock on success vs. fully ordered atomic\n   counterpart. No change for the spin lock guarantees.\n\nSuggested-by: Kees Cook <keescook@chromium.org>\nReviewed-by: David Windsor <dwindsor@gmail.com>\nReviewed-by: Hans Liljestrand <ishkamiel@gmail.com>\nSigned-off-by: Elena Reshetova <elena.reshetova@intel.com>\nSigned-off-by: J. Bruce Fields <bfields@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/be819f7b66031c4a21fdc8edc47a3ecd4cac635d"},{"sha":"8bb3ea77933e9796f8f15a5492481a96af8302d6","author":{"name":"Elena Reshetova","email":"ca7615e45606e9fb8cfe3ab86d8005547b5535f5@intel.com"},"message":"lockd: convert nlm_lockowner.count from atomic_t to refcount_t\n\natomic_t variables are currently used to implement reference\ncounters with the following properties:\n - counter is initialized to 1 using atomic_set()\n - a resource is freed upon counter reaching zero\n - once counter reaches zero, its further\n   increments aren't allowed\n - counter schema uses basic atomic operations\n   (set, inc, inc_not_zero, dec_and_test, etc.)\n\nSuch atomic variables should be converted to a newly provided\nrefcount_t type and API that prevents accidental counter overflows\nand underflows. This is important since overflows and underflows\ncan lead to use-after-free situation and be exploitable.\n\nThe variable nlm_lockowner.count is used as pure reference counter.\nConvert it to refcount_t and fix up the operations.\n\n**Important note for maintainers:\n\nSome functions from refcount_t API defined in lib/refcount.c\nhave different memory ordering guarantees than their atomic\ncounterparts.\nThe full comparison can be seen in\nhttps://lkml.org/lkml/2017/11/15/57 and it is hopefully soon\nin state to be merged to the documentation tree.\nNormally the differences should not matter since refcount_t provides\nenough guarantees to satisfy the refcounting use cases, but in\nsome rare cases it might matter.\nPlease double check that you don't have some undocumented\nmemory guarantees for this variable usage.\n\nFor the nlm_lockowner.count it might make a difference\nin following places:\n - nlm_put_lockowner(): decrement in refcount_dec_and_lock() only\n   provides RELEASE ordering, control dependency on success and\n   holds a spin lock on success vs. fully ordered atomic counterpart.\n   No changes in spin lock guarantees.\n\nSuggested-by: Kees Cook <keescook@chromium.org>\nReviewed-by: David Windsor <dwindsor@gmail.com>\nReviewed-by: Hans Liljestrand <ishkamiel@gmail.com>\nSigned-off-by: Elena Reshetova <elena.reshetova@intel.com>\nSigned-off-by: J. Bruce Fields <bfields@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/8bb3ea77933e9796f8f15a5492481a96af8302d6"},{"sha":"d9226ec9ef01832b1edc1781241920614c6407db","author":{"name":"Elena Reshetova","email":"ca7615e45606e9fb8cfe3ab86d8005547b5535f5@intel.com"},"message":"lockd: convert nlm_rqst.a_count from atomic_t to refcount_t\n\natomic_t variables are currently used to implement reference\ncounters with the following properties:\n - counter is initialized to 1 using atomic_set()\n - a resource is freed upon counter reaching zero\n - once counter reaches zero, its further\n   increments aren't allowed\n - counter schema uses basic atomic operations\n   (set, inc, inc_not_zero, dec_and_test, etc.)\n\nSuch atomic variables should be converted to a newly provided\nrefcount_t type and API that prevents accidental counter overflows\nand underflows. This is important since overflows and underflows\ncan lead to use-after-free situation and be exploitable.\n\nThe variable nlm_rqst.a_count is used as pure reference counter.\nConvert it to refcount_t and fix up the operations.\n\n**Important note for maintainers:\n\nSome functions from refcount_t API defined in lib/refcount.c\nhave different memory ordering guarantees than their atomic\ncounterparts.\nThe full comparison can be seen in\nhttps://lkml.org/lkml/2017/11/15/57 and it is hopefully soon\nin state to be merged to the documentation tree.\nNormally the differences should not matter since refcount_t provides\nenough guarantees to satisfy the refcounting use cases, but in\nsome rare cases it might matter.\nPlease double check that you don't have some undocumented\nmemory guarantees for this variable usage.\n\nFor the nlm_rqst.a_count it might make a difference\nin following places:\n - nlmclnt_release_call() and nlmsvc_release_call(): decrement\n   in refcount_dec_and_test() only\n   provides RELEASE ordering and control dependency on success\n   vs. fully ordered atomic counterpart\n\nSuggested-by: Kees Cook <keescook@chromium.org>\nReviewed-by: David Windsor <dwindsor@gmail.com>\nReviewed-by: Hans Liljestrand <ishkamiel@gmail.com>\nSigned-off-by: Elena Reshetova <elena.reshetova@intel.com>\nSigned-off-by: J. Bruce Fields <bfields@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/d9226ec9ef01832b1edc1781241920614c6407db"},{"sha":"66282ec1cf004c09083c29cb5e49019037937bbd","author":{"name":"Benjamin Coddington","email":"a662de85d20459d74b4e8c23fc1cb2d7c8533504@redhat.com"},"message":"nfsd4: permit layoutget of executable-only files\n\nClients must be able to read a file in order to execute it, and for pNFS\nthat means the client needs to be able to perform a LAYOUTGET on the file.\n\nThis behavior for executable-only files was added for OPEN in commit\na043226bc140 \"nfsd4: permit read opens of executable-only files\".\n\nThis fixes up xfstests generic/126 on block/scsi layouts.\n\nSigned-off-by: Benjamin Coddington <bcodding@redhat.com>\nSigned-off-by: J. Bruce Fields <bfields@redhat.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/66282ec1cf004c09083c29cb5e49019037937bbd"},{"sha":"fd989db807a00d552ebf29d8ffb20c2ef04742da","author":{"name":"Sergey Senozhatsky","email":"570a3d76c58b9b54de6bb70914e873361b66b749@gmail.com"},"message":"cris: Fix conflicting types for _etext, _edata, _end\n\nInclude asm/sections.h header which contains the correct\ntypes for _etext, _edata and _end - char arrays.\n\nSigned-off-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>\nSigned-off-by: Jesper Nilsson <jesper.nilsson@axis.com>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/fd989db807a00d552ebf29d8ffb20c2ef04742da"},{"sha":"f18affbea8f7aebb235bfdaf3ad4c307aa5f3d64","author":{"name":"Geert Uytterhoeven","email":"91a5f0ac06d51a651e45b62a5b36e28880b80bc4@glider.be"},"message":"iommu/omap: Fix debugfs_create_*() usage\n\nWhen exposing data access through debugfs, the correct\ndebugfs_create_*() functions must be used, depending on data type.\n\nRemove all casts from data pointers passed to debugfs_create_*()\nfunctions, as such casts prevent the compiler from flagging bugs.\n\nomap_iommu.nr_tlb_entries is \"int\", hence casting to \"u8 *\" exposes only\na part of it.  Fix this by using debugfs_create_u32() instead.\n\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/f18affbea8f7aebb235bfdaf3ad4c307aa5f3d64"},{"sha":"dc98b8480d8a68c2ce9aa28b9f0d714fd258bc0b","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"iommu/exynos: Don't unconditionally steal bus ops\n\nRemoving the early device registration hook overlooked the fact that\nit only ran conditionally on a compatible device being present in the\nDT. With exynos_iommu_init() now running as an unconditional initcall,\nproblems arise on non-Exynos systems when other IOMMU drivers find\nthemselves unable to install their ops on the platform bus, or at worst\nthe Exynos ops get called with someone else's domain and all hell breaks\nloose.\n\nThe global ops/cache setup could probably all now be triggered from the\nfirst IOMMU probe, as with dma_dev assigment, but for the time being the\nsimplest fix is to resurrect the logic from commit a7b67cd5d9af\n(\"iommu/exynos: Play nice in multi-platform builds\") to explicitly check\nthe DT for the presence of an Exynos IOMMU before trying anything.\n\nFixes: 928055a01b3f (\"iommu/exynos: Remove custom platform device registration code\")\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nAcked-by: Marek Szyprowski <m.szyprowski@samsung.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/dc98b8480d8a68c2ce9aa28b9f0d714fd258bc0b"},{"sha":"9d2e6505f6d6934e681aed502f566198cb25c74a","author":{"name":"Peter Xu","email":"095589f365f63a75bdb77eeef427b0f1da098ea8@redhat.com"},"message":"iommu/vt-d: Use domain instead of cache fetching\n\nafter commit a1ddcbe93010 (\"iommu/vt-d: Pass dmar_domain directly into\niommu_flush_iotlb_psi\", 2015-08-12), we have domain pointer as parameter\nto iommu_flush_iotlb_psi(), so no need to fetch it from cache again.\n\nMore importantly, a NULL reference pointer bug is reported on RHEL7 (and\nit can be reproduced on some old upstream kernels too, e.g., v4.13) by\nunplugging an 40g nic from a VM (hard to test unplug on real host, but\nit should be the same):\n\nhttps://bugzilla.redhat.com/show_bug.cgi?id=1531367\n\n[   24.391863] pciehp 0000:00:03.0:pcie004: Slot(0): Attention button pressed\n[   24.393442] pciehp 0000:00:03.0:pcie004: Slot(0): Powering off due to button press\n[   29.721068] i40evf 0000:01:00.0: Unable to send opcode 2 to PF, err I40E_ERR_QUEUE_EMPTY, aq_err OK\n[   29.783557] iommu: Removing device 0000:01:00.0 from group 3\n[   29.784662] BUG: unable to handle kernel NULL pointer dereference at 0000000000000304\n[   29.785817] IP: iommu_flush_iotlb_psi+0xcf/0x120\n[   29.786486] PGD 0\n[   29.786487] P4D 0\n[   29.786812]\n[   29.787390] Oops: 0000 [#1] SMP\n[   29.787876] Modules linked in: ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 xt_conntrack ip_set nfnetlink ebtable_nat ebtable_broute bridge stp llc ip6table_ng\n[   29.795371] CPU: 0 PID: 156 Comm: kworker/0:2 Not tainted 4.13.0 #14\n[   29.796366] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.11.0-1.el7 04/01/2014\n[   29.797593] Workqueue: pciehp-0 pciehp_power_thread\n[   29.798328] task: ffff94f5745b4a00 task.stack: ffffb326805ac000\n[   29.799178] RIP: 0010:iommu_flush_iotlb_psi+0xcf/0x120\n[   29.799919] RSP: 0018:ffffb326805afbd0 EFLAGS: 00010086\n[   29.800666] RAX: ffff94f5bc56e800 RBX: 0000000000000000 RCX: 0000000200000025\n[   29.801667] RDX: ffff94f5bc56e000 RSI: 0000000000000082 RDI: 0000000000000000\n[   29.802755] RBP: ffffb326805afbf8 R08: 0000000000000000 R09: ffff94f5bc86bbf0\n[   29.803772] R10: ffffb326805afba8 R11: 00000000000ffdc4 R12: ffff94f5bc86a400\n[   29.804789] R13: 0000000000000000 R14: 00000000ffdc4000 R15: 0000000000000000\n[   29.805792] FS:  0000000000000000(0000) GS:ffff94f5bfc00000(0000) knlGS:0000000000000000\n[   29.806923] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033\n[   29.807736] CR2: 0000000000000304 CR3: 000000003499d000 CR4: 00000000000006f0\n[   29.808747] Call Trace:\n[   29.809156]  flush_unmaps_timeout+0x126/0x1c0\n[   29.809800]  domain_exit+0xd6/0x100\n[   29.810322]  device_notifier+0x6b/0x70\n[   29.810902]  notifier_call_chain+0x4a/0x70\n[   29.812822]  __blocking_notifier_call_chain+0x47/0x60\n[   29.814499]  blocking_notifier_call_chain+0x16/0x20\n[   29.816137]  device_del+0x233/0x320\n[   29.817588]  pci_remove_bus_device+0x6f/0x110\n[   29.819133]  pci_stop_and_remove_bus_device+0x1a/0x20\n[   29.820817]  pciehp_unconfigure_device+0x7a/0x1d0\n[   29.822434]  pciehp_disable_slot+0x52/0xe0\n[   29.823931]  pciehp_power_thread+0x8a/0xa0\n[   29.825411]  process_one_work+0x18c/0x3a0\n[   29.826875]  worker_thread+0x4e/0x3b0\n[   29.828263]  kthread+0x109/0x140\n[   29.829564]  ? process_one_work+0x3a0/0x3a0\n[   29.831081]  ? kthread_park+0x60/0x60\n[   29.832464]  ret_from_fork+0x25/0x30\n[   29.833794] Code: 85 ed 74 0b 5b 41 5c 41 5d 41 5e 41 5f 5d c3 49 8b 54 24 60 44 89 f8 0f b6 c4 48 8b 04 c2 48 85 c0 74 49 45 0f b6 ff 4a 8b 3c f8 <80> bf\n[   29.838514] RIP: iommu_flush_iotlb_psi+0xcf/0x120 RSP: ffffb326805afbd0\n[   29.840362] CR2: 0000000000000304\n[   29.841716] ---[ end trace b10ec0d6900868d3 ]---\n\nThis patch fixes that problem if applied to v4.13 kernel.\n\nThe bug does not exist on latest upstream kernel since it's fixed as a\nside effect of commit 13cf01744608 (\"iommu/vt-d: Make use of iova\ndeferred flushing\", 2017-08-15).  But IMHO it's still good to have this\npatch upstream.\n\nCC: Alex Williamson <alex.williamson@redhat.com>\nSigned-off-by: Peter Xu <peterx@redhat.com>\nFixes: a1ddcbe93010 (\"iommu/vt-d: Pass dmar_domain directly into iommu_flush_iotlb_psi\")\nReviewed-by: Alex Williamson <alex.williamson@redhat.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/9d2e6505f6d6934e681aed502f566198cb25c74a"},{"sha":"5e3b4a15dd8da6bded2092694c8db3b505cbf711","author":{"name":"Sohil Mehta","email":"2582a1d41fdb51f97d99ba00105f834b478a8578@intel.com"},"message":"iommu/vt-d: Enable upto 57 bits of domain address width\n\nUpdate the IOMMU default domain address width to 57 bits. This would\nenable the IOMMU to do upto 5-levels of paging for second level\ntranslations - IOVA translation requests without PASID.\n\nEven though the maximum supported address width is being increased to\n57, __iommu_calculate_agaw() would set the actual supported address\nwidth to the maximum support available in IOMMU hardware.\n\nSigned-off-by: Sohil Mehta <sohil.mehta@intel.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/5e3b4a15dd8da6bded2092694c8db3b505cbf711"},{"sha":"59103caa6839592788e7ad58b35863aac034631a","author":{"name":"Sohil Mehta","email":"2582a1d41fdb51f97d99ba00105f834b478a8578@intel.com"},"message":"iommu/vt-d: Add a check for 1GB page support\n\nAdd a check to verify IOMMU 1GB page support. If the CPU supports 1GB\npages but the IOMMU does not support it then disable SVM by not\nallocating PASID tables.\n\nSigned-off-by: Sohil Mehta <sohil.mehta@intel.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/59103caa6839592788e7ad58b35863aac034631a"},{"sha":"f1ac10c24efbbcba0f8dae37ee90d45847f5c5af","author":{"name":"Sohil Mehta","email":"2582a1d41fdb51f97d99ba00105f834b478a8578@intel.com"},"message":"iommu/vt-d: Add a check for 5-level paging support\n\nAdd a check to verify IOMMU 5-level paging support. If the CPU supports\nsupports 5-level paging but the IOMMU does not support it then disable\nSVM by not allocating PASID tables.\n\nSigned-off-by: Sohil Mehta <sohil.mehta@intel.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/f1ac10c24efbbcba0f8dae37ee90d45847f5c5af"},{"sha":"2f13eb7c580fcbe3d73ebbe6fb1841381cad0a05","author":{"name":"Sohil Mehta","email":"2582a1d41fdb51f97d99ba00105f834b478a8578@intel.com"},"message":"iommu/vt-d: Enable 5-level paging mode in the PASID entry\n\nIf the CPU has support for 5-level paging enabled and the IOMMU also\nsupports 5-level paging then enable the 5-level paging mode for first-\nlevel translations - used when SVM is enabled.\n\nSigned-off-by: Sohil Mehta <sohil.mehta@intel.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/2f13eb7c580fcbe3d73ebbe6fb1841381cad0a05"},{"sha":"892d7aaddb24b0d3eaf05534ed29a264d3b52646","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"iommu/msm: Claim bus ops on probe\n\nSince the MSM IOMMU driver now probes via DT exclusively rather than\nplatform data, dependent masters should be deferred until the IOMMU\nitself is ready. Thus we can do away with the early initialisation\nhook to unconditionally claim the bus ops, and instead do that only\nonce an IOMMU is actually probed. Furthermore, this should also make\nthe driver safe for multiplatform kernels on non-MSM SoCs.\n\nReviewed-by: Sricharan R <sricharan@codeaurora.org>\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/892d7aaddb24b0d3eaf05534ed29a264d3b52646"},{"sha":"e7747d88e05eabed6fd921c3636a9d1f5b4f754f","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"iommu/ipmmu-vmsa: Remove redundant of_iommu_init_fn hook\n\nHaving of_iommu_init() call ipmmu_init() via ipmmu_vmsa_iommu_of_setup()\ndoes nothing that the subsys_initcall wouldn't do slightly later anyway,\nsince probe-deferral of masters means it is no longer critical to\nregister the driver super-early. Clean it up.\n\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>","distinct":false,"url":"https://api.github.com/repos/jessfraz/linux/commits/e7747d88e05eabed6fd921c3636a9d1f5b4f754f"}]}
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