{"action":"opened","issue":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/402","repository_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing","labels_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/402/labels{/name}","comments_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/402/comments","events_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/402/events","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/402","id":368705574,"node_id":"MDU6SXNzdWUzNjg3MDU1NzQ=","number":402,"title":"VPR doesn't handle the \"all zero\" case for cb and sb patterns","user":{"login":"kpad-git","id":43962888,"node_id":"MDQ6VXNlcjQzOTYyODg4","avatar_url":"https://avatars0.githubusercontent.com/u/43962888?v=4","gravatar_id":"","url":"https://api.github.com/users/kpad-git","html_url":"https://github.com/kpad-git","followers_url":"https://api.github.com/users/kpad-git/followers","following_url":"https://api.github.com/users/kpad-git/following{/other_user}","gists_url":"https://api.github.com/users/kpad-git/gists{/gist_id}","starred_url":"https://api.github.com/users/kpad-git/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/kpad-git/subscriptions","organizations_url":"https://api.github.com/users/kpad-git/orgs","repos_url":"https://api.github.com/users/kpad-git/repos","events_url":"https://api.github.com/users/kpad-git/events{/privacy}","received_events_url":"https://api.github.com/users/kpad-git/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2018-10-10T14:51:51Z","updated_at":"2018-10-10T14:51:51Z","closed_at":null,"author_association":"NONE","body":"If an arch file specifies cb or sb patterns for a segment as \"0 0 0 0\" (ie. all zeroes), VPR still generates connection and switch blocks for the beginning and end of the wire.\r\n\r\n#### Expected Behaviour\r\nI would expect that no connection or switch boxes would be generated.\r\n\r\n#### Steps to Reproduce\r\nI talked to kmurray, who said he could reproduce this, so I assume it can be reproduced with any architecture. I was using a vanilla length 4 wire example.\r\n\r\n"}}
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