{"push_id":2777690682,"size":21,"distinct_size":21,"ref":"refs/heads/master","head":"bf6c82eac58a3f2a267032a0efc7e25bf8e97830","before":"97fb547f4b91b83d451ce97766ebc9e6469f27cf","commits":[{"sha":"be633c47deedd5e30f07329dc5c3b3ac721a87d5","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"linux-user/mmap.c: handle invalid len maps correctly\n\nI've slightly re-organised the check to more closely match the\nsequence that the kernel uses in do_mmap(). We check for both the zero\ncase (EINVAL) and the overflow length case (ENOMEM).\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nCc: umarcor <1783362@bugs.launchpad.net>\nReviewed-by: Laurent Vivier <laurent@vivier.eu>\nMessage-Id: <20180730134321.19898-2-alex.bennee@linaro.org>\nSigned-off-by: Laurent Vivier <laurent@vivier.eu>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/be633c47deedd5e30f07329dc5c3b3ac721a87d5"},{"sha":"3db4648f7efd200ba35a0ff2861cdb03f278d10e","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"tests: add check_invalid_maps to test-mmap\n\nThis adds a test to make sure we fail properly for a 0 length mmap.\nThere are most likely other failure conditions we should also check.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nCc: umarcor <1783362@bugs.launchpad.net>\nMessage-Id: <20180730134321.19898-3-alex.bennee@linaro.org>\nSigned-off-by: Laurent Vivier <laurent@vivier.eu>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/3db4648f7efd200ba35a0ff2861cdb03f278d10e"},{"sha":"f2eba544d4a322232afffce65a5286a8697a6162","author":{"name":"Shivaprasad G Bhat","email":"90f736271cc61454bf7410f17f3d154578105aa0@linux.vnet.ibm.com"},"message":"linux-user: ppc64: don't use volatile register during safe_syscall\n\nr11 is a volatile register on PPC as per calling conventions.\nThe safe_syscall code uses it to check if the signal_pending\nis set during the safe_syscall. When a syscall is interrupted\non return from signal handling, the r11 might be corrupted\nbefore we retry the syscall leading to a crash. The registers\nr0-r13 are not to be used here as they have\nvolatile/designated/reserved usages.\n\nChange the code to use r14 which is non-volatile.\nUse SP+16 which is a slot for LR, for save/restore of previous value\nof r14. SP+16 can be used, as LR is preserved across the syscall.\n\nSteps to reproduce:\nOn PPC host, issue `qemu-x86_64 /usr/bin/cc -E -`\nAttempt Ctrl-C, the issue is reproduced.\n\nReference:\nhttps://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html#REG\nhttps://openpowerfoundation.org/wp-content/uploads/2016/03/ABI64BitOpenPOWERv1.1_16July2015_pub4.pdf\n\nSigned-off-by: Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com>\nTested-by: Richard Henderson <richard.henderson@linaro.org>\nTested-by: Laurent Vivier <laurent@vivier.eu>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Laurent Vivier <laurent@vivier.eu>\nMessage-Id: <153301568965.30312.10498134581068746871.stgit@dhcp-9-109-246-16>\nSigned-off-by: Laurent Vivier <laurent@vivier.eu>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/f2eba544d4a322232afffce65a5286a8697a6162"},{"sha":"46f75a816ef48cb2849670e6bcaa839155b2d6fc","author":{"name":"Marc-André Lureau","email":"a6f2b960a4aca61381fc650a67901b2ac8e83e6d@redhat.com"},"message":"monitor: temporary fix for dead-lock on event recursion\n\nWith a Spice port chardev, it is possible to reenter\nmonitor_qapi_event_queue() (when the client disconnects for\nexample). This will dead-lock on monitor_lock.\n\nInstead, use some TLS variables to check for recursion and queue the\nevents.\n\nFixes:\n (gdb) bt\n #0  0x00007fa69e7217fd in __lll_lock_wait () at /lib64/libpthread.so.0\n #1  0x00007fa69e71acf4 in pthread_mutex_lock () at /lib64/libpthread.so.0\n #2  0x0000563303567619 in qemu_mutex_lock_impl (mutex=0x563303d3e220 <monitor_lock>, file=0x5633036589a8 \"/home/elmarco/src/qq/monitor.c\", line=645) at /home/elmarco/src/qq/util/qemu-thread-posix.c:66\n #3  0x0000563302fa6c25 in monitor_qapi_event_queue (event=QAPI_EVENT_SPICE_DISCONNECTED, qdict=0x56330602bde0, errp=0x7ffc6ab5e728) at /home/elmarco/src/qq/monitor.c:645\n #4  0x0000563303549aca in qapi_event_send_spice_disconnected (server=0x563305afd630, client=0x563305745360, errp=0x563303d8d0f0 <error_abort>) at qapi/qapi-events-ui.c:149\n #5  0x00005633033e600f in channel_event (event=3, info=0x5633061b0050) at /home/elmarco/src/qq/ui/spice-core.c:235\n #6  0x00007fa69f6c86bb in reds_handle_channel_event (reds=<optimized out>, event=3, info=0x5633061b0050) at reds.c:316\n #7  0x00007fa69f6b193b in main_dispatcher_self_handle_channel_event (info=0x5633061b0050, event=3, self=0x563304e088c0) at main-dispatcher.c:197\n #8  0x00007fa69f6b193b in main_dispatcher_channel_event (self=0x563304e088c0, event=event@entry=3, info=0x5633061b0050) at main-dispatcher.c:197\n #9  0x00007fa69f6d0833 in red_stream_push_channel_event (s=s@entry=0x563305ad8f50, event=event@entry=3) at red-stream.c:414\n #10 0x00007fa69f6d086b in red_stream_free (s=0x563305ad8f50) at red-stream.c:388\n #11 0x00007fa69f6b7ddc in red_channel_client_finalize (object=0x563304df2360) at red-channel-client.c:347\n #12 0x00007fa6a56b7fb9 in g_object_unref () at /lib64/libgobject-2.0.so.0\n #13 0x00007fa69f6ba212 in red_channel_client_push (rcc=0x563304df2360) at red-channel-client.c:1341\n #14 0x00007fa69f68b259 in red_char_device_send_msg_to_client (client=<optimized out>, msg=0x5633059b6310, dev=0x563304e08bc0) at char-device.c:305\n #15 0x00007fa69f68b259 in red_char_device_send_msg_to_clients (msg=0x5633059b6310, dev=0x563304e08bc0) at char-device.c:305\n #16 0x00007fa69f68b259 in red_char_device_read_from_device (dev=0x563304e08bc0) at char-device.c:353\n #17 0x000056330317d01d in spice_chr_write (chr=0x563304cafe20, buf=0x563304cc50b0 \"{\\\"timestamp\\\": {\\\"seconds\\\": 1532944763, \\\"microseconds\\\": 326636}, \\\"event\\\": \\\"SHUTDOWN\\\", \\\"data\\\": {\\\"guest\\\": false}}\\r\\n\", len=111) at /home/elmarco/src/qq/chardev/spice.c:199\n #18 0x00005633034deee7 in qemu_chr_write_buffer (s=0x563304cafe20, buf=0x563304cc50b0 \"{\\\"timestamp\\\": {\\\"seconds\\\": 1532944763, \\\"microseconds\\\": 326636}, \\\"event\\\": \\\"SHUTDOWN\\\", \\\"data\\\": {\\\"guest\\\": false}}\\r\\n\", len=111, offset=0x7ffc6ab5ea70, write_all=false) at /home/elmarco/src/qq/chardev/char.c:112\n #19 0x00005633034df054 in qemu_chr_write (s=0x563304cafe20, buf=0x563304cc50b0 \"{\\\"timestamp\\\": {\\\"seconds\\\": 1532944763, \\\"microseconds\\\": 326636}, \\\"event\\\": \\\"SHUTDOWN\\\", \\\"data\\\": {\\\"guest\\\": false}}\\r\\n\", len=111, write_all=false) at /home/elmarco/src/qq/chardev/char.c:147\n #20 0x00005633034e1e13 in qemu_chr_fe_write (be=0x563304dbb800, buf=0x563304cc50b0 \"{\\\"timestamp\\\": {\\\"seconds\\\": 1532944763, \\\"microseconds\\\": 326636}, \\\"event\\\": \\\"SHUTDOWN\\\", \\\"data\\\": {\\\"guest\\\": false}}\\r\\n\", len=111) at /home/elmarco/src/qq/chardev/char-fe.c:42\n #21 0x0000563302fa6334 in monitor_flush_locked (mon=0x563304dbb800) at /home/elmarco/src/qq/monitor.c:425\n #22 0x0000563302fa6520 in monitor_puts (mon=0x563304dbb800, str=0x563305de7e9e \"\") at /home/elmarco/src/qq/monitor.c:468\n #23 0x0000563302fa680c in qmp_send_response (mon=0x563304dbb800, rsp=0x563304df5730) at /home/elmarco/src/qq/monitor.c:517\n #24 0x0000563302fa6905 in qmp_queue_response (mon=0x563304dbb800, rsp=0x563304df5730) at /home/elmarco/src/qq/monitor.c:538\n #25 0x0000563302fa6b5b in monitor_qapi_event_emit (event=QAPI_EVENT_SHUTDOWN, qdict=0x563304df5730) at /home/elmarco/src/qq/monitor.c:624\n #26 0x0000563302fa6c4b in monitor_qapi_event_queue (event=QAPI_EVENT_SHUTDOWN, qdict=0x563304df5730, errp=0x7ffc6ab5ed00) at /home/elmarco/src/qq/monitor.c:649\n #27 0x0000563303548cce in qapi_event_send_shutdown (guest=false, errp=0x563303d8d0f0 <error_abort>) at qapi/qapi-events-run-state.c:58\n #28 0x000056330313bcd7 in main_loop_should_exit () at /home/elmarco/src/qq/vl.c:1822\n #29 0x000056330313bde3 in main_loop () at /home/elmarco/src/qq/vl.c:1862\n #30 0x0000563303143781 in main (argc=3, argv=0x7ffc6ab5f068, envp=0x7ffc6ab5f088) at /home/elmarco/src/qq/vl.c:4644\n\nNote that error report is now moved to the first caller, which may\nreceive an error for a recursed event. This is probably fine (95% of\ncallers use &error_abort, the rest have NULL error and ignore it)\n\nSigned-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>\nMessage-Id: <20180731150144.14022-1-marcandre.lureau@redhat.com>\nReviewed-by: Markus Armbruster <armbru@redhat.com>\n[*_no_recurse renamed to *_no_reenter, local variables reordered]\nSigned-off-by: Markus Armbruster <armbru@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/46f75a816ef48cb2849670e6bcaa839155b2d6fc"},{"sha":"2aeefe1ea274e9a0ecbbac64e69c854c2c0b95e3","author":{"name":"Peter Maydell","email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org"},"message":"Update version for v3.0.0-rc3 release\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/2aeefe1ea274e9a0ecbbac64e69c854c2c0b95e3"},{"sha":"2727a8b8fe4f5f8339073960689f0981de33dc93","author":{"name":"Stefan Hajnoczi","email":"484520986196e4a799496429ce8a499eb6488adb@redhat.com"},"message":"hw/arm: make bitbanded IO optional on ARMv7-M\n\nSome ARM CPUs have bitbanded IO, a memory region that allows convenient\nbit access via 32-bit memory loads/stores.  This eliminates the need for\nread-modify-update instruction sequences.\n\nThis patch makes this optional feature an ARMv7MState qdev property,\nallowing boards to choose whether they want bitbanding or not.\n\nStatus of boards:\n * iotkit (Cortex M33), no bitband\n * mps2 (Cortex M3), bitband\n * msf2 (Cortex M3), bitband\n * stellaris (Cortex M3), bitband\n * stm32f205 (Cortex M3), bitband\n\nAs a side-effect of this patch, Peter Maydell noted that the Ethernet\ncontroller on mps2 board is now accessible.  Previously they were hidden\nby the bitband region (which does not exist on the real board).\n\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/2727a8b8fe4f5f8339073960689f0981de33dc93"},{"sha":"305147a58b0a317f7be9204a90ed5a69814dd461","author":{"name":"Stefan Hajnoczi","email":"484520986196e4a799496429ce8a499eb6488adb@redhat.com"},"message":"target/arm: add \"cortex-m0\" CPU model\n\nDefine a \"cortex-m0\" ARMv6-M CPU model.\n\nMost of the register reset values set by other CPU models are not\nrelevant for the cut-down ARMv6-M architecture.\n\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/305147a58b0a317f7be9204a90ed5a69814dd461"},{"sha":"0ddbea0d0beceac4da744f3b9e8976e62f5b84aa","author":{"name":"Stefan Hajnoczi","email":"484520986196e4a799496429ce8a499eb6488adb@redhat.com"},"message":"loader: extract rom_free() function\n\nThe next patch will need to free a rom.  There is already code to do\nthis in rom_add_file().\n\nNote that rom_add_file() uses:\n\n  rom = g_malloc0(sizeof(*rom));\n  ...\n  if (rom->fw_dir) {\n      g_free(rom->fw_dir);\n      g_free(rom->fw_file);\n  }\n\nThe conditional is unnecessary since g_free(NULL) is a no-op.\n\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/0ddbea0d0beceac4da744f3b9e8976e62f5b84aa"},{"sha":"7de0d43d6dbf9b6722f624aec3b2b86eb3f6e711","author":{"name":"Stefan Hajnoczi","email":"484520986196e4a799496429ce8a499eb6488adb@redhat.com"},"message":"loader: add rom transaction API\n\nImage file loaders may add a series of roms.  If an error occurs partway\nthrough loading there is no easy way to drop previously added roms.\n\nThis patch adds a transaction mechanism that works like this:\n\n  rom_transaction_begin();\n  ...call rom_add_*()...\n  rom_transaction_end(ok);\n\nIf ok is false then roms added in this transaction are dropped.\n\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/7de0d43d6dbf9b6722f624aec3b2b86eb3f6e711"},{"sha":"91426d13368ea37e032adf5a46489eae3794389e","author":{"name":"Su Hang","email":"cb8f95c7940a45032abc5b406beb3413bc487bf4@mails.ucas.ac.cn"},"message":"loader: Implement .hex file loader\n\nThis patch adds Intel Hexadecimal Object File format support to the\ngeneric loader device.  The file format specification is available here:\nhttp://www.piclist.com/techref/fileext/hex/intel.htm\n\nThis file format is often used with microcontrollers such as the\nmicro:bit, Arduino, STM32, etc.  Users expect to be able to run .hex\nfiles directly with without first converting them to ELF.  Most\nmicro:bit code is developed in web-based IDEs without direct user access\nto binutils so it is important for QEMU to handle this file format\nnatively.\n\nSigned-off-by: Su Hang <suhang16@mails.ucas.ac.cn>\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/91426d13368ea37e032adf5a46489eae3794389e"},{"sha":"bbc8da04a1cf2740a3ac84638a572e8b398a088f","author":{"name":"Su Hang","email":"cb8f95c7940a45032abc5b406beb3413bc487bf4@mails.ucas.ac.cn"},"message":"Add QTest testcase for the Intel Hexadecimal\n\n'test.hex' file is a bare metal ARM software stored in Hexadecimal\nObject Format. When it's loaded by QEMU, it will print \"Hello world!\\n\"\non console.\n\n`pre_store` array in 'hexloader-test.c' file, stores the binary format\nof 'test.hex' file, which is used to verify correctness.\n\nReviewed-by: Stefan Hajnoczi <stefanha@redhat.com>\nSuggested-by: Steffen Gortz <qemu.ml@steffen-goertz.de>\nSuggested-by: Stefan Hajnoczi <stefanha@redhat.com>\nSigned-off-by: Su Hang <suhang16@mails.ucas.ac.cn>\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/bbc8da04a1cf2740a3ac84638a572e8b398a088f"},{"sha":"4ca70fb0c5bb19d0b62070c2cf3bae76a39882d9","author":{"name":"Joel Stanley","email":"4816dabf8db1bc6cac35b3a24cab2ff844b5b0c7@jms.id.au"},"message":"MAINTAINERS: Add NRF51 entry\n\nThis contains the NRF51, and the machine that uses it, the BBC\nmicro:bit.\n\nReviewed-by: Stefan Hajnoczi <stefanha@redhat.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/4ca70fb0c5bb19d0b62070c2cf3bae76a39882d9"},{"sha":"f1c7ab85a4e9e719b27738f26b6c2254c906d521","author":{"name":"Joel Stanley","email":"4816dabf8db1bc6cac35b3a24cab2ff844b5b0c7@jms.id.au"},"message":"arm: Add Nordic Semiconductor nRF51 SoC\n\nThe nRF51 is a Cortex-M0 microcontroller with an on-board radio module,\nplus other common ARM SoC peripherals.\n\n http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf\n\nThis defines a basic model of the CPU and memory, with no peripherals\nimplemented at this stage.\n\nSigned-off-by: Joel Stanley <joel@jms.id.au>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/f1c7ab85a4e9e719b27738f26b6c2254c906d521"},{"sha":"8ee93d4a7512fe28899e535f7bc1fbfe0a4d77e3","author":{"name":"Joel Stanley","email":"4816dabf8db1bc6cac35b3a24cab2ff844b5b0c7@jms.id.au"},"message":"arm: Add BBC micro:bit machine\n\nThis adds the base for a machine model of the BBC micro:bit:\n\n  https://en.wikipedia.org/wiki/Micro_Bit\n\nThis is a system with a nRF51 SoC containing the main processor, with\nvarious peripherals on board.\n\nReviewed-by: Stefan Hajnoczi <stefanha@redhat.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/8ee93d4a7512fe28899e535f7bc1fbfe0a4d77e3"},{"sha":"07ca6f5b7d729f0978f6ebcaf6d6f76b7f2ff640","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"hw/misc/nrf51_rng: Add NRF51 random number generator peripheral\n\nAdd a model of the NRF51 random number generator peripheral.\nThis is a simple random generator that continuously generates\nnew random values after startup.\n\nReference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf\n\nSigned-off-by: Steffen Görtz <contrib@steffen-goertz.de>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/07ca6f5b7d729f0978f6ebcaf6d6f76b7f2ff640"},{"sha":"5a505735d141db7f6e0df66c01dbc3822f770ea3","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories\n\nThe nRF51 contains three regions of non-volatile memory (NVM):\n- CODE (R/W): contains code\n- FICR (R): Factory information like code size, chip id etc.\n- UICR (R/W): Changeable configuration data. Lock bits, Code\n  protection configuration, Bootloader address, Nordic SoftRadio\n  configuration, Firmware configuration.\n\nRead and write access to the memories is managed by the\nNon-volatile memory controller.\n\nMemory schema:\n [ CPU ] -+- [ NVM, either FICR, UICR or CODE ]\n          |      |\n          \\- [ NVMC ]","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/5a505735d141db7f6e0df66c01dbc3822f770ea3"},{"sha":"da6da399b057a4a49daa80c326091c28bc4cc21c","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"tests: Add bbc:microbit / nRF51 test suite\n\nThe microbit-test includes tests for the nRF51 NVMC\nperipheral and will host future nRF51 peripheral tests\nand board-level bbc:microbit tests.\n\nSigned-off-by: Steffen Görtz <contrib@steffen-goertz.de>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/da6da399b057a4a49daa80c326091c28bc4cc21c"},{"sha":"c6f02a9abf421dbaa563eabda1768d714d7033c6","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral\n\nThis adds a model of the nRF51 GPIO peripheral.\n\nReference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf\n\nThe nRF51 series microcontrollers support up to 32 GPIO pins in various configurations.\nThe pins can be used as input pins with pull-ups or pull-down.\nFurthermore, three different output driver modes per level are\navailable (disconnected, standard, high-current).\n\nThe GPIO-Peripheral has a mechanism for detecting level changes which is\nnot featured in this model.\n\nSigned-off-by: Steffen Görtz <contrib@steffen-goertz.de>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/c6f02a9abf421dbaa563eabda1768d714d7033c6"},{"sha":"c5d7186fdaaa85b37cbe43f5a8ccc0bef2a1913a","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"tests/microbit-test: Add Tests for nRF51 GPIO\n\nThe test suite for the nRF51 GPIO peripheral for now\nonly tests initial state. Additionally a set of\ntests testing an implementation detail of the model\nare included.\n\nSigned-off-by: Steffen Görtz <contrib@steffen-goertz.de>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/c5d7186fdaaa85b37cbe43f5a8ccc0bef2a1913a"},{"sha":"72e432af816dbac3bd3107dfa5263846a93cc76c","author":{"name":"Steffen Görtz","email":"9e4dd76ad9b38f33fdb417a4c01935958d5acd2a@steffen-goertz.de"},"message":"hw/timer/nrf51_timer: Add nRF51 Timer peripheral\n\nThis patch adds the model for the nRF51 timer peripheral.\nCurrently, only the TIMER mode is implemented.\n\nSigned-off-by: Steffen Görtz <contrib@steffen-goertz.de>","distinct":true,"url":"https://api.github.com/repos/douzepouze/qemu/commits/72e432af816dbac3bd3107dfa5263846a93cc76c"}]}
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