{"comment":{"url":"https://api.github.com/repos/jrrk/ariane/comments/27447082","html_url":"https://github.com/jrrk/ariane/commit/7b1dfb993f5b4d2758fd04777d51fe993226123d#commitcomment-27447082","id":27447082,"user":{"login":"zarubaf","id":199415,"avatar_url":"https://avatars3.githubusercontent.com/u/199415?v=4","gravatar_id":"","url":"https://api.github.com/users/zarubaf","html_url":"https://github.com/zarubaf","followers_url":"https://api.github.com/users/zarubaf/followers","following_url":"https://api.github.com/users/zarubaf/following{/other_user}","gists_url":"https://api.github.com/users/zarubaf/gists{/gist_id}","starred_url":"https://api.github.com/users/zarubaf/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/zarubaf/subscriptions","organizations_url":"https://api.github.com/users/zarubaf/orgs","repos_url":"https://api.github.com/users/zarubaf/repos","events_url":"https://api.github.com/users/zarubaf/events{/privacy}","received_events_url":"https://api.github.com/users/zarubaf/received_events","type":"User","site_admin":false},"position":null,"line":null,"path":null,"commit_id":"7b1dfb993f5b4d2758fd04777d51fe993226123d","created_at":"2018-02-09T09:57:01Z","updated_at":"2018-02-09T09:57:01Z","author_association":"NONE","body":"Yes indeed I am lacking information on this block. Basically it is similar to what has been done for our other cores (the documentation is on our projects website): it is a memory mapped set of registers which can be accessed via a standard bus (AXI for example). I need to invest some time next week to lay out the register map.\r\n\r\nWe will hopefully also release the necessary software and hardware quite soon. \r\n\r\nNevertheless, I've had a look at the RISC-V debug spec the other day and have to admit that I am tempted to implement. Mostly to reuse their software environment. What is your opinion on the offficial debug spec?\r\n\r\nBest, Florian"}}
{"actor":{"display_login":"zarubaf"}}