{"action":"created","issue":{"url":"https://api.github.com/repos/sinara-hw/Urukul/issues/16","repository_url":"https://api.github.com/repos/sinara-hw/Urukul","labels_url":"https://api.github.com/repos/sinara-hw/Urukul/issues/16/labels{/name}","comments_url":"https://api.github.com/repos/sinara-hw/Urukul/issues/16/comments","events_url":"https://api.github.com/repos/sinara-hw/Urukul/issues/16/events","html_url":"https://github.com/sinara-hw/Urukul/issues/16","id":377877438,"node_id":"MDU6SXNzdWUzNzc4Nzc0Mzg=","number":16,"title":"SYNC_IN jitter","user":{"login":"jordens","id":1338946,"node_id":"MDQ6VXNlcjEzMzg5NDY=","avatar_url":"https://avatars1.githubusercontent.com/u/1338946?v=4","gravatar_id":"","url":"https://api.github.com/users/jordens","html_url":"https://github.com/jordens","followers_url":"https://api.github.com/users/jordens/followers","following_url":"https://api.github.com/users/jordens/following{/other_user}","gists_url":"https://api.github.com/users/jordens/gists{/gist_id}","starred_url":"https://api.github.com/users/jordens/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jordens/subscriptions","organizations_url":"https://api.github.com/users/jordens/orgs","repos_url":"https://api.github.com/users/jordens/repos","events_url":"https://api.github.com/users/jordens/events{/privacy}","received_events_url":"https://api.github.com/users/jordens/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":16,"created_at":"2018-11-06T14:43:27Z","updated_at":"2018-12-04T10:55:30Z","closed_at":null,"author_association":"MEMBER","body":"The jitter on the SYNC_IN signal from Kasli to the AD9910 (throught the LVDS buffers and the fanout) is  very high in some caes (the tester setup connected to the buildbot). \r\n\r\nAt validation delay 1 (hold and setup margin 1 tap) the window is just 2 taps wide (a tap is about 75 ps).\r\nhttp://buildbot.m-labs.hk/builders/artiq/builds/2669/steps/python_unittest_2/logs/stdio\r\n\r\nThis is the SMP_ERR matrix on tester, rows are increasing validation delay, columns are SYNC_IN delay on the AD9910.:\r\n```\r\n[1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n```\r\nThere also seems to be some bounce around the edges (top row).\r\n\r\nOn the systems I have here I get about 5-6 tap wide windows at validation delay 1. That's not stellar but OK.\r\nWhen using the SYNC signal on board from the first DDS, the window at validation delay 1 is 8 taps wide on tester, 8-9 taps here.\r\nAssuming equal tap delay for the validation delays and the SYNC_IN delays, the theoretically best case is validation delay 4 and a window width of ~4 or a validation delay of 1 and a window width of ~10 (i.e. SYNC_IN delay periodicity minus twice the validation delay).\r\n\r\n```\r\n[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0]\r\n[1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0]\r\n[1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0]\r\n[1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0]\r\n[1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]\r\n```\r\n\r\nIn both cases Kasli/v1.1 and Urukul-AD9910/v1.3, connected via MMCX to Kasli-J1.\r\n\r\nThe jitter seems to come in part from Urukul and in part (the larger part) from Kasli. And it varies between setups.\r\nI changed a couple things (see the artiq changelog) to optimize jitter on the RTIO clock but there was little effect. From Vivado the max peak-peak jitter on the clock driving the SYNC output buffer in the FPGA is ~90ps.\r\nI tried running the SYNC fanout from the supposedly quieter P1V8A rail but that doesn't seem to work at all.\r\n\r\n@gkasprow @marmeladapk could you have a look at the jitter on SYNC_IN (EEM0:7, before and after the sync fanout, compared to the Kasli MMCX clock)?\r\n\r\n@cjbe @klickverbot When you were playing with SYNC, did you look at SMP_ERR? How did you select the SYNC_IN delay and the validation delay? Did you scan them?\r\n\r\nc.f. m-labs/artiq#1143"},"comment":{"url":"https://api.github.com/repos/sinara-hw/Urukul/issues/comments/444059163","html_url":"https://github.com/sinara-hw/Urukul/issues/16#issuecomment-444059163","issue_url":"https://api.github.com/repos/sinara-hw/Urukul/issues/16","id":444059163,"node_id":"MDEyOklzc3VlQ29tbWVudDQ0NDA1OTE2Mw==","user":{"login":"gkasprow","id":4325054,"node_id":"MDQ6VXNlcjQzMjUwNTQ=","avatar_url":"https://avatars3.githubusercontent.com/u/4325054?v=4","gravatar_id":"","url":"https://api.github.com/users/gkasprow","html_url":"https://github.com/gkasprow","followers_url":"https://api.github.com/users/gkasprow/followers","following_url":"https://api.github.com/users/gkasprow/following{/other_user}","gists_url":"https://api.github.com/users/gkasprow/gists{/gist_id}","starred_url":"https://api.github.com/users/gkasprow/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/gkasprow/subscriptions","organizations_url":"https://api.github.com/users/gkasprow/orgs","repos_url":"https://api.github.com/users/gkasprow/repos","events_url":"https://api.github.com/users/gkasprow/events{/privacy}","received_events_url":"https://api.github.com/users/gkasprow/received_events","type":"User","site_admin":false},"created_at":"2018-12-04T10:55:30Z","updated_at":"2018-12-04T10:55:30Z","author_association":"MEMBER","body":"You can try with FSEN pin state on LVDS receivers. It may affect the jitter."}}
{"actor":{"display_login":"gkasprow"}}