{"push_id":2751950961,"size":6,"distinct_size":6,"ref":"refs/heads/master","head":"09b424ebf978bf0517445a514ea149734c17b35b","before":"2fd17305485ff1179c6b607de24bd4064dbe73fd","commits":[{"sha":"17c9009a8f7f29de21632cce17f7901ac3b8a2ec","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: pvmmio optimization for plane update\n\nIt is performance optimization to reduce plane related register trap\ncounter. When update plane, multiple plane related registers are updated\ntogether, optimize it to firstly cache all register values in share page,\nthen only PLANE_SURF register writing is trapped. Plane pvmmio level is\nPVMMIO_PLANE_UPDATE.\nPatch for both SOS and UOS.\n\nV2: add memset tmp_plane to be more safer and add more commit description\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/17c9009a8f7f29de21632cce17f7901ac3b8a2ec"},{"sha":"53aaf8f20bf6e2827c3dcd53f4c40ee82ff23605","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: handling pvmmio update of plane registers in GVT-g\n\nWhen pvmmio level PVMMIO_PLANE_UPDATE is enabled, need handle multiple\nplane related registers updating together when PLANE_SURF is traped.\nsos only patch.\n\nV2: restore sequence of skl_plane_mmio_write/skl_plane_mmio_write and\nskl_plane_surf_write, while need add extra declarations.\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/53aaf8f20bf6e2827c3dcd53f4c40ee82ff23605"},{"sha":"d47ea3371efa1b340e04223ea2aaeb15d82f43e9","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: enable plane update pvmmio through enable_pvmmio param\n\nplane update pvmmio level is 0x2, need set it in enable_pvmmio for both SOS\nand UOS kernel driver.\nPatch for both SOS and UOS.\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/d47ea3371efa1b340e04223ea2aaeb15d82f43e9"},{"sha":"524a1db16f92b27ae4a168dd1d56b74c6120bc40","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: pvmmio optimization for plane wm register update\n\nIt is performance optimization to reduce plane wm related register trap\ncounter. When update plane wm, multiple plane wm related registers are\nupdated together, optimize it to firstly cache all register values in\nshare page, then only PLANE_NV12_BUF_CFG register writing is trapped.\nPlane pvmmio level is PVMMIO_PLANE_WM_UPDATE.\nIf plane restriction feature is enabled, trap handlers for plane wm\nrelated register are null, then directly return.\nPatch for both SOS and UOS.\n\nV2: when plane restriction feature is enabled, SOS trap handlers for\nplane wm related registers are null, then don't trap\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/524a1db16f92b27ae4a168dd1d56b74c6120bc40"},{"sha":"3f467bc95b60fbf96a12089dbb20ff3f238965a7","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: handling pvmmio update of plane wm registers in GVT-g\n\nWhen pvmmio level PVMMIO_PLANE_WM_UPDATE is enabled, need handle multiple\nplane wm related registers updating when PLANE_NV12_BUF_CFG writing is\ntraped.\nsos only patch.\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/3f467bc95b60fbf96a12089dbb20ff3f238965a7"},{"sha":"09b424ebf978bf0517445a514ea149734c17b35b","author":{"name":"Fei Jiang","email":"61ddc1defa6d1f5178eb7cba64ca1c6499d7f764@intel.com"},"message":"drm/i915/gvt: enable plane wm pvmmio level through enable_pvmmio param\n\nplane wm update pvmmio level is 0x4, need set it in enable_pvmmio for both\nSOS and UOS kernel driver.\nPatch for both SOS and UOS.\n\nV2: use PVMMIO_PLANE_WM_UPDATE bit definition to improve readability\n\nSigned-off-by: Fei Jiang <fei.jiang@intel.com>\nReviewed-by: Min He <min.he@intel.com>\nReviewed-by: Zhao Yakui <yakui.zhao@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-kernel/commits/09b424ebf978bf0517445a514ea149734c17b35b"}]}
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