{"push_id":2868345127,"size":5,"distinct_size":5,"ref":"refs/heads/vanilla-legic","head":"a125f2ce71da2da738a4513d3a81b34cc1be4a10","before":"20912c8a339bf57394173115e6b63fcf45122304","commits":[{"sha":"f3c8131a0df4bd1d5cf39b886ba7c355efc2430c","author":{"name":"Oleg Moiseenko","email":"d3ca68b5d91b171bb437d2cfb153bff077e059d9@gmail.com"},"message":"update travis config (#662)","distinct":true,"url":"https://api.github.com/repos/drandreas/proxmark3/commits/f3c8131a0df4bd1d5cf39b886ba7c355efc2430c"},{"sha":"6e3d8d671ac59e308c2ec83136890dc1af2edc65","author":{"name":"Oleg Moiseenko","email":"d3ca68b5d91b171bb437d2cfb153bff077e059d9@gmail.com"},"message":"implement argtable in hf 14a apdu (#490)\n\n* added `hf 14a reader` to source and added functionality to exec empty commands\r\n* added `hf 14a raw`\r\n* added samples to command's help\r\n* added some help\r\n* added changelog\r\n* update to new argtable3 --- https://github.com/argtable/argtable3\r\n* changed included getopt to `https://github.com/freebsd/freebsd/blob/master/include/getopt.h` (getopt from freebsd with simplified BSD license)","distinct":true,"url":"https://api.github.com/repos/drandreas/proxmark3/commits/6e3d8d671ac59e308c2ec83136890dc1af2edc65"},{"sha":"1b902aa01afa39ff413b74142cd56d092b4500a1","author":{"name":"AntiCat","email":"0fc5e9a3efdccddc0609e6126edbb5fa87535523@anticat.ch"},"message":"Legic Tag Simulator (#666)\n\n* FPGA Hi-Simulate: Formatted code\r\n* FPGA Hi-Simulate: Fixed documantation\r\n* FPGA Hi-Simulate: Freed up 4 LUTs\r\n* FPGA Hi-Simulate: Added 212kHz SSP-Clock option\r\n* Legic: Moved card simulator into separate file & cleaned interface.\r\nReader and card simulation have almost no common code. Moreover the sim\r\nuses an SSP Clock at 212kHz for all timings to prevent any drifting from\r\nthe PRNG. This clock speed is not available in reader simulation mode (SSP\r\nruns at up to 3.4MHz, and changes speed between TX and RX). For these\r\nreasons having the code in separate files makes it significantly cleaner.\r\n* Legic: Implemented RX and TX for card simulation\r\n* Legic: Implemented setup phase for card simulation\r\n* Legic: Implemented read command for card simulation\r\n* Legic: Implemented write command for card simulation","distinct":true,"url":"https://api.github.com/repos/drandreas/proxmark3/commits/1b902aa01afa39ff413b74142cd56d092b4500a1"},{"sha":"53edb044c0dfe82fd9d0a0e0d3444a51ebe358f4","author":{"name":"wllm-rbnt","email":"75733cfe400c91bc603e49ae2d70494d2137a4e9@conostix.com"},"message":"Allow clean Legic simulation exit without button press (#668)","distinct":true,"url":"https://api.github.com/repos/drandreas/proxmark3/commits/53edb044c0dfe82fd9d0a0e0d3444a51ebe358f4"},{"sha":"a125f2ce71da2da738a4513d3a81b34cc1be4a10","author":{"name":"AntiCat","email":"64b2b6d12bfe4baae7dad3d018f8cbf6b0e7a044@anticat.ch"},"message":"Update CHANGELOG.md","distinct":true,"url":"https://api.github.com/repos/drandreas/proxmark3/commits/a125f2ce71da2da738a4513d3a81b34cc1be4a10"}]}
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