{"push_id":3161988960,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"ef03385f424bb2e4416b8bf0d46d3561bb16e40e","before":"a5113d922d5a0fc7f6a90c0f75c51c79bba78d88","commits":[{"sha":"ef03385f424bb2e4416b8bf0d46d3561bb16e40e","author":{"name":"Sainath Grandhi","email":"69dd364cc32a6cbaecda1f7c063884ee546948e4@intel.com"},"message":"hv: Write Buffer Flush - VT-d\n\nThis patch does the following changes\nAccording to VT-d spec Section 6.8 \"Write Buffer Flushing\" DRAM write buffers\nare flushed implicitly upon Remapping Hardware Caches Invalidation even on\nplatforms that set RWBF to 1 in capability register. So removed write buffer\nflushing as current ACRN issues cache invalidation commands in all cases.\n\nTracked-On: #1855\nSigned-off-by: Sainath Grandhi <sainath.grandhi@intel.com>","distinct":true,"url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/commits/ef03385f424bb2e4416b8bf0d46d3561bb16e40e"}]}
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