{"push_id":2906158527,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"503ca1ae93b0693775c0ed0496deff10d6f85e30","before":"9fa607f6149da2da811107375c356a56b68e9c41","commits":[{"sha":"503ca1ae93b0693775c0ed0496deff10d6f85e30","author":{"name":"Daniil Fukalov","email":"47f326c161e6edcdde165264aa04916b3cd2f3f5@amd.com"},"message":"[RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled\n\nFor the AMDGPU target if a MBB contains exec mask restore preamble, SplitEditor may get state when it cannot insert a spill instruction.\n\nE.g. for a MIR\n\nbb.100:\n    %1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc, implicit $exec\nand if the regalloc will try to allocate a virtreg to the physreg already assigned to virtreg %1, it should insert spill instruction before the S_OR_SAVEEXEC_B64 instruction.\nBut it is not possible since can generate incorrect code in terms of exec mask.\n\nThe change makes regalloc to ignore such physreg candidates.\n\nReviewed By: rampitec\n\nDifferential Revision: https://reviews.llvm.org/D52052","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/503ca1ae93b0693775c0ed0496deff10d6f85e30"}]}
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