{"action":"created","issue":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/380","repository_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing","labels_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/380/labels{/name}","comments_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/380/comments","events_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/380/events","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/380","id":347886702,"node_id":"MDU6SXNzdWUzNDc4ODY3MDI=","number":380,"title":"Timing and switch block error in VTR 8. 0","user":{"login":"qaarah","id":40689621,"node_id":"MDQ6VXNlcjQwNjg5NjIx","avatar_url":"https://avatars2.githubusercontent.com/u/40689621?v=4","gravatar_id":"","url":"https://api.github.com/users/qaarah","html_url":"https://github.com/qaarah","followers_url":"https://api.github.com/users/qaarah/followers","following_url":"https://api.github.com/users/qaarah/following{/other_user}","gists_url":"https://api.github.com/users/qaarah/gists{/gist_id}","starred_url":"https://api.github.com/users/qaarah/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/qaarah/subscriptions","organizations_url":"https://api.github.com/users/qaarah/orgs","repos_url":"https://api.github.com/users/qaarah/repos","events_url":"https://api.github.com/users/qaarah/events{/privacy}","received_events_url":"https://api.github.com/users/qaarah/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":4,"created_at":"2018-08-06T11:33:55Z","updated_at":"2018-08-21T16:32:09Z","closed_at":"2018-08-21T16:00:54Z","author_association":"NONE","body":"Hi,\r\nI am trying to palce and route using VPR the blif generated by yosys (synth_ice40). I face the following error.\r\nArchitecture file: sample_arch.xml\r\nCircuit name: Example_LUT\r\n\r\nWarning 1: Model 'multiply' input port 'b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 2: Model 'multiply' input port 'a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 3: Model 'multiply' output port 'out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\r\nWarning 4: Model 'single_port_ram' input port 'data' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 5: Model 'single_port_ram' input port 'addr' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 6: Model 'single_port_ram' input port 'we' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 7: Model 'single_port_ram' output port 'out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\r\nWarning 8: Model 'dual_port_ram' input port 'data2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 9: Model 'dual_port_ram' input port 'data1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 10: Model 'dual_port_ram' input port 'addr2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 11: Model 'dual_port_ram' input port 'addr1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 12: Model 'dual_port_ram' input port 'we2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 13: Model 'dual_port_ram' input port 'we1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\r\nWarning 14: Model 'dual_port_ram' output port 'out2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\r\nWarning 15: Model 'dual_port_ram' output port 'out1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\r\nError 1: sample_arch.xml:129 Unexpected attribute 'auto' found on node 'layout'.\r\nWhen I do solve this issue by giving new sample architecture provided on https://vtr-verilog-to-routing.readthedocs.io/en/latest/vpr/file_formats.html#fpga-architecture-xml, I  get the following error.\r\nError 1: Arch_VPR8.xml:94 Found 1 'timing' child node(s) of 'device' (expected 0). has been replaced with the <switch_block> tag. Please upgrade your architecture file.\r\nI also tried to play with switch_block but I do not know, what up-gradation is required. \r\nThanks"},"comment":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/comments/414737923","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/380#issuecomment-414737923","issue_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/380","id":414737923,"node_id":"MDEyOklzc3VlQ29tbWVudDQxNDczNzkyMw==","user":{"login":"qaarah","id":40689621,"node_id":"MDQ6VXNlcjQwNjg5NjIx","avatar_url":"https://avatars2.githubusercontent.com/u/40689621?v=4","gravatar_id":"","url":"https://api.github.com/users/qaarah","html_url":"https://github.com/qaarah","followers_url":"https://api.github.com/users/qaarah/followers","following_url":"https://api.github.com/users/qaarah/following{/other_user}","gists_url":"https://api.github.com/users/qaarah/gists{/gist_id}","starred_url":"https://api.github.com/users/qaarah/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/qaarah/subscriptions","organizations_url":"https://api.github.com/users/qaarah/orgs","repos_url":"https://api.github.com/users/qaarah/repos","events_url":"https://api.github.com/users/qaarah/events{/privacy}","received_events_url":"https://api.github.com/users/qaarah/received_events","type":"User","site_admin":false},"created_at":"2018-08-21T16:32:09Z","updated_at":"2018-08-21T16:32:09Z","author_association":"NONE","body":"Yes, That make sense. Got it. \r\nThanks\r\n"}}
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