{"push_id":2535908566,"size":424,"distinct_size":424,"ref":"refs/heads/llvm_master","head":"4d0342f0d936afa6485755b87ad8eef7ed0a86d7","before":"fef8b01d9b1a75def0ff6b5511f1e95e4437ba9e","commits":[{"sha":"b91ac890b2622ac90dbd62c74acf2430acb00dbe","author":{"name":"Francis Visoiu Mistrih","email":"7a95e7be7df2469ab0a6511684ac541d5b50df28@yahoo.com"},"message":"[CodeGen] Print user-friendly debug locations as MI comments\n\nIf available, print the file, line and column of the DebugLoc attached\nto the MachineInstr:\n\nMOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17\nrenamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17\n\nDifferential Revision: https://reviews.llvm.org/D45992\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330709 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/b91ac890b2622ac90dbd62c74acf2430acb00dbe"},{"sha":"ad168c349451f03369bdfc7959ee5fbc90c9ba3a","author":{"name":"Alexander Ivchenko","email":"2c04cd96101bf19c6b7b8726113da8b7d294b669@intel.com"},"message":"[X86] Replace action Promote with Expand for operation ISD::SINT_TO_FP\n\nSummary:\nIf attribute \"use-soft-float\"=\"true\" is set then X86ISelLowering.cpp sets\n'Promote' action for ISD::SINT_TO_FP operation on type i32.\n\nBut 'Promote' action is not proper in this case since lib function\n__floatsidf is available for casting from signed int to float type.\nThus Expand action is more suitable here.\n\nThe Expand action should be set for ISD::UINT_TO_FP for soft float as well.\n\nIf function attribute \"use-soft-float\"=\"true\" is set then infinite looping\ncan happen in DAG combining, function visitSINT_TO_FP() replaces SINT_TO_FP\nnode with UINT_TO_FP node and function combineUIntToFP() replace vice versa in cycle.\nThe fix prevents it.\n\nPatch by vrybalov\n\nDifferential Revision: https://reviews.llvm.org/D45572\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330711 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/ad168c349451f03369bdfc7959ee5fbc90c9ba3a"},{"sha":"a9a87be18b9c5aad2003e14ea028e400e2f2f21f","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[MC] Remove orphan MCSchedModel::computeReciprocalThroughput declaration. NFCI.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330713 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/a9a87be18b9c5aad2003e14ea028e400e2f2f21f"},{"sha":"2574f6647ee315b354c78e5245577be13a8ef08d","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86] Add vector element insertion/extraction scheduler classes\n\nSplit off pinsr/pextr and extractps instructions.\n\n(Mostly) fixes PR36887.\n\nNote: It might be worth adding a WriteFInsertLd class as well in the future.\n\nDifferential Revision: https://reviews.llvm.org/D45929\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330714 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/2574f6647ee315b354c78e5245577be13a8ef08d"},{"sha":"18d09b9a77f7aa70a9cc7a4a3b511becda5b2e89","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86] Fix missing cfi from sitofp checks\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330715 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/18d09b9a77f7aa70a9cc7a4a3b511becda5b2e89"},{"sha":"d0c01140be8d3f918b6ff4f5a4d5dbd0fb51c5b2","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"Fix Wdocumentation warnings. NFCI.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330716 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/d0c01140be8d3f918b6ff4f5a4d5dbd0fb51c5b2"},{"sha":"a6bf70d02a341791719b6dbc81c3a654db107c52","author":{"name":"Ulrich Weigand","email":"dfbb67861321c3a0b65599ad75850a0b877f5c0d@de.ibm.com"},"message":"[SystemZ] Use preferred 16-byte function alignment\n\nWhile not necessary for correctness, it is preferable for\nperformance reasons on all architectures we currently support\nto align functions to 16-byte boundaries by default.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330718 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/a6bf70d02a341791719b6dbc81c3a654db107c52"},{"sha":"6d80e6324bbd53093c15949dd7495105decde33c","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330720 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/6d80e6324bbd53093c15949dd7495105decde33c"},{"sha":"0f80c5447f7095e2a904a7339844a9b854e6cd5c","author":{"name":"Andrea Di Biagio","email":"477cf5b24d5c0cb561469a6faea86f0cd78ed1ab@sn.scee.net"},"message":"[llvm-mca] Refactor the Scheduler interface in preparation for PR36663.\n\nZero latency instructions are now scheduled the same way as other instructions.\nBefore this patch, there was a specialzed code path for those instructions.\n\nAll scheduler events are now generated from method `scheduleInstruction()` and\nfrom method `cycleEvent()`. This will make easier to implement a \"execution\nstage\", and let that stage publish all the scheduler events.\n\nNo functional change intended.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330723 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/0f80c5447f7095e2a904a7339844a9b854e6cd5c"},{"sha":"5b7ab74398ae82859d837f991346ea16ba1c7f53","author":{"name":"Benjamin Kramer","email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com"},"message":"[LoadStoreVectorize] Ignore interleaved invariant loads.\n\nThe memory location an invariant load is using can never be clobbered by\nany store, so it's safe to move the load ahead of the store.\n\nDifferential Revision: https://reviews.llvm.org/D46011\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330725 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/5b7ab74398ae82859d837f991346ea16ba1c7f53"},{"sha":"b99e72106adb7d34ae49ff65443b2dae339c1939","author":{"name":"David Blaikie","email":"05f726f834638679f776bde9b9fcd7e9d7242de5@gmail.com"},"message":"Fix some layering in AggressiveInstCombine (avoiding inclusion of Scalar.h)\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330726 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/b99e72106adb7d34ae49ff65443b2dae339c1939"},{"sha":"70f3bbf514c1231db76ba5c24739c96c6ef9a03a","author":{"name":"Nico Weber","email":"0d2d6fe0cb2e9ade0d2bf90d72a72b8ac034ef0e@gmx.de"},"message":"Remove LLVM_INSTALL_CCTOOLS_SYMLINKS\n\nIt used to symlink dsymutil to llvm-dsymutil, but after r327790 llvm's dsymutil\nbinary is now called dsymutil without prefix.\n\nr327792 then reversed the direction of the symlink if\nLLVM_INSTALL_CCTOOLS_SYMLINKS was set, but that looks like a buildfix and not\nlike something anyone should need.\n\nhttps://reviews.llvm.org/D45966\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330727 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/70f3bbf514c1231db76ba5c24739c96c6ef9a03a"},{"sha":"7537653e9a6677149bef4f48d6019fd915958366","author":{"name":"Dan Liew","email":"2591e5f46f28d303f9dc027d475a5c60d8dea17a@su-root.co.uk"},"message":"[lit] Remove spurious `-` in invocation of lit in\n`shtest-xunit-output.py` test.\n\nAlthough there is no `-` file Jeremy Morse has reported to me that it\ncauses problems in their setup because lit tries to find it and ends up\nloading an out of tree lit configuration file.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330728 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/7537653e9a6677149bef4f48d6019fd915958366"},{"sha":"e5ad7684b57bee04d0a625609bc6cc90bb7dfed2","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[InstCombine] regenerate checks; NFC\n\nThe current version of the script uses regex for params.\nThis could mask a bug (param values got wrongly swapped),\nbut it seems unlikely in practice, so let's just update\nthe whole file to reduce diffs when there is a meaningful\nchange here.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330729 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/e5ad7684b57bee04d0a625609bc6cc90bb7dfed2"},{"sha":"fc4e13c88fc3ea2ad6b5cc21fd466f4c2d97444f","author":{"name":"Mark Searles","email":"691d79a4bd45e50bb2acba1a9a032290c1069f4b@gmail.com"},"message":"[AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency:\n- s/SWaitcnt/Waitcnt s/WaitCnt/Waitcnt\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330730 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/fc4e13c88fc3ea2ad6b5cc21fd466f4c2d97444f"},{"sha":"6ddbc3eac4ab29ca35a77f2b07a29068f07d8d64","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[InstCombine] regenerate checks; NFC\n\nThe first step in fixing problems raised in D45862\nis to make the problems visible. Now we can more easily\nsee/update cases where selects have been turned into \nmultiple instructions with no apparent improvement in \nanalysis or benefits for other passes (vectorization).\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330731 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/6ddbc3eac4ab29ca35a77f2b07a29068f07d8d64"},{"sha":"6f8184d949f0793d04b132890fbf7f91ade34b06","author":{"name":"Simon Atanasyan","email":"088e16a1019277b15d58faf0541e11910eb756f6@atanasyan.com"},"message":"[mips] Show an error if register number is out of range\n\nCurrent code does not check that a register number is in the 0-31 range.\nSometimes the parser checks that later for some kinds of instructions,\nbut that leads to unclear / incorrect error messages like that:\n\n  % cat test.s\n  .text\n  lb $4, 8($32)\n\n  % llvm-mc test.s -triple=mips64-unknown-linux\n  test.s:2:10: error: expected memory with 16-bit signed offset\n    lb $4, 8($32)\n           ^\n\nSometimes the parser just crashes:\n\n  % cat test.s\n  .text\n  lw  $4, 8($32)\n\n  % llvm-mc test.s -triple=mips64-unknown-linux\n\nThis patch resolves the problem by checking that register number after\n'$' sign is in the 0-31 range. If the number is out of the range the\nparser shows the `invalid register number` error, but treats invalid\nregister number as a normal one to continue parsing and catch other\npossible errors.\n\nDifferential Revision: https://reviews.llvm.org/D45919\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330732 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/6f8184d949f0793d04b132890fbf7f91ade34b06"},{"sha":"9830843b265c0b9cde94e1b01a26224331287992","author":{"name":"Andrea Di Biagio","email":"477cf5b24d5c0cb561469a6faea86f0cd78ed1ab@sn.scee.net"},"message":"[llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.\n\nThe instruction printer used by llvm-mca to generate the performance report now\ndefaults the output assembly format to the format used for the input assembly\nfile.\n\nOn x86, the asm format can be either AT&T or Intel, depending on the\npresence/absence of directive `.intel_syntax`.\n\nUsers can still specify a different assembly dialect with the command line flag\n-output-asm-variant=<uint>.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330733 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/9830843b265c0b9cde94e1b01a26224331287992"},{"sha":"7d78f54577d6913c92ec342cc526ba61dad99e68","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86][IVB] Add F16C resource tests.\n\nNote this is IvyBridge (which shares the model) NOT SandyBridge.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330734 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/7d78f54577d6913c92ec342cc526ba61dad99e68"},{"sha":"f862b68e42ad70d0c8524d7ef3d8f295d480349d","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies\n\nThese are stores, not loads, so don't need to account for load latency.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330735 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/cdl-saarland/vplan-rv/commits/f862b68e42ad70d0c8524d7ef3d8f295d480349d"}]}
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