{"action":"created","issue":{"url":"https://api.github.com/repos/steveicarus/iverilog/issues/199","repository_url":"https://api.github.com/repos/steveicarus/iverilog","labels_url":"https://api.github.com/repos/steveicarus/iverilog/issues/199/labels{/name}","comments_url":"https://api.github.com/repos/steveicarus/iverilog/issues/199/comments","events_url":"https://api.github.com/repos/steveicarus/iverilog/issues/199/events","html_url":"https://github.com/steveicarus/iverilog/issues/199","id":331361139,"node_id":"MDU6SXNzdWUzMzEzNjExMzk=","number":199,"title":"divide overflow is not detected for verilog 32-bit integers.","user":{"login":"oskarguan","id":23741503,"node_id":"MDQ6VXNlcjIzNzQxNTAz","avatar_url":"https://avatars2.githubusercontent.com/u/23741503?v=4","gravatar_id":"","url":"https://api.github.com/users/oskarguan","html_url":"https://github.com/oskarguan","followers_url":"https://api.github.com/users/oskarguan/followers","following_url":"https://api.github.com/users/oskarguan/following{/other_user}","gists_url":"https://api.github.com/users/oskarguan/gists{/gist_id}","starred_url":"https://api.github.com/users/oskarguan/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/oskarguan/subscriptions","organizations_url":"https://api.github.com/users/oskarguan/orgs","repos_url":"https://api.github.com/users/oskarguan/repos","events_url":"https://api.github.com/users/oskarguan/events{/privacy}","received_events_url":"https://api.github.com/users/oskarguan/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2018-06-11T21:43:40Z","updated_at":"2018-06-14T21:13:13Z","closed_at":"2018-06-14T21:13:13Z","author_association":"NONE","body":"I'm using iverilog 10.1 on x64 win7 system with \"iverlog -v\" outputs:\r\n\r\n$ iverilog -v\r\nIcarus Verilog version 10.1 (stable) (v10_1_1)\r\n\r\nCopyright 1998-2015 Stephen Williams\r\n\r\nWhen I simulating my serial divider, I found that divide overflow of 32-bit integers:\r\n$signed(32'h8000_0000) / $signed(32'hFFFF_FFFF) \r\nis not detected by vvp and will stall the program when evaluating the expression.\r\n\r\nMy test program is:\r\n\r\nmodule divov1;\r\n  reg [31:0] q1;\r\n  reg [31:0] q2;\r\n  reg [31:0] quotient;\r\n  initial begin\r\n    q1 = 32'h8000_0000;\r\n    q2 = 32'hFFFF_FFFF;\r\n    quotient = $signed(q1) / $signed(q2);\r\n    $display(\"quotient = 0x%08h;\", quotient);\r\n    $finish;\r\n  end\r\nendmodule // divov1\r\n\r\nExecuting the test program never returns to the shell (cygwin) or cmd.exe.\r\n\r\n$vvp divov.vvp\r\n\r\n\r\nI also tested wider (64-bit) and narrower (16-bit) integers. Both of them didn't stall the program.\r\n\r\nThe 64-bit test program is:\r\n\r\nmodule divov2;\r\n  reg [63:0] q1;\r\n  reg [63:0] q2;\r\n  reg [63:0] quotient;\r\n  initial begin\r\n    q1 = 64'h8000_0000_0000_0000;\r\n    q2 = 64'hFFFF_FFFF_FFFF_FFFF;\r\n    quotient = $signed(q1) / $signed(q2);\r\n    $display(\"quotient = 0x%016h;\", quotient);\r\n    $finish;\r\n  end\r\nendmodule // divov2\r\n\r\nThe output of 64-bit test program is:\r\n\r\n$ vvp divov2.vvp\r\nquotient = 0x8000000000000000;\r\n\r\nThe 16-bit test program is\r\n\r\nmodule divov3;\r\n  reg [15:0] q1;\r\n  reg [15:0] q2;\r\n  reg [15:0] quotient;\r\n  initial begin\r\n    q1 = 16'h8000;\r\n    q2 = 16'hFFFF;\r\n    quotient = $signed(q1) / $signed(q2);\r\n    $display(\"quotient = 0x%04h;\", quotient);\r\n    $finish;\r\n  end\r\nendmodule // divov3\r\n\r\nThe output of 16-bit test program is:\r\n\r\n$ vvp divov3.vvp\r\nquotient = 0x8000;\r\n"},"comment":{"url":"https://api.github.com/repos/steveicarus/iverilog/issues/comments/397440143","html_url":"https://github.com/steveicarus/iverilog/issues/199#issuecomment-397440143","issue_url":"https://api.github.com/repos/steveicarus/iverilog/issues/199","id":397440143,"node_id":"MDEyOklzc3VlQ29tbWVudDM5NzQ0MDE0Mw==","user":{"login":"oskarguan","id":23741503,"node_id":"MDQ6VXNlcjIzNzQxNTAz","avatar_url":"https://avatars2.githubusercontent.com/u/23741503?v=4","gravatar_id":"","url":"https://api.github.com/users/oskarguan","html_url":"https://github.com/oskarguan","followers_url":"https://api.github.com/users/oskarguan/followers","following_url":"https://api.github.com/users/oskarguan/following{/other_user}","gists_url":"https://api.github.com/users/oskarguan/gists{/gist_id}","starred_url":"https://api.github.com/users/oskarguan/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/oskarguan/subscriptions","organizations_url":"https://api.github.com/users/oskarguan/orgs","repos_url":"https://api.github.com/users/oskarguan/repos","events_url":"https://api.github.com/users/oskarguan/events{/privacy}","received_events_url":"https://api.github.com/users/oskarguan/received_events","type":"User","site_admin":false},"created_at":"2018-06-14T21:13:13Z","updated_at":"2018-06-14T21:13:13Z","author_association":"NONE","body":"I built the master branch on MINGW64 and MSYS2 with uname -a output:\r\n\r\n$ uname -a\r\nMINGW64_NT-6.1 oskarguan-win7 2.10.0(0.325/5/3) 2018-02-09 15:25 x86_64 Msys\r\n\r\nGCC and all dependent packages were installed with MSYS2's pacman. \r\n\r\nThe upper 3 testcases terminated normally.\r\n\r\n$ vvp divop1.vvp\r\nquotient = 0x80000000;\r\n\r\n$ vvp divop2.vvp\r\nquotient = 0x8000000000000000;\r\n\r\n$ vvp divop3.vvp\r\nquotient = 0x8000;\r\n\r\nThis issue seems solved."}}
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