{"push_id":2687885278,"size":25,"distinct_size":1,"ref":"refs/heads/amd-hcc","head":"a00b0199968405f679a13ceb10efb065316e18ab","before":"ea115504c3f9f2a4bc173083e90c4856fc2596a1","commits":[{"sha":"8dc6c5c5dae53e8e6155577670721ed796ab94ee","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Remove the AsmName from the HAX,HDX,HCX,HBX,HSI,HDI,HBP,HSP,HIP artificial registers so they can't be parsed by the assembly parser.\n\nThere are no instructions that use them so they weren't causing any bad matches. But they weren't being diagnosed as \"invalid register name\" if they were used and would instead trigger some form of invalid operand.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336054 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/8dc6c5c5dae53e8e6155577670721ed796ab94ee"},{"sha":"16815e99bbac1ba34e041ab1cb137db9aca89c78","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Move the X86InstrFMA3Info class into the cpp file. Expose only a getFMA3Group free function. NFCI\n\nThe class only exists to hold a DenseMap and is only created as a ManagedStatic. It used to expose a single static method that outside code was expected to use.\n\nThis patch moves that static function out of the class and moves it implementation into the cpp file. It can now access the ManagedStatic directly by name without the need for the other static method that accessed the ManagedStatic.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336055 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/16815e99bbac1ba34e041ab1cb137db9aca89c78"},{"sha":"c9cdb1550831cffeb2cce550f01022b9ca8fb318","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch master into amd-master","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/c9cdb1550831cffeb2cce550f01022b9ca8fb318"},{"sha":"ed5068fcf14edc70bb5cefccf276c0240621697c","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Move the memory unfolding table creation into its own class and make it a ManagedStatic.\n\nAlso move the static folding tables, their search functions and the new class into new cpp/h files.\n\nThe unfolding table is effectively static data. It's just a different ordering and a subset of the static folding tables.\n\nBy putting it in a separate ManagedStatic we ensure we only have one copy instead of one per X86InstrInfo object. This way also makes it only get initialized when really needed.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336056 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/ed5068fcf14edc70bb5cefccf276c0240621697c"},{"sha":"bae318922746f3ad60d2659e6d7b65c61a8aca6a","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Remove unnecessary include. NFC\n\nLeftover from when the pass contained a DenseMap before it switched to binary search.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336057 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/bae318922746f3ad60d2659e6d7b65c61a8aca6a"},{"sha":"bc0e3d8f8978319d5e5dea2addf7c250bafdd07b","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-master into amd-common","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/bc0e3d8f8978319d5e5dea2addf7c250bafdd07b"},{"sha":"76adafa48adae44f7de033a096431fd8ef6a9e02","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-common into amd-common","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/76adafa48adae44f7de033a096431fd8ef6a9e02"},{"sha":"0de2000b2d0b29423c891a9551310a638b2b5959","author":{"name":"Paul Semel","email":"e3e0e96728d8016e88bce48ed9ec9751ba671429@gmail.com"},"message":"[llvm-readobj] Fix printing format\n\nWe were printing every character, even those that weren't printable. It\ndoesn't really make sense for this option.\n\nThe string content was sticked to its address, added two spaces in\nbetween.\n\nDifferential Revision: https://reviews.llvm.org/D48271\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336058 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/0de2000b2d0b29423c891a9551310a638b2b5959"},{"sha":"eaabebdbe0095cd5a648d2762e5d199e047080b2","author":{"name":"Eugene Leviant","email":"89f63051247d9692bf8ba81e334b646bb12d0f6b@accesssoftek.com"},"message":"[Evaluator] Improve evaluation of call instruction\n\nRecommit of r335324 after buildbot failure fix\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336059 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/eaabebdbe0095cd5a648d2762e5d199e047080b2"},{"sha":"243c2fa15c2407d2f94c68e85fc3201e27a4746d","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[SLPVectorizer][X86] Add some alternate tests for cast operators\n\nAlternate opcode handling only supports binary operators, these tests demonstrate missed opportunities to vectorize some sitofp/uitofp and fptosi/fptoui style casts as well as some (successful) float bits manipulations\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336060 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/243c2fa15c2407d2f94c68e85fc3201e27a4746d"},{"sha":"2d07720488be48890c5700b118e58eed90d11388","author":{"name":"Paul Semel","email":"e3e0e96728d8016e88bce48ed9ec9751ba671429@gmail.com"},"message":"Revert \"[llvm-readobj] Fix printing format\"\n\nThere is a problem with the formatting on windows build.\nI need to investigate on this.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336061 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/2d07720488be48890c5700b118e58eed90d11388"},{"sha":"e101271f2136e646748d81e35859556c8aba71f7","author":{"name":"David Green","email":"4503caa52df5afa1c818a4a776e14b0cb7e5dc0c@arm.com"},"message":"[UnrollAndJam] New Unroll and Jam pass\n\nThis is a simple implementation of the unroll-and-jam classical loop\noptimisation.\n\nThe basic idea is that we take an outer loop of the form:\n\n  for i..\n    ForeBlocks(i)\n    for j..\n      SubLoopBlocks(i, j)\n    AftBlocks(i)\n\nInstead of doing normal inner or outer unrolling, we unroll as follows:\n\n  for i... i+=2\n    ForeBlocks(i)\n    ForeBlocks(i+1)\n    for j..\n      SubLoopBlocks(i, j)\n      SubLoopBlocks(i+1, j)\n    AftBlocks(i)\n    AftBlocks(i+1)\n  Remainder Loop\n\nSo we have unrolled the outer loop, then jammed the two inner loops into\none. This can lead to a simpler inner loop if memory accesses can be shared\nbetween the now jammed loops.\n\nTo do this we have to prove that this is all safe, both for the memory\naccesses (using dependence analysis) and that ForeBlocks(i+1) can move before\nAftBlocks(i) and SubLoopBlocks(i, j).\n\nDifferential Revision: https://reviews.llvm.org/D41953\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336062 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/e101271f2136e646748d81e35859556c8aba71f7"},{"sha":"5252d29bf8798efb21cb5bdb56ac55f201787c67","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch master into amd-master","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/5252d29bf8798efb21cb5bdb56ac55f201787c67"},{"sha":"4c7a6ba2a437adc7443b458b32b9ca74adbe59df","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[SLPVectorizer] Use InstructionsState Op/Alt opcodes directly. NFCI.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336063 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/4c7a6ba2a437adc7443b458b32b9ca74adbe59df"},{"sha":"6fed3d8070003bd65e0af3b70aaa04f7ca12260e","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[PatternMatch] allow undef elements in vectors with m_Neg\n\nThis is similar to the m_Not change from D44076.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336064 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/6fed3d8070003bd65e0af3b70aaa04f7ca12260e"},{"sha":"cdf029155af09297fe9f54140e0512f05cf663e4","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-master into amd-common","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/cdf029155af09297fe9f54140e0512f05cf663e4"},{"sha":"77442a72e04998d9319a3172ff2d0a814526d719","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[InstCombine] add abs tests with undef elts; NFC\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336065 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/77442a72e04998d9319a3172ff2d0a814526d719"},{"sha":"23d1e8ab6005d6ce1ef805ca9d7e36013f065bec","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86][Disassembler] Remove TYPE_BNDR from translateImmediate.\n\nI've check the disassembler tables and this shouldn't be reachable. Which is good since if it was reachable there should have been a 'return' after the addOperand line.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336066 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/23d1e8ab6005d6ce1ef805ca9d7e36013f065bec"},{"sha":"967d11bf6fee34fb41d003fa3d27f7d4f15e49aa","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-common into amd-common","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/967d11bf6fee34fb41d003fa3d27f7d4f15e49aa"},{"sha":"b1dbeaa9ce7550794a23782506599b9160bf7bdb","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsState.isOpcodeOrAlt helper. NFCI.\n\nThis is a basic step towards matching more general instructions types than just opcodes.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336068 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/b1dbeaa9ce7550794a23782506599b9160bf7bdb"}]}
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