{"push_id":2933315727,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"d185c9493b86178cd943a50af121bab15a70371c","before":"07da021fe45154f8cdcfb45f0a7a0c9fee21133e","commits":[{"sha":"d185c9493b86178cd943a50af121bab15a70371c","author":{"name":"Victor Espinoza","email":"63740743e86c4f0dccc1c20d431ac5b9ff8c8653@gmail.com"},"message":"Update .gitignore","distinct":true,"url":"https://api.github.com/repos/Victor-Espinoza-Verilog-RISC-Processor/Lab_5_Memory_and_Display_Controllers/commits/d185c9493b86178cd943a50af121bab15a70371c"}]}
{"actor":{"display_login":"victor-espinoza"}}