{"push_id":2604368732,"size":49,"distinct_size":0,"ref":"refs/heads/HEAD","head":"e609fa71e89c81fbe2670411be62da95dfb093e0","before":"98c0a88ea31140d2fdb0eac9c153212d036f6d0d","commits":[{"sha":"38ab74e7ca6961f019d771c9500df2ab340693fa","author":{"name":"Stefan Berger","email":"5c96973112e540fb909b13997fcd087e5bfbee96@linux.vnet.ibm.com"},"message":"tpm: extend TPM emulator with state migration support\n\nExtend the TPM emulator backend device with state migration support.\n\nThe external TPM emulator 'swtpm' provides a protocol over\nits control channel to retrieve its state blobs. We implement\nfunctions for getting and setting the different state blobs.\nIn case the setting of the state blobs fails, we return a\nnegative errno code to fail the start of the VM.\n\nSince we have an external TPM emulator, we need to make sure\nthat we do not migrate the state for as long as it is busy\nprocessing a request. We need to wait for notification that\nthe request has completed processing.\n\nSigned-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>\nReviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/38ab74e7ca6961f019d771c9500df2ab340693fa"},{"sha":"9ec08c485e3f97d26dd47868582c1ae1b959c182","author":{"name":"Stefan Berger","email":"5c96973112e540fb909b13997fcd087e5bfbee96@linux.vnet.ibm.com"},"message":"tpm: extend TPM TIS with state migration support\n\nExtend the TPM TIS interface with state migration support.\n\nWe need to synchronize with the backend thread to make sure that a command\nbeing processed by the external TPM emulator has completed and its\nresponse been received.\n\nSigned-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>\nReviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/9ec08c485e3f97d26dd47868582c1ae1b959c182"},{"sha":"9d1f0985a77429c6d527077a44b28d43f5906112","author":{"name":"Stefan Berger","email":"5c96973112e540fb909b13997fcd087e5bfbee96@linux.vnet.ibm.com"},"message":"docs: tpm: add VM save/restore example and troubleshooting guide\n\nExtend the docs related to TPM with specs related to VM save and\nrestore and a troubleshooting guide for TPM migration.\n\nSigned-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>\nReviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/9d1f0985a77429c6d527077a44b28d43f5906112"},{"sha":"b21373d0713d060e42dcec8262197a91b71dfd4b","author":{"name":"Stefan Berger","email":"5c96973112e540fb909b13997fcd087e5bfbee96@linux.vnet.ibm.com"},"message":"test: Add test cases that use the external swtpm with CRB interface\n\nAdd a test program for testing the CRB with the external swtpm.\n\nThe 1st test case extends a PCR and reads back the value and compares\nit against an expected return packet.\n\nThe 2nd test case repeats the 1st test case and then migrates the\nexternal swtpm's state along with the VM state to a destination\nQEMU and swtpm and checks that the PCR has the expected value now.\n\nThe test cases require 'swtpm' to be installed on the system and\nin the PATH and 'swtpm' must support the --tpm2 option. If this is\nnot the case, the test will be skipped.\n\nSigned-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/b21373d0713d060e42dcec8262197a91b71dfd4b"},{"sha":"8534063a38583f1e0458daf076154131a83fa0e0","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: dec_load: Use bool instead of unsigned int\n\nUse bool instead of unsigned int to represent flags.\nNo functional change.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/8534063a38583f1e0458daf076154131a83fa0e0"},{"sha":"b51b3d43deeb9880b383603806daedf125ae9cce","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: dec_store: Use bool instead of unsigned int\n\nUse bool instead of unsigned int to represent flags.\nAlso, use extract32 instead of open coding the bit extract.\n\nNo functional change.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/b51b3d43deeb9880b383603806daedf125ae9cce"},{"sha":"0e9033c8c53c3839871c59ef431bcfdc9359d0c1","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: compute_ldst_addr: Use bool instead of int\n\nUse bool instead of int to represent flags.\nNo functional change.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0e9033c8c53c3839871c59ef431bcfdc9359d0c1"},{"sha":"4c8ac10737ae38256d59406801591d9dca2bd69b","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Fallback to our latest CPU version\n\nToday, when running QEMU in linux-user or with boards that don't\nselect a specific CPU version, we treat it as an invalid version\nand log a message.\n\nInstead, if no specific version was selected, fallback to our\nlatest CPU version.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/4c8ac10737ae38256d59406801591d9dca2bd69b"},{"sha":"5c594ef3c77c7226e7b2080430b9b74d26d5bd7e","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Correct special register array sizes\n\nCorrect special register array sizes.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/5c594ef3c77c7226e7b2080430b9b74d26d5bd7e"},{"sha":"c56911a424c5279a5113c4e1d508733a60c12dbc","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Correct the PVR array size\n\nCorrect the PVR array size, there are 13 PVR registers.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/c56911a424c5279a5113c4e1d508733a60c12dbc"},{"sha":"cfeea807e5af996979b2c13ab3b6eb447e1796bb","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Tighten up TCGv_i32 vs TCGv type usage\n\nTighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when\nTCGv_i32 should be used.\n\nThis is in preparation for adding 64bit addressing support.\nNo functional change.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/cfeea807e5af996979b2c13ab3b6eb447e1796bb"},{"sha":"a17f7c05f07aa3a825f7dc1ba22d70df16098d3c","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Remove USE_MMU PVR checks\n\nWe already have a CPU property to control if a core has\nan MMU or not. Remove USE_MMU PVR checks in favor of\nlooking at the property.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/a17f7c05f07aa3a825f7dc1ba22d70df16098d3c"},{"sha":"9e50a927b4e2e724849f6ec19fa55fe40e13d174","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Conditionalize setting of PVR11_USE_MMU\n\nConditionalize setting of PVR11_USE_MMU on the use_mmu\nCPU property, otherwise we may incorrectly advertise an\nMMU via PVR when the core in fact has none.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/9e50a927b4e2e724849f6ec19fa55fe40e13d174"},{"sha":"a2de5ca451354155a0d6a9b098cbdd44eabb2da5","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Bypass MMU with MMU_NOMMU_IDX\n\nBypass MMU translation when mmu-index MMU_NOMMU_IDX is used.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/a2de5ca451354155a0d6a9b098cbdd44eabb2da5"},{"sha":"0dc4af5c1a0e8d3f73b176f8fd3159e77a4c2492","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Make compute_ldst_addr always use a temp\n\nMake compute_ldst_addr always use a temp. This simplifies\nthe code a bit in preparation for adding support for\n64bit addresses.\n\nNo functional change.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0dc4af5c1a0e8d3f73b176f8fd3159e77a4c2492"},{"sha":"0a87e691b3924d5e3964dd1b77eb88b000dd4126","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Remove pointer indirection for ld/st addresses\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0a87e691b3924d5e3964dd1b77eb88b000dd4126"},{"sha":"403322ea6c383b3337fe3c52d9ed84958f94bcd1","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Use TCGv for load/store addresses\n\nUse TCGv for load/store addresses, allowing for future\ncomputation of 64-bit load/store address.\n\nNo functional change.\n\nAcked-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/403322ea6c383b3337fe3c52d9ed84958f94bcd1"},{"sha":"0031eef23ac0850cb04f6932ba8c42d2d6e712f2","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Name special registers we support\n\nName special registers we support.\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0031eef23ac0850cb04f6932ba8c42d2d6e712f2"},{"sha":"bdfc1e886939f06b94f4fee3105a41dbd20a97db","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Break out trap_userspace()\n\nBreak out trap_userspace() to avoid open coding it everywhere.\nFor privileged insns, we now always stop translation of the\ncurrent insn for cores without exceptions.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/bdfc1e886939f06b94f4fee3105a41dbd20a97db"},{"sha":"9ba8cd452bb48ad63e2878f8ebef4cfb18f46812","author":{"name":"Edgar E. Iglesias","email":"3c2cc96b84b05462a9c234ea604e7fc218094334@xilinx.com"},"message":"target-microblaze: Break out trap_illegal()\n\nBreak out trap_illegal() to handle illegal operation traps.\nWe now generally stop translation of the current insn if\nit's not valid.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/9ba8cd452bb48ad63e2878f8ebef4cfb18f46812"}]}
{"actor":{"display_login":"joyxu"}}