{"push_id":2802832439,"size":5,"distinct_size":5,"ref":"refs/heads/for-upstream-clk","head":"eb16425a1c6dffcc3c78e8adfc1c0654a12af1f8","before":"3303c650971bc244574a6a3631e42eed781dcb96","commits":[{"sha":"a37ce8a966c87eead9dd9efbf42a5cab8b73eee8","author":{"name":"Paul Cercueil","email":"a027184a55211cd23e3f3094f1fdc728df5e0500@crapouillou.net"},"message":"clk: ingenic: Add proper Kconfig entries\n\nPreviously, the CGU code corresponding to the SoC for which we're\ncompiling the kernel was the only one enabled, which made it impossible\nto build one kernel that supports them all.\n\nNow, it is possible to select more than one SoC to support.\n\nSigned-off-by: Paul Cercueil <paul@crapouillou.net>","distinct":true,"url":"https://api.github.com/repos/OpenDingux/linux/commits/a37ce8a966c87eead9dd9efbf42a5cab8b73eee8"},{"sha":"739139608861fefa51ffc1c9989c75e713a9ea98","author":{"name":"Paul Cercueil","email":"a027184a55211cd23e3f3094f1fdc728df5e0500@crapouillou.net"},"message":"dt-bindings: clock: Add jz4725b-cgu.h header\n\nThis will be used from the devicetree bindings to specify the clocks\nthat should be obtained from the jz4725b-cgu driver.\n\nSigned-off-by: Paul Cercueil <paul@crapouillou.net>","distinct":true,"url":"https://api.github.com/repos/OpenDingux/linux/commits/739139608861fefa51ffc1c9989c75e713a9ea98"},{"sha":"e12dc768bc42586b26b514bb5b2c188f9bdb20f5","author":{"name":"Paul Cercueil","email":"a027184a55211cd23e3f3094f1fdc728df5e0500@crapouillou.net"},"message":"clk: Add Ingenic jz4725b CGU driver\n\nAdd support for the clocks provided by the CGU in the Ingenic JZ4725B\nSoC.\n\nSigned-off-by: Paul Cercueil <paul@crapouillou.net>","distinct":true,"url":"https://api.github.com/repos/OpenDingux/linux/commits/e12dc768bc42586b26b514bb5b2c188f9bdb20f5"},{"sha":"c56d8574a3ae28b135a20e2a59378bd67d2a312c","author":{"name":"Paul Cercueil","email":"a027184a55211cd23e3f3094f1fdc728df5e0500@crapouillou.net"},"message":"clk: ingenic: Add support for divider tables\n\nSome clocks provided on the jz4770 have dividers, whose hardware value\n(as written in the register) cannot be expressed as an affine function\nto the actual divider value.\n\nFor instance, for the CPU clock, the dividers are coded as follows:\n\n    ------------------\n    | Bits     | Div |\n    ------------------\n    | 0  0  0  |  1  |\n    | 0  0  1  |  2  |\n    | 0  1  0  |  3  |\n    | 0  1  1  |  4  |\n    | 1  0  0  |  6  |\n    | 1  0  1  |  8  |\n    | 1  1  0  | 12  |\n    ------------------\n\nTo support this setup, we introduce a new field in the\ningenic_cgu_div_info structure that allows to specify the divider table.\n\nSigned-off-by: Paul Cercueil <paul@crapouillou.net>","distinct":true,"url":"https://api.github.com/repos/OpenDingux/linux/commits/c56d8574a3ae28b135a20e2a59378bd67d2a312c"},{"sha":"eb16425a1c6dffcc3c78e8adfc1c0654a12af1f8","author":{"name":"Paul Cercueil","email":"a027184a55211cd23e3f3094f1fdc728df5e0500@crapouillou.net"},"message":"clk: ingenic: jz4770: Fix incorrect dividers for main clocks\n\nThe main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were reporting\nincorrect dividers, and thus an incorrect rate.\n\nSigned-off-by: Paul Cercueil <paul@crapouillou.net>","distinct":true,"url":"https://api.github.com/repos/OpenDingux/linux/commits/eb16425a1c6dffcc3c78e8adfc1c0654a12af1f8"}]}
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