{"action":"created","comment":{"url":"https://api.github.com/repos/WebAssembly/simd/pulls/comments/230246492","pull_request_review_id":170941493,"id":230246492,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDIzMDI0NjQ5Mg==","diff_hunk":"@@ -27,143 +27,170 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`.\n \n | Instruction               | `simdop` | Immediate operands |\n | --------------------------|---------:|--------------------|\n-| `v128.const`              |        0 | i:ImmByte[16]      |\n-| `v128.load`               |        1 | m:memarg           |\n-| `v128.store`              |        2 | m:memarg           |\n-| `i8x16.splat`             |        3 | -                  |\n-| `i16x8.splat`             |        4 | -                  |\n-| `i32x4.splat`             |        5 | -                  |\n-| `i64x2.splat`             |        6 | -                  |\n-| `f32x4.splat`             |        7 | -                  |\n-| `f64x2.splat`             |        8 | -                  |\n-| `i8x16.extract_lane_s`    |        9 | i:LaneIdx16        |\n-| `i8x16.extract_lane_u`    |       10 | i:LaneIdx16        |\n-| `i16x8.extract_lane_s`    |       11 | i:LaneIdx8         |\n-| `i16x8.extract_lane_u`    |       12 | i:LaneIdx8         |\n-| `i32x4.extract_lane`      |       13 | i:LaneIdx4         |\n-| `i64x2.extract_lane`      |       14 | i:LaneIdx2         |\n-| `f32x4.extract_lane`      |       15 | i:LaneIdx4         |\n-| `f64x2.extract_lane`      |       16 | i:LaneIdx2         |\n-| `i8x16.replace_lane`      |       17 | i:LaneIdx16        |\n-| `i16x8.replace_lane`      |       18 | i:LaneIdx8         |\n-| `i32x4.replace_lane`      |       19 | i:LaneIdx4         |\n-| `i64x2.replace_lane`      |       20 | i:LaneIdx2         |\n-| `f32x4.replace_lane`      |       21 | i:LaneIdx4         |\n-| `f64x2.replace_lane`      |       22 | i:LaneIdx2         |\n-| `v8x16.shuffle`           |       23 | s:LaneIdx32[16]    |\n-| `i8x16.add`               |       24 | -                  |\n-| `i16x8.add`               |       25 | -                  |\n-| `i32x4.add`               |       26 | -                  |\n-| `i64x2.add`               |       27 | -                  |\n-| `i8x16.sub`               |       28 | -                  |\n-| `i16x8.sub`               |       29 | -                  |\n-| `i32x4.sub`               |       30 | -                  |\n-| `i64x2.sub`               |       31 | -                  |\n-| `i8x16.mul`               |       32 | -                  |\n-| `i16x8.mul`               |       33 | -                  |\n-| `i32x4.mul`               |       34 | -                  |\n-| `i8x16.neg`               |       36 | -                  |\n-| `i16x8.neg`               |       37 | -                  |\n-| `i32x4.neg`               |       38 | -                  |\n-| `i64x2.neg`               |       39 | -                  |\n-| `i8x16.add_saturate_s`    |       40 | -                  |\n-| `i8x16.add_saturate_u`    |       41 | -                  |\n-| `i16x8.add_saturate_s`    |       42 | -                  |\n-| `i16x8.add_saturate_u`    |       43 | -                  |\n-| `i8x16.sub_saturate_s`    |       44 | -                  |\n-| `i8x16.sub_saturate_u`    |       45 | -                  |\n-| `i16x8.sub_saturate_s`    |       46 | -                  |\n-| `i16x8.sub_saturate_u`    |       47 | -                  |\n-| `i8x16.shl`               |       48 | -                  |\n-| `i16x8.shl`               |       49 | -                  |\n-| `i32x4.shl`               |       50 | -                  |\n-| `i64x2.shl`               |       51 | -                  |\n-| `i8x16.shr_s`             |       52 | -                  |\n-| `i8x16.shr_u`             |       53 | -                  |\n-| `i16x8.shr_s`             |       54 | -                  |\n-| `i16x8.shr_u`             |       55 | -                  |\n-| `i32x4.shr_s`             |       56 | -                  |\n-| `i32x4.shr_u`             |       57 | -                  |\n-| `i64x2.shr_s`             |       58 | -                  |\n-| `i64x2.shr_u`             |       59 | -                  |\n-| `v128.and`                |       60 | -                  |\n-| `v128.or`                 |       61 | -                  |\n-| `v128.xor`                |       62 | -                  |\n-| `v128.not`                |       63 | -                  |\n-| `v128.bitselect`          |       64 | -                  |\n-| `i8x16.any_true`          |       65 | -                  |\n-| `i16x8.any_true`          |       66 | -                  |\n-| `i32x4.any_true`          |       67 | -                  |\n-| `i64x2.any_true`          |       68 | -                  |\n-| `i8x16.all_true`          |       69 | -                  |\n-| `i16x8.all_true`          |       70 | -                  |\n-| `i32x4.all_true`          |       71 | -                  |\n-| `i64x2.all_true`          |       72 | -                  |\n-| `i8x16.eq`                |       73 | -                  |\n-| `i16x8.eq`                |       74 | -                  |\n-| `i32x4.eq`                |       75 | -                  |\n-| `f32x4.eq`                |       77 | -                  |\n-| `f64x2.eq`                |       78 | -                  |\n-| `i8x16.ne`                |       79 | -                  |\n-| `i16x8.ne`                |       80 | -                  |\n-| `i32x4.ne`                |       81 | -                  |\n-| `f32x4.ne`                |       83 | -                  |\n-| `f64x2.ne`                |       84 | -                  |\n-| `i8x16.lt_s`              |       85 | -                  |\n-| `i8x16.lt_u`              |       86 | -                  |\n-| `i16x8.lt_s`              |       87 | -                  |\n-| `i16x8.lt_u`              |       88 | -                  |\n-| `i32x4.lt_s`              |       89 | -                  |\n-| `i32x4.lt_u`              |       90 | -                  |\n-| `f32x4.lt`                |       93 | -                  |\n-| `f64x2.lt`                |       94 | -                  |\n-| `i8x16.le_s`              |       95 | -                  |\n-| `i8x16.le_u`              |       96 | -                  |\n-| `i16x8.le_s`              |       97 | -                  |\n-| `i16x8.le_u`              |       98 | -                  |\n-| `i32x4.le_s`              |       99 | -                  |\n-| `i32x4.le_u`              |      100 | -                  |\n-| `f32x4.le`                |      103 | -                  |\n-| `f64x2.le`                |      104 | -                  |\n-| `i8x16.gt_s`              |      105 | -                  |\n-| `i8x16.gt_u`              |      106 | -                  |\n-| `i16x8.gt_s`              |      107 | -                  |\n-| `i16x8.gt_u`              |      108 | -                  |\n-| `i32x4.gt_s`              |      109 | -                  |\n-| `i32x4.gt_u`              |      110 | -                  |\n-| `f32x4.gt`                |      113 | -                  |\n-| `f64x2.gt`                |      114 | -                  |\n-| `i8x16.ge_s`              |      115 | -                  |\n-| `i8x16.ge_u`              |      116 | -                  |\n-| `i16x8.ge_s`              |      117 | -                  |\n-| `i16x8.ge_u`              |      118 | -                  |\n-| `i32x4.ge_s`              |      119 | -                  |\n-| `i32x4.ge_u`              |      120 | -                  |\n-| `f32x4.ge`                |      123 | -                  |\n-| `f64x2.ge`                |      124 | -                  |\n-| `f32x4.neg`               |      125 | -                  |\n-| `f64x2.neg`               |      126 | -                  |\n-| `f32x4.abs`               |      127 | -                  |\n-| `f64x2.abs`               |      128 | -                  |\n-| `f32x4.min`               |      129 | -                  |\n-| `f64x2.min`               |      130 | -                  |\n-| `f32x4.max`               |      131 | -                  |\n-| `f64x2.max`               |      132 | -                  |\n-| `f32x4.add`               |      133 | -                  |\n-| `f64x2.add`               |      134 | -                  |\n-| `f32x4.sub`               |      135 | -                  |\n-| `f64x2.sub`               |      136 | -                  |\n-| `f32x4.div`               |      137 | -                  |\n-| `f64x2.div`               |      138 | -                  |\n-| `f32x4.mul`               |      139 | -                  |\n-| `f64x2.mul`               |      140 | -                  |\n-| `f32x4.sqrt`              |      141 | -                  |\n-| `f64x2.sqrt`              |      142 | -                  |\n-| `f32x4.convert_s/i32x4`   |      143 | -                  |\n-| `f32x4.convert_u/i32x4`   |      144 | -                  |\n-| `f64x2.convert_s/i64x2`   |      145 | -                  |\n-| `f64x2.convert_u/i64x2`   |      146 | -                  |\n-| `i32x4.trunc_s/f32x4:sat` |      147 | -                  |\n-| `i32x4.trunc_u/f32x4:sat` |      148 | -                  |\n-| `i64x2.trunc_s/f64x2:sat` |      149 | -                  |\n-| `i64x2.trunc_u/f64x2:sat` |      150 | -                  |\n+| `v128.load`               |    `0x00`| m:memarg           |\n+| `v128.store`              |    `0x01`| m:memarg           |\n+| `v128.const`              |    `0x02`| i:ImmByte[16]      |\n+| `v8x16.shuffle`           |    `0x03`| s:LaneIdx32[16]    |\n+| `i8x16.splat`             |    `0x04`| -                  |\n+| `i8x16.extract_lane_s`    |    `0x05`| i:LaneIdx16        |\n+| `i8x16.extract_lane_u`    |    `0x06`| i:LaneIdx16        |\n+| `i8x16.replace_lane`      |    `0x07`| i:LaneIdx16        |\n+| `i16x8.splat`             |    `0x08`| -                  |\n+| `i16x8.extract_lane_s`    |    `0x09`| i:LaneIdx8         |\n+| `i16x8.extract_lane_u`    |    `0x0a`| i:LaneIdx8         |\n+| `i16x8.replace_lane`      |    `0x0b`| i:LaneIdx8         |\n+| `i32x4.splat`             |    `0x0c`| -                  |\n+| `i32x4.extract_lane`      |    `0x0d`| i:LaneIdx4         |\n+| `i32x4.replace_lane`      |    `0x0e`| i:LaneIdx4         |\n+| `i64x2.splat`             |    `0x0f`| -                  |\n+| `i64x2.extract_lane`      |    `0x10`| i:LaneIdx2         |\n+| `i64x2.replace_lane`      |    `0x11`| i:LaneIdx2         |\n+| `f32x4.splat`             |    `0x12`| -                  |\n+| `f32x4.extract_lane`      |    `0x13`| i:LaneIdx4         |\n+| `f32x4.replace_lane`      |    `0x14`| i:LaneIdx4         |\n+| `f64x2.splat`             |    `0x15`| -                  |\n+| `f64x2.extract_lane`      |    `0x16`| i:LaneIdx2         |\n+| `f64x2.replace_lane`      |    `0x17`| i:LaneIdx2         |\n+| `v128.and`                |    `0x18`| -                  |\n+| `v128.or`                 |    `0x19`| -                  |\n+| `v128.xor`                |    `0x1a`| -                  |\n+| `v128.not`                |    `0x1b`| -                  |\n+| `v128.bitselect`          |    `0x1c`| -                  |\n+| `i8x16.eq`                |    `0x1d`| -                  |\n+| `i8x16.ne`                |    `0x1e`| -                  |\n+| `i8x16.lt_s`              |    `0x1f`| -                  |\n+| `i8x16.lt_u`              |    `0x20`| -                  |\n+| `i8x16.gt_s`              |    `0x21`| -                  |\n+| `i8x16.gt_u`              |    `0x22`| -                  |\n+| `i8x16.le_s`              |    `0x23`| -                  |\n+| `i8x16.le_u`              |    `0x24`| -                  |\n+| `i8x16.ge_s`              |    `0x25`| -                  |\n+| `i8x16.ge_u`              |    `0x26`| -                  |\n+| `i16x8.eq`                |    `0x27`| -                  |\n+| `i16x8.ne`                |    `0x28`| -                  |\n+| `i16x8.lt_s`              |    `0x29`| -                  |\n+| `i16x8.lt_u`              |    `0x2a`| -                  |\n+| `i16x8.gt_s`              |    `0x2b`| -                  |\n+| `i16x8.gt_u`              |    `0x2c`| -                  |\n+| `i16x8.le_s`              |    `0x2d`| -                  |\n+| `i16x8.le_u`              |    `0x2e`| -                  |\n+| `i16x8.ge_s`              |    `0x2f`| -                  |\n+| `i16x8.ge_u`              |    `0x30`| -                  |\n+| `i32x4.eq`                |    `0x31`| -                  |\n+| `i32x4.ne`                |    `0x32`| -                  |\n+| `i32x4.lt_s`              |    `0x33`| -                  |\n+| `i32x4.lt_u`              |    `0x34`| -                  |\n+| `i32x4.gt_s`              |    `0x35`| -                  |\n+| `i32x4.gt_u`              |    `0x36`| -                  |\n+| `i32x4.le_s`              |    `0x37`| -                  |\n+| `i32x4.le_u`              |    `0x38`| -                  |\n+| `i32x4.ge_s`              |    `0x39`| -                  |\n+| `i32x4.ge_u`              |    `0x3a`| -                  |\n+| -                         |    `0x3b`| -                  |\n+| -                         |    `0x3c`| -                  |\n+| -                         |    `0x3d`| -                  |\n+| -                         |    `0x3e`| -                  |\n+| -                         |    `0x3f`| -                  |\n+| -                         |    `0x40`| -                  |\n+| -                         |    `0x41`| -                  |\n+| -                         |    `0x42`| -                  |\n+| -                         |    `0x43`| -                  |\n+| -                         |    `0x44`| -                  |\n+| `f32x4.eq`                |    `0x45`| -                  |\n+| `f32x4.ne`                |    `0x46`| -                  |\n+| `f32x4.lt`                |    `0x47`| -                  |\n+| `f32x4.gt`                |    `0x48`| -                  |\n+| `f32x4.le`                |    `0x49`| -                  |\n+| `f32x4.ge`                |    `0x4a`| -                  |\n+| `f64x2.eq`                |    `0x4b`| -                  |\n+| `f64x2.ne`                |    `0x4c`| -                  |\n+| `f64x2.lt`                |    `0x4d`| -                  |\n+| `f64x2.gt`                |    `0x4e`| -                  |\n+| `f64x2.le`                |    `0x4f`| -                  |\n+| `f64x2.ge`                |    `0x50`| -                  |\n+| `i8x16.add`               |    `0x51`| -                  |\n+| `i8x16.add_saturate_s`    |    `0x52`| -                  |\n+| `i8x16.add_saturate_u`    |    `0x53`| -                  |\n+| `i8x16.sub`               |    `0x54`| -                  |\n+| `i8x16.sub_saturate_s`    |    `0x55`| -                  |\n+| `i8x16.sub_saturate_u`    |    `0x56`| -                  |\n+| `i8x16.mul`               |    `0x57`| -                  |\n+| -                         |    `0x58`| -                  |\n+| -                         |    `0x59`| -                  |\n+| `i8x16.shl`               |    `0x5a`| -                  |\n+| `i8x16.shr_s`             |    `0x5b`| -                  |\n+| `i8x16.shr_u`             |    `0x5c`| -                  |\n+| `i8x16.neg`               |    `0x5d`| -                  |\n+| `i8x16.any_true`          |    `0x5e`| -                  |","path":"proposals/simd/BinarySIMD.md","position":238,"original_position":238,"commit_id":"6bc61d5c995d753056e6cf7da6ecb8c717275437","original_commit_id":"6bc61d5c995d753056e6cf7da6ecb8c717275437","user":{"login":"tlively","id":7121787,"node_id":"MDQ6VXNlcjcxMjE3ODc=","avatar_url":"https://avatars1.githubusercontent.com/u/7121787?v=4","gravatar_id":"","url":"https://api.github.com/users/tlively","html_url":"https://github.com/tlively","followers_url":"https://api.github.com/users/tlively/followers","following_url":"https://api.github.com/users/tlively/following{/other_user}","gists_url":"https://api.github.com/users/tlively/gists{/gist_id}","starred_url":"https://api.github.com/users/tlively/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tlively/subscriptions","organizations_url":"https://api.github.com/users/tlively/orgs","repos_url":"https://api.github.com/users/tlively/repos","events_url":"https://api.github.com/users/tlively/events{/privacy}","received_events_url":"https://api.github.com/users/tlively/received_events","type":"User","site_admin":false},"body":"Also think that using `v8x16` for only shuffles is weird (see #38), but I think keeping `i8x16` and friends for sign-agnostic operations that still only make sense for integer lanes is reasonable. To counter, what do you think of changing shuffle to be `v128.shuffle`?","created_at":"2018-11-02T01:09:10Z","updated_at":"2018-11-02T01:09:11Z","html_url":"https://github.com/WebAssembly/simd/pull/48#discussion_r230246492","pull_request_url":"https://api.github.com/repos/WebAssembly/simd/pulls/48","author_association":"CONTRIBUTOR","_links":{"self":{"href":"https://api.github.com/repos/WebAssembly/simd/pulls/comments/230246492"},"html":{"href":"https://github.com/WebAssembly/simd/pull/48#discussion_r230246492"},"pull_request":{"href":"https://api.github.com/repos/WebAssembly/simd/pulls/48"}},"in_reply_to_id":230243126},"pull_request":{"url":"https://api.github.com/repos/WebAssembly/simd/pulls/48","id":226198018,"node_id":"MDExOlB1bGxSZXF1ZXN0MjI2MTk4MDE4","html_url":"https://github.com/WebAssembly/simd/pull/48","diff_url":"https://github.com/WebAssembly/simd/pull/48.diff","patch_url":"https://github.com/WebAssembly/simd/pull/48.patch","issue_url":"https://api.github.com/repos/WebAssembly/simd/issues/48","number":48,"state":"open","locked":false,"title":"Reorganize opcodes by kind and type","user":{"login":"tlively","id":7121787,"node_id":"MDQ6VXNlcjcxMjE3ODc=","avatar_url":"https://avatars1.githubusercontent.com/u/7121787?v=4","gravatar_id":"","url":"https://api.github.com/users/tlively","html_url":"https://github.com/tlively","followers_url":"https://api.github.com/users/tlively/followers","following_url":"https://api.github.com/users/tlively/following{/other_user}","gists_url":"https://api.github.com/users/tlively/gists{/gist_id}","starred_url":"https://api.github.com/users/tlively/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tlively/subscriptions","organizations_url":"https://api.github.com/users/tlively/orgs","repos_url":"https://api.github.com/users/tlively/repos","events_url":"https://api.github.com/users/tlively/events{/privacy}","received_events_url":"https://api.github.com/users/tlively/received_events","type":"User","site_admin":false},"body":"This is yet another opcode renumbering.\r\n\r\nI tried to take into account all the comments on #42, particularly @binji's comment about trying to be consistent with the MVP opcode ordering. I also left explicit gaps in the chart for what I think should be reserved opcodes to make the reserved opcodes easier to see and talk about for the time being.\r\n\r\nFeedback welcome!\r\n\r\ncc @dtig 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