{"push_id":2415706935,"size":4,"distinct_size":4,"ref":"refs/heads/qemu-devel","head":"fefb74ccd5e9f3f3b13992c44116736e9943830b","before":"9845a7e3b83a5efe4e552dbb7ad9f8ea642b27bc","commits":[{"sha":"b4ed317d21760eaf9671a2563645c829dfbd496d","author":{"name":"Michael Clark","email":"90d5b738658411aed8489ac35edde876bcc37b1d@sifive.com"},"message":"RISC-V: Convert cpu definition towards future model\n\n- Model borrowed from target/sh4/cpu.c\n- Rewrote riscv_cpu_list to use object_class_get_list\n- Dropped 'struct RISCVCPUInfo' and used TypeInfo array\n- Replaced riscv_cpu_register_types with DEFINE_TYPES\n- Marked base class as abstract\n\nCc: Igor Mammedov <imammedo@redhat.com>\nCc: Sagar Karandikar <sagark@eecs.berkeley.edu>\nCc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Palmer Dabbelt <palmer@sifive.com>\nSigned-off-by: Michael Clark <mjc@sifive.com>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Igor Mammedov <imammedo@redhat.com>","distinct":true,"url":"https://api.github.com/repos/michaeljclark/riscv-qemu/commits/b4ed317d21760eaf9671a2563645c829dfbd496d"},{"sha":"8ad2eba899b3462d074b1965be7a39ca2fda6ff4","author":{"name":"Michael Clark","email":"90d5b738658411aed8489ac35edde876bcc37b1d@sifive.com"},"message":"RISC-V: Clear mtval/stval on exceptions without info\n\nmtval/stval must be set on all exceptions but zero is\na legal value if there is no exception specific info.\nPlacing the instruction bytes for illegal instruction\nexceptions in mtval/stval is an optional feature and\nis currently not supported by QEMU RISC-V.\n\nCc: Sagar Karandikar <sagark@eecs.berkeley.edu>\nCc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Palmer Dabbelt <palmer@sifive.com>\nSigned-off-by: Michael Clark <mjc@sifive.com>","distinct":true,"url":"https://api.github.com/repos/michaeljclark/riscv-qemu/commits/8ad2eba899b3462d074b1965be7a39ca2fda6ff4"},{"sha":"7125e4be0dacb8cfb041ca43666fabecf0b67c9c","author":{"name":"Michael Clark","email":"90d5b738658411aed8489ac35edde876bcc37b1d@sifive.com"},"message":"RISC-V: Remove erroneous comment from translate.c\n\nCc: Sagar Karandikar <sagark@eecs.berkeley.edu>\nCc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Palmer Dabbelt <palmer@sifive.com>\nSigned-off-by: Michael Clark <mjc@sifive.com>","distinct":true,"url":"https://api.github.com/repos/michaeljclark/riscv-qemu/commits/7125e4be0dacb8cfb041ca43666fabecf0b67c9c"},{"sha":"fefb74ccd5e9f3f3b13992c44116736e9943830b","author":{"name":"Michael Clark","email":"90d5b738658411aed8489ac35edde876bcc37b1d@sifive.com"},"message":"RISC-V: Fix riscv_isa_string memory size bug\n\nThis version uses a constant size memory buffer sized for\nthe maximum possible ISA string length. It also uses g_new\ninstead of g_new0, uses more efficient logic to append\nextensions and adds manual zero termination of the string.\n\nCc: Palmer Dabbelt <palmer@sifive.com>\nCc: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Michael Clark <mjc@sifive.com>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>","distinct":true,"url":"https://api.github.com/repos/michaeljclark/riscv-qemu/commits/fefb74ccd5e9f3f3b13992c44116736e9943830b"}]}
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