{"action":"created","issue":{"url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/773","repository_url":"https://api.github.com/repos/KiCad/kicad-symbols","labels_url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/773/labels{/name}","comments_url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/773/comments","events_url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/773/events","html_url":"https://github.com/KiCad/kicad-symbols/pull/773","id":342619255,"node_id":"MDExOlB1bGxSZXF1ZXN0MjAyNDc0OTAz","number":773,"title":"DDR3 SDRAM","user":{"login":"vlunyov","id":20477142,"node_id":"MDQ6VXNlcjIwNDc3MTQy","avatar_url":"https://avatars3.githubusercontent.com/u/20477142?v=4","gravatar_id":"","url":"https://api.github.com/users/vlunyov","html_url":"https://github.com/vlunyov","followers_url":"https://api.github.com/users/vlunyov/followers","following_url":"https://api.github.com/users/vlunyov/following{/other_user}","gists_url":"https://api.github.com/users/vlunyov/gists{/gist_id}","starred_url":"https://api.github.com/users/vlunyov/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/vlunyov/subscriptions","organizations_url":"https://api.github.com/users/vlunyov/orgs","repos_url":"https://api.github.com/users/vlunyov/repos","events_url":"https://api.github.com/users/vlunyov/events{/privacy}","received_events_url":"https://api.github.com/users/vlunyov/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2018-07-19T07:59:07Z","updated_at":"2018-07-19T10:56:45Z","closed_at":null,"author_association":"CONTRIBUTOR","pull_request":{"url":"https://api.github.com/repos/KiCad/kicad-symbols/pulls/773","html_url":"https://github.com/KiCad/kicad-symbols/pull/773","diff_url":"https://github.com/KiCad/kicad-symbols/pull/773.diff","patch_url":"https://github.com/KiCad/kicad-symbols/pull/773.patch"},"body":"Added all modern Micron DDR3L SDRAM chips 1/2/4/8 Gb with all possible data bus width 4/8/16 bit.\r\nOne common (manufacturer independent) x16bit DDR3(L) SDRAM 1-8Gb was added too.\r\nhttps://www.micron.com/products/dram/ddr3-sdram\r\nTwo footprints BGA-96 and BGA-78 were used. Pitch 0.8mm.\r\n\r\nList of added components:\r\n![ddr3](https://user-images.githubusercontent.com/20477142/42928998-78d565d6-8b41-11e8-8b0a-bfca1070bccd.png)\r\n\r\nExample drawing:\r\n![mt41k512m16](https://user-images.githubusercontent.com/20477142/42929332-6d6b9c1e-8b42-11e8-87b0-db6d2edec47e.png)\r\n\r\n"},"comment":{"url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/comments/406237448","html_url":"https://github.com/KiCad/kicad-symbols/pull/773#issuecomment-406237448","issue_url":"https://api.github.com/repos/KiCad/kicad-symbols/issues/773","id":406237448,"node_id":"MDEyOklzc3VlQ29tbWVudDQwNjIzNzQ0OA==","user":{"login":"poeschlr","id":18327350,"node_id":"MDQ6VXNlcjE4MzI3MzUw","avatar_url":"https://avatars0.githubusercontent.com/u/18327350?v=4","gravatar_id":"","url":"https://api.github.com/users/poeschlr","html_url":"https://github.com/poeschlr","followers_url":"https://api.github.com/users/poeschlr/followers","following_url":"https://api.github.com/users/poeschlr/following{/other_user}","gists_url":"https://api.github.com/users/poeschlr/gists{/gist_id}","starred_url":"https://api.github.com/users/poeschlr/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/poeschlr/subscriptions","organizations_url":"https://api.github.com/users/poeschlr/orgs","repos_url":"https://api.github.com/users/poeschlr/repos","events_url":"https://api.github.com/users/poeschlr/events{/privacy}","received_events_url":"https://api.github.com/users/poeschlr/received_events","type":"User","site_admin":false},"created_at":"2018-07-19T10:56:45Z","updated_at":"2018-07-19T10:56:45Z","author_association":"CONTRIBUTOR","body":"You are certainly free to fix other symbols as well but it is definitely not required.\r\n\r\nIf you keep the geometry changes to a minimum it should be ok."}}
{"actor":{"display_login":"poeschlr"}}