{"action":"created","comment":{"url":"https://api.github.com/repos/OPAE/opae-sdk/pulls/comments/224771170","pull_request_review_id":164224682,"id":224771170,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDIyNDc3MTE3MA==","diff_hunk":"@@ -0,0 +1,129 @@\n+// Copyright(c) 2018, Intel Corporation\n+//\n+// Redistribution  and  use  in source  and  binary  forms,  with  or  without\n+// modification, are permitted provided that the following conditions are met:\n+//\n+// * Redistributions of  source code  must retain the  above copyright notice,\n+//   this list of conditions and the following disclaimer.\n+// * Redistributions in binary form must reproduce the above copyright notice,\n+//   this list of conditions and the following disclaimer in the documentation\n+//   and/or other materials provided with the distribution.\n+// * Neither the name  of Intel Corporation  nor the names of its contributors\n+//   may be used to  endorse or promote  products derived  from this  software\n+//   without specific prior written permission.\n+//\n+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE\n+// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE\n+// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR\n+// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF\n+// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS\n+// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN\n+// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)\n+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE\n+// POSSIBILITY OF SUCH DAMAGE.\n+// **************************************************************************\n+\n+#ifndef _ASE_HOST_MEMORY_H_\n+#define _ASE_HOST_MEMORY_H_\n+\n+//\n+// Definitions for accessing host memory from the FPGA simulator.  Host\n+// memory address mapping and contents are managed entirely in the application.\n+// The RTL simulator sends requests to the application for all reads, writes\n+// and address translation.\n+//\n+// The primary reason for handling all memory in the application instead of\n+// by allocating shared memory buffers with the simulator is to be able\n+// to map and access an arbitrary location from the FPGA, even if the page\n+// is already mapped and in use by the application.  It is nearly impossible\n+// in Linux to reclassify an existing memory page as shared.  Handling all\n+// accesses on the application side makes shared mapping unnecessary.\n+//\n+\n+//\n+// Requests types that may be sent from simulator to application.\n+//\n+typedef enum {\n+\tHOST_MEM_REQ_READ_LINE,","path":"ase/sw/ase_host_memory.h","position":49,"original_position":49,"commit_id":"21eec77c372c136ba55a561a4dd25521c66fdffe","original_commit_id":"21eec77c372c136ba55a561a4dd25521c66fdffe","user":{"login":"michael-adler","id":10950878,"node_id":"MDQ6VXNlcjEwOTUwODc4","avatar_url":"https://avatars0.githubusercontent.com/u/10950878?v=4","gravatar_id":"","url":"https://api.github.com/users/michael-adler","html_url":"https://github.com/michael-adler","followers_url":"https://api.github.com/users/michael-adler/followers","following_url":"https://api.github.com/users/michael-adler/following{/other_user}","gists_url":"https://api.github.com/users/michael-adler/gists{/gist_id}","starred_url":"https://api.github.com/users/michael-adler/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/michael-adler/subscriptions","organizations_url":"https://api.github.com/users/michael-adler/orgs","repos_url":"https://api.github.com/users/michael-adler/repos","events_url":"https://api.github.com/users/michael-adler/events{/privacy}","received_events_url":"https://api.github.com/users/michael-adler/received_events","type":"User","site_admin":false},"body":"Yes.","created_at":"2018-10-12T12:45:48Z","updated_at":"2018-10-12T12:45:48Z","html_url":"https://github.com/OPAE/opae-sdk/pull/766#discussion_r224771170","pull_request_url":"https://api.github.com/repos/OPAE/opae-sdk/pulls/766","author_association":"MEMBER","_links":{"self":{"href":"https://api.github.com/repos/OPAE/opae-sdk/pulls/comments/224771170"},"html":{"href":"https://github.com/OPAE/opae-sdk/pull/766#discussion_r224771170"},"pull_request":{"href":"https://api.github.com/repos/OPAE/opae-sdk/pulls/766"}},"in_reply_to_id":224628016},"pull_request":{"url":"https://api.github.com/repos/OPAE/opae-sdk/pulls/766","id":221523464,"node_id":"MDExOlB1bGxSZXF1ZXN0MjIxNTIzNDY0","html_url":"https://github.com/OPAE/opae-sdk/pull/766","diff_url":"https://github.com/OPAE/opae-sdk/pull/766.diff","patch_url":"https://github.com/OPAE/opae-sdk/pull/766.patch","issue_url":"https://api.github.com/repos/OPAE/opae-sdk/issues/766","number":766,"state":"open","locked":false,"title":"Add support for FPGA_BUF_PREALLOCATED to fpgaPrepareBuffer() in ASE","user":{"login":"michael-adler","id":10950878,"node_id":"MDQ6VXNlcjEwOTUwODc4","avatar_url":"https://avatars0.githubusercontent.com/u/10950878?v=4","gravatar_id":"","url":"https://api.github.com/users/michael-adler","html_url":"https://github.com/michael-adler","followers_url":"https://api.github.com/users/michael-adler/followers","following_url":"https://api.github.com/users/michael-adler/following{/other_user}","gists_url":"https://api.github.com/users/michael-adler/gists{/gist_id}","starred_url":"https://api.github.com/users/michael-adler/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/michael-adler/subscriptions","organizations_url":"https://api.github.com/users/michael-adler/orgs","repos_url":"https://api.github.com/users/michael-adler/repos","events_url":"https://api.github.com/users/michael-adler/events{/privacy}","received_events_url":"https://api.github.com/users/michael-adler/received_events","type":"User","site_admin":false},"body":"Allowing the mapping of pre-allocated memory forces a rearchitecting of the way the RTL simulator and the application share memory. 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More refined error detection now reports accesses to addresses where the virtually mapped pages have been unmapped improperly.\r\n- Improved pinned buffer management allows many more pages to be mapped without performance loss.\r\n- Various logging bug fixes, e.g. logging of pinned buffer addresses and 64 bit MMIO write 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