{"action":"created","issue":{"url":"https://api.github.com/repos/nvdla/hw/issues/110","repository_url":"https://api.github.com/repos/nvdla/hw","labels_url":"https://api.github.com/repos/nvdla/hw/issues/110/labels{/name}","comments_url":"https://api.github.com/repos/nvdla/hw/issues/110/comments","events_url":"https://api.github.com/repos/nvdla/hw/issues/110/events","html_url":"https://github.com/nvdla/hw/issues/110","id":309539120,"number":110,"title":"NVDLA running on a FPGA platform","user":{"login":"ratnayak","id":35048817,"avatar_url":"https://avatars1.githubusercontent.com/u/35048817?v=4","gravatar_id":"","url":"https://api.github.com/users/ratnayak","html_url":"https://github.com/ratnayak","followers_url":"https://api.github.com/users/ratnayak/followers","following_url":"https://api.github.com/users/ratnayak/following{/other_user}","gists_url":"https://api.github.com/users/ratnayak/gists{/gist_id}","starred_url":"https://api.github.com/users/ratnayak/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ratnayak/subscriptions","organizations_url":"https://api.github.com/users/ratnayak/orgs","repos_url":"https://api.github.com/users/ratnayak/repos","events_url":"https://api.github.com/users/ratnayak/events{/privacy}","received_events_url":"https://api.github.com/users/ratnayak/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":14,"created_at":"2018-03-28T21:30:28Z","updated_at":"2018-05-09T14:34:12Z","closed_at":null,"author_association":"NONE","body":"This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .\r\n\r\nwe are putting nv_full (as nv_small is not available as yet) on Xilinx VU440 (largest FPGA by Xilinx). nv_full fits comfortably on VU440 utilizing about 82% LUTs as per Vivado implementation.\r\nwe'd have the host running on an ARM A53 processor on a Xilinx Zynq (ASIC ARM). the signalling between two FPGAs--Zynq(host) and VU440(nv_full) will be via direct parallel connections (simple & straightforward) and we have enough IOs for this.\r\n\r\na) we'd like to know if anyone out there has already implemented nv_full on a FPGA platform and successful in getting it running as expected.\r\nb) we would very much like to sync w you--either you got it running or still some distance to go-- perhaps we can discuss details, inputs on issues encountered, how resolved them etc.\r\n\r\nlook forward to hearing from you."},"comment":{"url":"https://api.github.com/repos/nvdla/hw/issues/comments/387759854","html_url":"https://github.com/nvdla/hw/issues/110#issuecomment-387759854","issue_url":"https://api.github.com/repos/nvdla/hw/issues/110","id":387759854,"user":{"login":"giusecesa4","id":31472608,"avatar_url":"https://avatars1.githubusercontent.com/u/31472608?v=4","gravatar_id":"","url":"https://api.github.com/users/giusecesa4","html_url":"https://github.com/giusecesa4","followers_url":"https://api.github.com/users/giusecesa4/followers","following_url":"https://api.github.com/users/giusecesa4/following{/other_user}","gists_url":"https://api.github.com/users/giusecesa4/gists{/gist_id}","starred_url":"https://api.github.com/users/giusecesa4/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/giusecesa4/subscriptions","organizations_url":"https://api.github.com/users/giusecesa4/orgs","repos_url":"https://api.github.com/users/giusecesa4/repos","events_url":"https://api.github.com/users/giusecesa4/events{/privacy}","received_events_url":"https://api.github.com/users/giusecesa4/received_events","type":"User","site_admin":false},"created_at":"2018-05-09T14:34:12Z","updated_at":"2018-05-09T14:34:12Z","author_association":"NONE","body":"Thanks, it helped a lot"}}
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