{"action":"created","issue":{"url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/1499","repository_url":"https://api.github.com/repos/projectacrn/acrn-hypervisor","labels_url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/1499/labels{/name}","comments_url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/1499/comments","events_url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/1499/events","html_url":"https://github.com/projectacrn/acrn-hypervisor/pull/1499","id":370963298,"node_id":"MDExOlB1bGxSZXF1ZXN0MjIzNTE2OTA4","number":1499,"title":"DM: add MSI and INTR support for i6300esb watchdog","user":{"login":"jsun26intel","id":36183416,"node_id":"MDQ6VXNlcjM2MTgzNDE2","avatar_url":"https://avatars0.githubusercontent.com/u/36183416?v=4","gravatar_id":"","url":"https://api.github.com/users/jsun26intel","html_url":"https://github.com/jsun26intel","followers_url":"https://api.github.com/users/jsun26intel/followers","following_url":"https://api.github.com/users/jsun26intel/following{/other_user}","gists_url":"https://api.github.com/users/jsun26intel/gists{/gist_id}","starred_url":"https://api.github.com/users/jsun26intel/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jsun26intel/subscriptions","organizations_url":"https://api.github.com/users/jsun26intel/orgs","repos_url":"https://api.github.com/users/jsun26intel/repos","events_url":"https://api.github.com/users/jsun26intel/events{/privacy}","received_events_url":"https://api.github.com/users/jsun26intel/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2018-10-17T08:48:02Z","updated_at":"2018-10-18T01:29:37Z","closed_at":null,"author_association":"CONTRIBUTOR","pull_request":{"url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/pulls/1499","html_url":"https://github.com/projectacrn/acrn-hypervisor/pull/1499","diff_url":"https://github.com/projectacrn/acrn-hypervisor/pull/1499.diff","patch_url":"https://github.com/projectacrn/acrn-hypervisor/pull/1499.patch"},"body":"Per i6300esb spec, when WDT_INT_TYPE(bit 0 and 1 of WDT config register)\r\nare set to 00, IRQ feature should be supported.\r\n\r\nThe WDT_INT_ACTIVE bit is set when the first stage of the 35-bit\r\ndown-counter reaches zero. An interrupt will be generated if WDT_INT_TYPE\r\nis configured to do so (See WDT Configuration Register). This is a sticky\r\nbit and is only cleared by writing a 1.\r\n\r\nSMI feature(WDT_INT_TYPE are set to 0x10) is not supported.\r\n\r\nTracked-On: #1498\r\nSigned-off-by: Victor Sun <victor.sun@intel.com>\r\nAcked-by: Yin Fengwei <fengwei.yin@intel.com>"},"comment":{"url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/comments/430844158","html_url":"https://github.com/projectacrn/acrn-hypervisor/pull/1499#issuecomment-430844158","issue_url":"https://api.github.com/repos/projectacrn/acrn-hypervisor/issues/1499","id":430844158,"node_id":"MDEyOklzc3VlQ29tbWVudDQzMDg0NDE1OA==","user":{"login":"ClaudZhang1995","id":37544522,"node_id":"MDQ6VXNlcjM3NTQ0NTIy","avatar_url":"https://avatars1.githubusercontent.com/u/37544522?v=4","gravatar_id":"","url":"https://api.github.com/users/ClaudZhang1995","html_url":"https://github.com/ClaudZhang1995","followers_url":"https://api.github.com/users/ClaudZhang1995/followers","following_url":"https://api.github.com/users/ClaudZhang1995/following{/other_user}","gists_url":"https://api.github.com/users/ClaudZhang1995/gists{/gist_id}","starred_url":"https://api.github.com/users/ClaudZhang1995/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ClaudZhang1995/subscriptions","organizations_url":"https://api.github.com/users/ClaudZhang1995/orgs","repos_url":"https://api.github.com/users/ClaudZhang1995/repos","events_url":"https://api.github.com/users/ClaudZhang1995/events{/privacy}","received_events_url":"https://api.github.com/users/ClaudZhang1995/received_events","type":"User","site_admin":false},"created_at":"2018-10-18T01:29:37Z","updated_at":"2018-10-18T01:29:37Z","author_association":"NONE","body":"Ready to merge"}}
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