{"action":"created","comment":{"url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/comments/199728420","pull_request_review_id":133889153,"id":199728420,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDE5OTcyODQyMA==","diff_hunk":"@@ -0,0 +1,825 @@\n+/*\n+ * Copyright (C) 2018 Marvell International Ltd.\n+ *\n+ * SPDX-License-Identifier:     BSD-3-Clause\n+ * https://spdx.org/licenses\n+ */\n+\n+#include <assert.h>\n+#include <bakery_lock.h>\n+#include <debug.h>\n+#include <delay_timer.h>\n+#include <cache_llc.h>\n+#include <console.h>\n+#include <gicv2.h>\n+#include <marvell_pm.h>\n+#include <mmio.h>\n+#include <mss_pm_ipc.h>\n+#include <plat_config.h>\n+#include <plat_marvell.h>\n+#include <platform.h>\n+#include <plat_pm_trace.h>\n+#include <platform.h>\n+\n+#define MVEBU_PRIVATE_UID_REG\t\t0x30\n+#define MVEBU_RFU_GLOBL_SW_RST\t\t0x84\n+#define MVEBU_CCU_RVBAR(cpu)\t\t(MVEBU_REGS_BASE + 0x640 + (cpu * 4))\n+#define MVEBU_CCU_CPU_UN_RESET(cpu)\t(MVEBU_REGS_BASE + 0x650 + (cpu * 4))\n+\n+#define MPIDR_CPU_GET(mpidr)\t\t((mpidr) & MPIDR_CPU_MASK)\n+#define MPIDR_CLUSTER_GET(mpidr)\tMPIDR_AFFLVL1_VAL((mpidr))\n+\n+#define MVEBU_GPIO_MASK(index)\t\t(1 << (index % 32))\n+#define MVEBU_MPP_MASK(index)\t\t(0xF << (4 * (index % 8)))\n+#define MVEBU_GPIO_VALUE(index, value)\t(value << (index % 32))\n+\n+#define MVEBU_USER_CMD_0_REG\t\t(MVEBU_DRAM_MAC_BASE + 0x20)\n+#define MVEBU_USER_CMD_CH0_OFFSET\t28\n+#define MVEBU_USER_CMD_CH0_MASK\t\t(1 << MVEBU_USER_CMD_CH0_OFFSET)\n+#define MVEBU_USER_CMD_CH0_EN\t\t(1 << MVEBU_USER_CMD_CH0_OFFSET)\n+#define MVEBU_USER_CMD_CS_OFFSET\t24\n+#define MVEBU_USER_CMD_CS_MASK\t\t(0xF << MVEBU_USER_CMD_CS_OFFSET)\n+#define MVEBU_USER_CMD_CS_ALL\t\t(0xF << MVEBU_USER_CMD_CS_OFFSET)\n+#define MVEBU_USER_CMD_SR_OFFSET\t6\n+#define MVEBU_USER_CMD_SR_MASK\t\t(0x3 << MVEBU_USER_CMD_SR_OFFSET)\n+#define MVEBU_USER_CMD_SR_ENTER\t\t(0x1 << MVEBU_USER_CMD_SR_OFFSET)\n+#define MVEBU_MC_PWR_CTRL_REG\t\t(MVEBU_DRAM_MAC_BASE + 0x54)\n+#define MVEBU_MC_AC_ON_DLY_OFFSET\t8\n+#define MVEBU_MC_AC_ON_DLY_MASK\t\t(0xF << MVEBU_MC_AC_ON_DLY_OFFSET)\n+#define MVEBU_MC_AC_ON_DLY_DEF_VAR\t(8 << MVEBU_MC_AC_ON_DLY_OFFSET)\n+#define MVEBU_MC_AC_OFF_DLY_OFFSET\t4\n+#define MVEBU_MC_AC_OFF_DLY_MASK\t(0xF << MVEBU_MC_AC_OFF_DLY_OFFSET)\n+#define MVEBU_MC_AC_OFF_DLY_DEF_VAR\t(0xC << MVEBU_MC_AC_OFF_DLY_OFFSET)\n+#define MVEBU_MC_PHY_AUTO_OFF_OFFSET\t0\n+#define MVEBU_MC_PHY_AUTO_OFF_MASK\t(1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET)\n+#define MVEBU_MC_PHY_AUTO_OFF_EN\t(1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET)\n+\n+/* this lock synchronize AP multiple cores execution with MSS */\n+DEFINE_BAKERY_LOCK(pm_sys_lock);\n+\n+/* Weak definitions may be overridden in specific board */\n+#pragma weak plat_get_pm_cfg\n+\n+/* AP806 CPU power down /power up definitions */\n+enum CPU_ID {\n+\tCPU0,\n+\tCPU1,\n+\tCPU2,\n+\tCPU3\n+};\n+\n+#define REG_WR_VALIDATE_TIMEOUT\t\t(2000)\n+\n+#define FEATURE_DISABLE_STATUS_REG\t\t\t\\\n+\t\t\t(MVEBU_REGS_BASE + 0x6F8230)\n+#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET\t4\n+#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK\t\t\\\n+\t\t\t(0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET)\n+\n+#ifdef MVEBU_SOC_AP807\n+\t#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET\t\t1\n+\t#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET\t0\n+#else\n+#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET\t\t0\n+\t#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET\t31\n+#endif\n+\n+#define PWRC_CPUN_CR_REG(cpu_id)\t\t\\\n+\t\t\t(MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))\n+#define PWRC_CPUN_CR_PWR_DN_RQ_MASK\t\t\\\n+\t\t\t(0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET)\n+#define PWRC_CPUN_CR_ISO_ENABLE_OFFSET\t\t16\n+#define PWRC_CPUN_CR_ISO_ENABLE_MASK\t\t\\\n+\t\t\t(0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)\n+#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK\t\\\n+\t\t\t(0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)\n+\n+#define CCU_B_PRCRN_REG(cpu_id)\t\t\t\\\n+\t\t\t(MVEBU_REGS_BASE + 0x1A50 + \\\n+\t\t\t((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4))\n+#define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET\t0\n+#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK\t\\\n+\t\t\t(0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)\n+\n+/* power switch fingers */\n+#define AP807_PWRC_LDO_CR0_REG\t\t\t\\\n+\t\t\t(MVEBU_REGS_BASE + 0x680000 + 0x100)\n+#define AP807_PWRC_LDO_CR0_OFFSET\t\t16\n+#define AP807_PWRC_LDO_CR0_MASK\t\t\t\\\n+\t\t\t(0xff << AP807_PWRC_LDO_CR0_OFFSET)\n+#define AP807_PWRC_LDO_CR0_VAL\t\t\t0xfd\n+\n+/*\n+ * Power down CPU:\n+ * Used to reduce power consumption, and avoid SoC unnecessary temperature rise.\n+ */\n+static int plat_marvell_cpu_powerdown(int cpu_id)\n+{\n+\tuint32_t\treg_val;\n+\tint\t\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\n+\tINFO(\"Powering down CPU%d\\n\", cpu_id);\n+\n+\t/* 1. Isolation enable */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 2. Read and check Isolation enabled - verify bit set to 1 */\n+\tdo {\n+\t\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) &&\n+\t\t exit_loop > 0);\n+\n+\t/* 3. Switch off CPU power */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 4. Read and check Switch Off - verify bit set to 0 */\n+\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\tdo {\n+\t\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while (reg_val & PWRC_CPUN_CR_PWR_DN_RQ_MASK && exit_loop > 0);\n+\n+\tif (exit_loop <= 0)\n+\t\tgoto cpu_poweroff_error;\n+\n+\t/* 5. De-Assert power ready */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val &= ~PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 6. Assert CPU POR reset */\n+\treg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));\n+\treg_val &= ~CCU_B_PRCRN_CPUPORESET_STATIC_MASK;\n+\tmmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val);\n+\n+\t/* 7. Read and poll on Validate the CPU is out of reset */\n+\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\tdo {\n+\t\treg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while (reg_val & CCU_B_PRCRN_CPUPORESET_STATIC_MASK && exit_loop > 0);\n+\n+\tif (exit_loop <= 0)\n+\t\tgoto cpu_poweroff_error;\n+\n+\tINFO(\"Successfully powered down CPU%d\\n\", cpu_id);\n+\n+\treturn 0;\n+\n+cpu_poweroff_error:\n+\tERROR(\"ERROR: Can't power down CPU%d\\n\", cpu_id);\n+\treturn -1;\n+}\n+\n+/*\n+ * Power down CPUs 1-3 at early boot stage,\n+ * to reduce power consumption and SoC temperature.\n+ * This is triggered by BLE prior to DDR initialization.\n+ *\n+ * Note:\n+ * All CPUs will be powered up by plat_marvell_cpu_powerup on Linux boot stage,\n+ * which is triggered by PSCI ops (pwr_domain_on).\n+ */\n+int plat_marvell_early_cpu_powerdown(void)\n+{\n+\tuint32_t cpu_cluster_status =\n+\t\tmmio_read_32(FEATURE_DISABLE_STATUS_REG) &\n+\t\t\t     FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK;\n+\t/* if cpu_cluster_status bit is set,\n+\t * that means we have only single cluster\n+\t */\n+\tint cluster_count = cpu_cluster_status ? 1 : 2;\n+\n+\tINFO(\"Powering off unused CPUs\\n\");\n+\n+\t/* CPU1 is in AP806 cluster-0, which always exists, so power it down */\n+\tif (plat_marvell_cpu_powerdown(CPU1) == -1)\n+\t\treturn -1;\n+\n+\t/*\n+\t * CPU2-3 are in AP806 2nd cluster (cluster-1),\n+\t * which doesn't exists in dual-core systems.\n+\t * so need to check if we have dual-core (single cluster)\n+\t * or quad-code (2 clusters)\n+\t */\n+\tif (cluster_count == 2) {\n+\t\t/* CPU2-3 are part of 2nd cluster */\n+\t\tif (plat_marvell_cpu_powerdown(CPU2) == -1)\n+\t\t\treturn -1;\n+\t\tif (plat_marvell_cpu_powerdown(CPU3) == -1)\n+\t\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Power up CPU - part of Linux boot stage\n+ */\n+static int plat_marvell_cpu_powerup(u_register_t mpidr)\n+{\n+\tuint32_t\treg_val;\n+\tint\tcpu_id = MPIDR_CPU_GET(mpidr),\n+\t\tcluster = MPIDR_CLUSTER_GET(mpidr);\n+\tint\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\n+\t/* calculate absolute CPU ID */\n+\tcpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id;\n+\n+\tINFO(\"Powering on CPU%d\\n\", cpu_id);\n+\n+#ifdef MVEBU_SOC_AP807\n+\t/* Activate 2 power switch fingers */\n+\treg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG);\n+\treg_val &= ~(AP807_PWRC_LDO_CR0_MASK);\n+\treg_val |= (AP807_PWRC_LDO_CR0_VAL << AP807_PWRC_LDO_CR0_OFFSET);\n+\tmmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val);\n+\tudelay(100);\n+#endif\n+\n+\t/* 1. Switch CPU power ON */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val |= 0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 2. Wait for CPU on, up to 100 uSec: */\n+\tudelay(100);\n+\n+\t/* 3. Assert power ready */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 4. Read & Validate power ready\n+\t * used in order to generate 16 Host CPU cycles\n+\t */\n+\tdo {\n+\t\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&\n+\t\t exit_loop > 0);\n+\n+\tif (exit_loop <= 0)\n+\t\tgoto cpu_poweron_error;\n+\n+\t/* 5. Isolation disable */\n+\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\treg_val &= ~PWRC_CPUN_CR_ISO_ENABLE_MASK;\n+\tmmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);\n+\n+\t/* 6. Read and check Isolation enabled - verify bit set to 1 */\n+\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\tdo {\n+\t\treg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while ((reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) &&\n+\t\t exit_loop > 0);\n+\n+\t/* 7. De Assert CPU POR reset & Core reset */\n+\treg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));\n+\treg_val |= 0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET;\n+\tmmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val);\n+\n+\t/* 8. Read & Validate CPU POR reset */\n+\texit_loop = REG_WR_VALIDATE_TIMEOUT;\n+\tdo {\n+\t\treg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));\n+\t\texit_loop--;\n+\t} while (!(reg_val & (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)) &&\n+\t\t exit_loop > 0);\n+\n+\tif (exit_loop <= 0)\n+\t\tgoto cpu_poweron_error;\n+\n+\tINFO(\"Successfully powered on CPU%d\\n\", cpu_id);\n+\n+\treturn 0;\n+\n+cpu_poweron_error:\n+\tERROR(\"ERROR: Can't power up CPU%d\\n\", cpu_id);\n+\treturn -1;\n+}\n+\n+static int plat_marvell_cpu_on(u_register_t mpidr)\n+{\n+\tint cpu_id;\n+\tint cluster;\n+\n+\t/* Set barierr */\n+\tdsbsy();\n+\n+\t/* Get cpu number - use CPU ID */\n+\tcpu_id =  MPIDR_CPU_GET(mpidr);\n+\n+\t/* Get cluster number - use affinity level 1 */\n+\tcluster = MPIDR_CLUSTER_GET(mpidr);\n+\n+\t/* Set CPU private UID */\n+\tmmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4);\n+\n+\t/* Set the cpu start address to BL1 entry point (align to 0x10000) */\n+\tmmio_write_32(MVEBU_CCU_RVBAR(cpu_id),\n+\t\t      PLAT_MARVELL_CPU_ENTRY_ADDR >> 16);\n+\n+\t/* Get the cpu out of reset */\n+\tmmio_write_32(MVEBU_CCU_CPU_UN_RESET(cpu_id), 0x10001);\n+\n+\treturn 0;\n+}\n+\n+/*****************************************************************************\n+ * A8K handler called to check the validity of the power state\n+ * parameter.\n+ *****************************************************************************\n+ */\n+static int a8k_validate_power_state(unsigned int power_state,\n+\t\t\t    psci_power_state_t *req_state)\n+{\n+\tint pstate = psci_get_pstate_type(power_state);\n+\tint pwr_lvl = psci_get_pstate_pwrlvl(power_state);\n+\tint i;\n+\n+\tif (pwr_lvl > PLAT_MAX_PWR_LVL)\n+\t\treturn PSCI_E_INVALID_PARAMS;\n+\n+\t/* Sanity check the requested state */\n+\tif (pstate == PSTATE_TYPE_STANDBY) {\n+\t\t/*\n+\t\t * It's possible to enter standby only on power level 0\n+\t\t * Ignore any other power level.\n+\t\t */\n+\t\tif (pwr_lvl != MARVELL_PWR_LVL0)\n+\t\t\treturn PSCI_E_INVALID_PARAMS;\n+\n+\t\treq_state->pwr_domain_state[MARVELL_PWR_LVL0] =\n+\t\t\t\t\tMARVELL_LOCAL_STATE_RET;\n+\t} else {\n+\t\tfor (i = MARVELL_PWR_LVL0; i <= pwr_lvl; i++)\n+\t\t\treq_state->pwr_domain_state[i] =\n+\t\t\t\t\tMARVELL_LOCAL_STATE_OFF;\n+\t}\n+\n+\t/*\n+\t * We expect the 'state id' to be zero.\n+\t */\n+\tif (psci_get_pstate_id(power_state))\n+\t\treturn PSCI_E_INVALID_PARAMS;\n+\n+\treturn PSCI_E_SUCCESS;\n+}\n+\n+/*****************************************************************************\n+ * A8K handler called when a CPU is about to enter standby.\n+ *****************************************************************************\n+ */\n+static void a8k_cpu_standby(plat_local_state_t cpu_state)\n+{\n+\tERROR(\"%s: needs to be implemented\\n\", __func__);\n+\tpanic();\n+}\n+\n+/*****************************************************************************\n+ * A8K handler called when a power domain is about to be turned on. The\n+ * mpidr determines the CPU to be turned on.\n+ *****************************************************************************\n+ */\n+static int a8k_pwr_domain_on(u_register_t mpidr)\n+{\n+\t/* Power up CPU (CPUs 1-3 are powered off at start of BLE) */\n+\tplat_marvell_cpu_powerup(mpidr);\n+\n+\tif (is_pm_fw_running()) {\n+\t\tunsigned int target =\n+\t\t\t\t((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));\n+\n+\t\t/*\n+\t\t * pm system synchronization - used to synchronize\n+\t\t * multiple core access to MSS\n+\t\t */\n+\t\tbakery_lock_get(&pm_sys_lock);\n+\n+\t\t/* send CPU ON IPC Message to MSS */\n+\t\tmss_pm_ipc_msg_send(target, PM_IPC_MSG_CPU_ON, 0);\n+\n+\t\t/* trigger IPC message to MSS */\n+\t\tmss_pm_ipc_msg_trigger();\n+\n+\t\t/* pm system synchronization */\n+\t\tbakery_lock_release(&pm_sys_lock);\n+\n+\t\t/* trace message */\n+\t\tPM_TRACE(TRACE_PWR_DOMAIN_ON | target);\n+\t} else {\n+\t\t/* proprietary CPU ON exection flow */\n+\t\tplat_marvell_cpu_on(mpidr);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*****************************************************************************\n+ * A8K handler called to validate the entry point.\n+ *****************************************************************************\n+ */\n+static int a8k_validate_ns_entrypoint(uintptr_t entrypoint)\n+{\n+\treturn PSCI_E_SUCCESS;\n+}\n+\n+/*****************************************************************************\n+ * A8K handler called when a power domain is about to be turned off. The\n+ * target_state encodes the power state that each level should transition to.\n+ *****************************************************************************\n+ */\n+static void a8k_pwr_domain_off(const psci_power_state_t *target_state)\n+{\n+\tif (is_pm_fw_running()) {\n+\t\tunsigned int idx = plat_my_core_pos();\n+\n+\t\t/* Prevent interrupts from spuriously waking up this cpu */\n+\t\tgicv2_cpuif_disable();\n+\n+\t\t/* pm system synchronization - used to synchronize multiple\n+\t\t * core access to MSS\n+\t\t */\n+\t\tbakery_lock_get(&pm_sys_lock);\n+\n+\t\t/* send CPU OFF IPC Message to MSS */\n+\t\tmss_pm_ipc_msg_send(idx, PM_IPC_MSG_CPU_OFF, target_state);\n+\n+\t\t/* trigger IPC message to MSS */\n+\t\tmss_pm_ipc_msg_trigger();\n+\n+\t\t/* pm system synchronization */\n+\t\tbakery_lock_release(&pm_sys_lock);\n+\n+\t\t/* trace message */\n+\t\tPM_TRACE(TRACE_PWR_DOMAIN_OFF);\n+\t} else {\n+\t\tINFO(\"%s: is not supported without SCP\\n\", __func__);\n+\t}\n+}\n+\n+/* Get PM config to power off the SoC */\n+void *plat_get_pm_cfg(void)\n+{\n+\treturn NULL;\n+}\n+\n+/*\n+ * This function should be called on restore from\n+ * \"suspend to RAM\" state when the execution flow\n+ * has to bypass BootROM image to RAM copy and speed up\n+ * the system recovery\n+ *\n+ */\n+static void plat_exit_bootrom(void)\n+{\n+\texit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE);\n+}\n+\n+/*\n+ * Prepare for the power off of the system via GPIO\n+ */\n+static void plat_marvell_power_off_gpio(struct power_off_method *pm_cfg)\n+{\n+\tunsigned int gpio;\n+\tunsigned int idx;\n+\tunsigned int shift;\n+\tunsigned int reg;\n+\tunsigned int addr;\n+\tgpio_info_t *info;\n+\tunsigned int tog_bits;\n+\n+\tassert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) &&\n+\t       (pm_cfg->cfg.gpio.step_count < PMIC_GPIO_MAX_TOGGLE_STEP));\n+\n+\t/* Prepare GPIOs for PMIC */\n+\tfor (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) {\n+\t\tinfo = &pm_cfg->cfg.gpio.info[gpio];\n+\t\t/* Set PMIC GPIO to output mode */\n+\t\treg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT_EN(\n+\t\t\t\t   info->cp_index, info->gpio_index));\n+\t\tmmio_write_32(MVEBU_CP_GPIO_DATA_OUT_EN(\n+\t\t\t      info->cp_index, info->gpio_index),\n+\t\t\t      reg & ~MVEBU_GPIO_MASK(info->gpio_index));\n+\n+\t\t/* Set the appropriate MPP to GPIO mode */\n+\t\treg = mmio_read_32(MVEBU_PM_MPP_REGS(info->cp_index,\n+\t\t\t\t\t\t     info->gpio_index));\n+\t\tmmio_write_32(MVEBU_PM_MPP_REGS(info->cp_index,\n+\t\t\t\t\t\tinfo->gpio_index),\n+\t\t\treg & ~MVEBU_MPP_MASK(info->gpio_index));\n+\t}\n+\n+\t/* Wait for MPP & GPIO pre-configurations done */\n+\tmdelay(pm_cfg->cfg.gpio.delay_ms);\n+\n+\t/* Toggle the GPIO values, and leave final step to be triggered\n+\t * after  DDR self-refresh is enabled\n+\t */\n+\tfor (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) {\n+\t\ttog_bits = pm_cfg->cfg.gpio.seq[idx];\n+\n+\t\t/* The GPIOs must be within same GPIO register,\n+\t\t * thus could get the original value by first GPIO\n+\t\t */\n+\t\tinfo = &pm_cfg->cfg.gpio.info[0];\n+\t\treg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT(\n+\t\t\t\t   info->cp_index, info->gpio_index));\n+\t\taddr = MVEBU_CP_GPIO_DATA_OUT(info->cp_index, info->gpio_index);\n+\n+\t\tfor (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) {\n+\t\t\tshift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32;\n+\t\t\tif (GPIO_LOW == (tog_bits & (1 << gpio)))\n+\t\t\t\treg &= ~(1 << shift);\n+\t\t\telse\n+\t\t\t\treg |= (1 << shift);\n+\t\t}\n+\n+\t\t/* Set the GPIO register, for last step just store\n+\t\t * register address and values to system registers\n+\t\t */\n+\t\tif (idx < pm_cfg->cfg.gpio.step_count - 1) {\n+\t\t\tmmio_write_32(MVEBU_CP_GPIO_DATA_OUT(\n+\t\t\t\t      info->cp_index, info->gpio_index), reg);\n+\t\t\tmdelay(pm_cfg->cfg.gpio.delay_ms);\n+\t\t} else {\n+\t\t\t/* Save GPIO register value to X17 and address to X18 */\n+\t\t\t__asm__ volatile (\n+\t\t\t\t\"mov\tx17, %0\\n\\t\"\n+\t\t\t\t\"mov\tx18, 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