{"push_id":2461745701,"size":87,"distinct_size":87,"ref":"refs/heads/jenkins","head":"0b04a24ae3e5447c0749aa4976365cc4c5051441","before":"1c87b7f1cf587be7dbfd42ab51c95a19463cbe09","commits":[{"sha":"096942be2cb656a8f28b98905e1783adba3aae7f","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/pp: use user constant buffers\n\nThis fixes a radeonsi crash.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105026","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/096942be2cb656a8f28b98905e1783adba3aae7f"},{"sha":"8cd58df2f2592bf5a19ef7431eccaca6b8a445cc","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/pp: fix MLAA shaders\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99549","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/8cd58df2f2592bf5a19ef7431eccaca6b8a445cc"},{"sha":"a8a696a38f432b67f24e0373343b20404f703d0e","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: use a mask for VBOs and shaders prefetching\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nTested-by: Dieter Nützel <Dieter@nuetzel-hh.de>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/a8a696a38f432b67f24e0373343b20404f703d0e"},{"sha":"4ad7595f350462c704fbe5b2bd2ca406c904e78e","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nTested-by: Dieter Nützel <Dieter@nuetzel-hh.de>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/4ad7595f350462c704fbe5b2bd2ca406c904e78e"},{"sha":"942fdfe35725c95728bb6a854d9191125c2002b8","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: implement a fast prefetch path for the vertex stage\n\nThis allows to start draws as soon as possible.\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nTested-by: Dieter Nützel <Dieter@nuetzel-hh.de>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/942fdfe35725c95728bb6a854d9191125c2002b8"},{"sha":"f421a3163751f482818958d8745701ec3174ff83","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"anv/image: Do not override lower bits of dword.\n\nThe lower bits seem to have extra fields in every platform but gen8\n(even though we don't use them in gen9). So just go ahead and avoid\nusing them for the address.\n\nv4: Use Jason's suggestion for comment explaining the change.\nv5: Fix aux_address comment in anv_private.h (Jason)\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/f421a3163751f482818958d8745701ec3174ff83"},{"sha":"8e1f2e1d2dee09cf61c13c0aadf99712f59fafb9","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"genxml: Preserve fields that share dword space with addresses.\n\nSome instructions contain fields that are either an address or a value\nof some type based on the content of other fields, such as clear color\nvalues vs address. That works fine if these fields are in the less\nsignificant dword, the lower 32 bits of the address, because they get\nOR'ed with the address. But if they are in the higher 32 bits, they get\ndiscarded.\n\nOn Gen10 we have fields that share space with the higher 16 bits of the\naddress too. This commit makes sure those fields don't get discarded.\n\nv5: Remove spurious whitespace (Jason).\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/8e1f2e1d2dee09cf61c13c0aadf99712f59fafb9"},{"sha":"7e616ae2014d78e8173fd4ade7a001b85ffd0a08","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/genxml: Use a single field for clear color address on gen10.\n\ngenxml does not support having two address fields with different names\nbut same position in the state struct. Both \"Clear Color Address\"\nand \"Clear Depth Address Low\" mean the same thing, only for different\nsurface types.\n\nTo workaround this genxml limitation, rename \"Clear Color Address\"\nto \"Clear Value Address\" and use it for both color and depth. Do the\nsame for the high bits.\n\nTODO: add support for multiple addresses at the same position in the\nxml.\n\nv2: Combine high and low order bits into a single address field.\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/7e616ae2014d78e8173fd4ade7a001b85ffd0a08"},{"sha":"f77789a3f0bfd094f8d36dd50f65b5f948745eb1","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/genxml: Add Clear Color struct to gen10+.\n\nv5: Split genxml changes into its own commit (Jason).\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/f77789a3f0bfd094f8d36dd50f65b5f948745eb1"},{"sha":"94675edcfda93dab29f2ed8a1f218d6491dbb085","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel: Use Clear Color struct size.\n\nThe size of the clear color struct (expected by the hardware) is 8\ndwords (isl_dev.ss.clear_value_state_size here). But we still need to\ntrack the size of the clear color, used when memcopying it to/from the\nstate buffer. For that we keep isl_dev.ss.clear_value_size.\n\nv4:\n - Add struct to gen11 too (Jason, Jordan)\n - Add field for Converted Clear Color to gen11 (Jason)\n - Add clear_color_state_offset to differentiate from\n   clear_value_offset.\n - Fix all the places where clear_value_size was used.\n\nv5 (Jason):\n - Split genxml changes to another commit.\n - Remove unnecessary gen checks.\n - Bring back missing offset increment to init_fast_clear_color().\n\nv6 (Jason):\n - On init_fast_clear_color, change:\n   addr.offset += 4 => sdi.Address.offset += i * 4\n - Use GEN_GEN instead of GEN_VERSIONx10.\n\n[jordan.l.justen@intel.com: isl_device_init changes]\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nSigned-off-by: Jordan Justen <jordan.l.justen@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/94675edcfda93dab29f2ed8a1f218d6491dbb085"},{"sha":"b8f45cf967e1810c4e59b49b1ed1d955f01496a1","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/isl: Add support to emit clear value address.\n\ngen10 can emit the clear color by setting it on a buffer somewhere, and\nthen adding only the address to the surface state.\n\nThis commit add support for that on isl_surf_fill_state, and if that is\nrequested, skip setting the clear value itself.\n\nv2: Add assert to make sure we are at least on gen10.\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/b8f45cf967e1810c4e59b49b1ed1d955f01496a1"},{"sha":"188a473b9a198d1fb070e2635177a0fc689117b7","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/blorp: Add support for fast clear address.\n\nOn gen10+, if surface->clear_color_addr is present, use it directly\nintead of copying it to the surface state.\n\nv4: Remove redundant #if clause for GEN <= 10 (Jason)\nv5: Move flush after the reloc, and keep lower bits (Topi).\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/188a473b9a198d1fb070e2635177a0fc689117b7"},{"sha":"92eb5bbc68d732463e9afb2373c9bd47e5ee0864","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/blorp: Only copy clear color when doing a resolve.\n\nWe only need to copy the clear color from the state buffer to the\ninlined surface state when doing a resolve.\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/92eb5bbc68d732463e9afb2373c9bd47e5ee0864"},{"sha":"14260e7c60d936e94905a06e51e4e61c1b37a1e6","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"intel/blorp: Update clear color state buffer during fast clears.\n\nWe always want to update the fast clear color during a fast clear on\ni965. On anv, we are doing that before a resolve, but by adding support\nto blorp, we can do a similar thing and update it during a fast clear\ninstead.\n\nThe goal is to remove some code from anv that does such update, and\ncentralize everything in blorp, hopefully removing a lot of code\nduplication. It also allows us to have a similar behavior on gen < 9 and\ngen >= 10.\n\nv5: s/we/we are/ (Jordan)\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/14260e7c60d936e94905a06e51e4e61c1b37a1e6"},{"sha":"ab633c2d6108afc55c7c9f5436296832bdb18492","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"i965/miptree: Add space to store the clear value in the aux surface.\n\nSimilarly to vulkan where we store the clear value in the aux surface,\nwe can do the same in GL.\n\nv2: Remove unneeded extra function.\nv3: Use clear_value_state_size instead of clear_value_size.\nv4:\n - rename to clear_color_state_size\n - store clear_color_bo and clear_color_offset in the aux buf struct\nv5: Unreference clear color bo (Jordan)\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/ab633c2d6108afc55c7c9f5436296832bdb18492"},{"sha":"8735c86ce08155a6cd07addbc848f148d0bc82a9","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"i965/miptree: Add new clear color BO for winsys aux buffers\n\nAdd an extra BO to store clear color when we receive the aux buffer from\nthe window system. Since we have no control over the aux buffer size in\nthis case, we need the new BO to store only the clear color.\n\nv5:\n - Better subject (Jordan).\n - Drop alignment from brw_bo_alloc().\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/8735c86ce08155a6cd07addbc848f148d0bc82a9"},{"sha":"5449f942f20e7bd9379219532b3f7a29a55c0d55","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"i965: Add aux_buf variable to simplify code.\n\nIn a follow up patch, we make use of clear_color_bo, which is in\nmt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the\nsame thing on both aux buffers, just use aux_buf already.\n\nv5: Add aux_buf to brw_wm_surface_state too.\nv6: Drop aux_surf and use aux_buf->surf instead (Jason).\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/5449f942f20e7bd9379219532b3f7a29a55c0d55"},{"sha":"2efe8309d3dd44eb37dcf887f49fb3ce14746df8","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"i965/blorp: Update the fast clear value buffer.\n\nOn Gen10, whenever we do a fast clear, blorp will update the clear color\nstate buffer for us, as long as we set the clear color address\ncorrectly.\n\nHowever, on a hiz clear, if the surface is already on the fast clear\nstate we skip the actual fast clear operation and, before gen10, only\nupdated the miptree. On gen10+ we need to update the clear value state\nbuffer too, since blorp will not be doing a fast clear and updating it\nfor us.\n\nv4:\n - do not use clear_value_size in the for loop\n - Get the address of the clear color from the aux buffer or the\n clear_color_bo, depending on which one is available.\n - let core blorp update the clear color, but also update it when we\n skip a fast clear depth.\n\nv5: Better subject (Jordan).\nv6: Remove outdated comment (Jason).\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/2efe8309d3dd44eb37dcf887f49fb3ce14746df8"},{"sha":"7987d041fda0c98b243e540a46ac3a57a23cad26","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"i965/surface_state: Emit the clear color address instead of value.\n\nOn Gen10, when emitting the surface state, use the value stored in the\nclear color entry buffer by using a clear color address in the surface\nstate.\n\nv4: Use the clear color offset from the clear_color_bo, when available.\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/7987d041fda0c98b243e540a46ac3a57a23cad26"},{"sha":"3f96b459f425d05dfb1c809b2b9c2f66f8763743","author":{"name":"Rafael Antognolli","email":"23baadb5a81be7cd65c37490e682e3faa5f22835@intel.com"},"message":"anv: Add a helper to extract clear color from the attachment.\n\nExtract the code from color_attachment_compute_aux_usage, so we can\nlater reuse it to update the clear color state buffer.\n\nSigned-off-by: Rafael Antognolli <rafael.antognolli@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":true,"url":"https://api.github.com/repos/rantogno/mesa/commits/3f96b459f425d05dfb1c809b2b9c2f66f8763743"}]}
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