{"push_id":2593361546,"size":1000,"distinct_size":1989,"ref":"refs/heads/master","head":"8c15b1c473735b61f3c4487c4b553bdb01469750","before":"44fdd91af0473a4e6ea907d24ca2711863642493","commits":[{"sha":"f3a5c86e78138b8cb7c2869e211e7b16e22debb1","author":{"name":"Vedant Kumar","email":"004c457a2ebaecf18123fd2614baa1d571fe5234@apple.com"},"message":"[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)\n\nSetting the right SDLoc on a newly-created zextload fixes a line table\nbug which resulted in non-linear stepping behavior.\n\nSeveral backend tests contained CHECK lines which relied on the IROrder\ninherited from the wrong SDLoc. This patch breaks that dependence where\nfeasbile and regenerates test cases where not.\n\nIn some cases, changing a node's IROrder may alter register allocation\nand spill behavior. This can affect performance. I have chosen not to\nprevent this by applying a \"known good\" IROrder to SDLocs, as this may\nhide a more general bug in the scheduler, or cause regressions on other\ntest inputs.\n\nrdar://33755881, Part of: llvm.org/PR37262\n\nDifferential Revision: https://reviews.llvm.org/D45995\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331300 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/f3a5c86e78138b8cb7c2869e211e7b16e22debb1"},{"sha":"fec188eac77babb3d4ebce29093eb60c80e1eb75","author":{"name":"Vedant Kumar","email":"004c457a2ebaecf18123fd2614baa1d571fe5234@apple.com"},"message":"[DAGCombiner] Change the SDLoc on split extloads (2/N)\n\nIn DAGCombiner, we try to simplify this pattern:\n\n  ([s|z]ext (load ...))\n\nConceptually, a new extload which is created while splitting the load\nshould have the same debug location as the load.\n\nMaking this change affects the IROrder of the new load, causing some\ntest case churn.\n\nIn practice, the new location is never different from the location of\nthe [s|z]ext, at least not during check-llvm or a stage2 build.\n\nPart of: llvm.org/PR37262\n\nDifferential Revision: https://reviews.llvm.org/D46156\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331301 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/fec188eac77babb3d4ebce29093eb60c80e1eb75"},{"sha":"cad24a07046c972c33ae9945bb2439b621aa45ca","author":{"name":"Vedant Kumar","email":"004c457a2ebaecf18123fd2614baa1d571fe5234@apple.com"},"message":"[DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)\n\nPrior to this patch, for the given test case, we would apply the\nlocation associated with the sdiv instruction to instructions which\nperform the load.\n\nPart of: llvm.org/PR37262.\n\nDifferential Revision: https://reviews.llvm.org/D46222\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331302 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/cad24a07046c972c33ae9945bb2439b621aa45ca"},{"sha":"1ae0aae5523207826cb7d137c6b9c54de4bc4d30","author":{"name":"Vedant Kumar","email":"004c457a2ebaecf18123fd2614baa1d571fe5234@apple.com"},"message":"[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)\n\nThe logic for this combine is almost identical to the logic for a\n(sext (sextload x)) combine.\n\nThis commit factors out the logic so it can be shared by both combines,\nand corrects the SDLoc assigned in the zext version of the combine.\n\nPrior to this patch, for the given test case, we would apply the\nlocation associated with the udiv instruction to instructions which\nperform the load.\n\nPart of: llvm.org/PR37262\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331303 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/1ae0aae5523207826cb7d137c6b9c54de4bc4d30"},{"sha":"792a593446ed0b42368e6c3b8a4fc80a14eebcca","author":{"name":"Eli Friedman","email":"8e5ee4945af1f17b38864e236876caaaabff2d25@codeaurora.org"},"message":"[AArch64] Add more tests for 64-bit immediate lowering.\n\nThis adds a some more tests, and adds some notes to tests which are using\na suboptimal lowering.\n\nThe constants with suboptimal lowerings seem to be relatively rare in\npractice, but it might be a fun project to work on improvements.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331304 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/792a593446ed0b42368e6c3b8a4fc80a14eebcca"},{"sha":"b5a4cf07e41a6c84ef6fad5b30e1f152cc86a311","author":{"name":"Jessica Paquette","email":"5ec7c8f0b43ec4db30d85351834103e780635c18@apple.com"},"message":"Create a MachineBasicBlock for created IR-level BasicBlock\n\nWhile running the lit tests for the most recent version of D45916\n(https://reviews.llvm.org/D45916), I found that a couple tests for this pass\nsuddenly started segfaulting. Since the outliner wasn't actually doing anything\nto the code in either of these tests I got curious.\n\nI found that the pass doesn’t completely create the machine-level constructs\nnecessary to actually add a MachineFunction and MachineBasicBlock to the\nmodule. This patch adds in those missing bits. After this, adding the\noutliner before this pass won’t cause it to segfault.\n\nYou can recreate this behaviour by adding the MachineOutliner directly before\nthe pass and having it return false immediately.\n\nhttps://reviews.llvm.org/D46330\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331307 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/b5a4cf07e41a6c84ef6fad5b30e1f152cc86a311"},{"sha":"b68ff828994f3b96586ba9a60224cdc32ea9990c","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[PhaseOrdering] add tests for bittest patterns from bitfields; NFC\n\nAs mentioned in D45986, there's a potential ordering dependency \nbetween instcombine and aggressive-instcombine for detecting these,\nso I'm adding a few tests to confirm that the expected folds occur\nusing -O3 (because aggressive-instcombine only runs at -O3 currently).\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331308 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/b68ff828994f3b96586ba9a60224cdc32ea9990c"},{"sha":"bcc7a8e41380a21e3a2cfae66ac454db2f37573e","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[AggressiveInstCombine] add more bitfield test patterns; NFC\n\nAdd another baseline for D45986 and a pattern that won't be\nmatched with that patch.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331309 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/bcc7a8e41380a21e3a2cfae66ac454db2f37573e"},{"sha":"2f7417dcfbdf398767d1c5e3f211e05430485761","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare\n\nand (or (lshr X, C), ...), 1 --> (X & C') != 0\n\nI initially thought about implementing the minimal pattern in instcombine as mentioned here:\nhttps://bugs.llvm.org/show_bug.cgi?id=37098#c6\n\n...but we need to do better to catch the more general sequence from the motivating test \n(more than 2 bits in the compare). And a test-suite run with statistics showed that this \npattern only happened 2 times currently. It would potentially happen more often if \nreassociation worked better (D45842), but it's probably still not too frequent?\n\nThis is small enough that I didn't see a need to create a whole new class/file within \nAggressiveInstCombine. There are likely other relatively small matchers like what was \ndiscussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome). \nWe could potentially also consolidate matchers for ctpop, bswap, etc under here.\n\nDifferential Revision: https://reviews.llvm.org/D45986\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331311 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/2f7417dcfbdf398767d1c5e3f211e05430485761"},{"sha":"090f8159a4427a50add2719b3505a2fd886e3aa2","author":{"name":"David Bolvansky","email":"9a1fedb3c7ae5df4a0c3ebeae3c6559a1f31f556@gmail.com"},"message":"[CFLGraph][NFC] Simplify/reorder switch in visitConstantExpr\n\nReviewers: hfinkel, efriedma, spatel, dsanders, Danil, rjmccall\n\nReviewed By: rjmccall\n\nSubscribers: dberlin, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D46259\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331312 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/090f8159a4427a50add2719b3505a2fd886e3aa2"},{"sha":"20a92cda49ebaf2e054c566cf11a8910e6ad9945","author":{"name":"Farhana Aleen","email":"6f3c4fc3a36a36c78c831ff1ac5f3ce9ef337418@gmail.com"},"message":"[AMDGPU] Support horizontal vectorization.\n\nAuthor: FarhanaAleen\n\nReviewed By: rampitec, arsenm\n\nSubscribers: llvm-commits, AMDGPU\n\nDifferential Revision: https://reviews.llvm.org/D46213\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331313 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/20a92cda49ebaf2e054c566cf11a8910e6ad9945"},{"sha":"ff933fa1afa8817f8e240595c20160a1da9f0c16","author":{"name":"Matt Davis","email":"e8b6b5e72583fddb49d02eaa15be6df846f3440a@sony.com"},"message":"[llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translation unit into its own translation unit. NFC\n\nThe logic remains the same.  Eventually, I see the RCU acting as its own separate stage in the instruction pipeline.\n\nDifferential Revision: https://reviews.llvm.org/D46331\n\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331316 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/ff933fa1afa8817f8e240595c20160a1da9f0c16"},{"sha":"ac135922af3a607633b1e3894d1226ad56fef75c","author":{"name":"Sam Clegg","email":"4504a65e6a180f18042ae97f363f5ae49cc5c461@chromium.org"},"message":"[WebAssembly] Fix debug printing of symbol types\n\nThe Info.Kind field is a uint8_t which the OS was\ntrying to print as an ascii char.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331317 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/ac135922af3a607633b1e3894d1226ad56fef75c"},{"sha":"81352e1cb7abb274ba345342a25aa824a3208c5f","author":{"name":"Sam Clegg","email":"4504a65e6a180f18042ae97f363f5ae49cc5c461@chromium.org"},"message":"Fix release build breakage\n\nThis function was added in rL331220 but wasn't\ntesting in release configurations.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331320 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/81352e1cb7abb274ba345342a25aa824a3208c5f"},{"sha":"f4f861bbdf9be5247430542e8b4b86c28b7eeef5","author":{"name":"Dean Michael Berris","email":"34a37f59e4ade3cf49221306f04217acf3e86255@google.com"},"message":"[XRay][tools] Rename llvm-xray filenames from .cc -> .cpp (NFC)\n\nSummary:\nThis brings the filenames in accordance to the style guide and LLVM\nconventions for C++ filenames.\n\nAs suggested by rnk@ in D46068.\n\nReviewers: rnk\n\nSubscribers: mgorny, mgrang, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D46301\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331321 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/f4f861bbdf9be5247430542e8b4b86c28b7eeef5"},{"sha":"dd5fd467498efc62e277520625bd1d75b1852155","author":{"name":"Bjorn Pettersson","email":"1b71aeb3adabd976d8717519db9db04b7ad59d74@ericsson.com"},"message":"[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)\n\nSummary:\nThis is a follow up to rL331182. A PHI node can be split up into\nseveral MIR PHI nodes when being selected. When there is a\ndbg.value intrinsic that uses the result of such a PHI node we\nneed to select several DBG_VALUE instructions, with fragment\nexpressions, in order to do a correct selection.\n\nReviewers: rnk, aprantl, vsk\n\nReviewed By: vsk\n\nSubscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk\n\nTags: #debug-info\n\nDifferential Revision: https://reviews.llvm.org/D46329\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331337 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/dd5fd467498efc62e277520625bd1d75b1852155"},{"sha":"a5108a08ceab35886a7df07c86f96aedd3d94bb7","author":{"name":"Piotr Padlewski","email":"83a6da1a0f6a5e3ab62b8666cc788eee7a3d8b6f@gmail.com"},"message":"Mark invariant.group.barrier as inaccessiblememonly\n\nIt turned out that readonly argmemonly is not enough.\n\n  store 42, %p\n  %b = barrier(%p)\n  store 43, %b\nthe first store is dead, but because barrier was marked as\nreading argument memory, it was considered alive. With\ninaccessiblememonly it doesn't read the argument, but\nit also can't be CSEd.\n\nbased on: https://reviews.llvm.org/D32006\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331338 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/a5108a08ceab35886a7df07c86f96aedd3d94bb7"},{"sha":"33b9c81ee37a04beee653bcf4e6b636064793446","author":{"name":"Sander de Smalen","email":"cfb2bb6ce14dfe626ffa26d9d86d8d43a3b39961@arm.com"},"message":"[AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.\n\nReviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar\n\nReviewed By: SjoerdMeijer\n\nDifferential Revision: https://reviews.llvm.org/D46250\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331339 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/33b9c81ee37a04beee653bcf4e6b636064793446"},{"sha":"3a58e1f0020baa9814952f06968c8749652625ad","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values\n\nIntel models were targeting x87 instead of packed sse.\n\nAlso fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331340 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/3a58e1f0020baa9814952f06968c8749652625ad"},{"sha":"112e4a35e62d26265811c7b161b76ccf6b2394aa","author":{"name":"Simon Dardis","email":"65660f3f6618d20e92f342c6422290db343c3251@mips.com"},"message":"[mips] Correct the predicates for shifts.\n\nReviewers: smaksimovic, abeserminji, atanasyan\n\nDifferential Revision: https://reviews.llvm.org/D46123\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331341 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/vvlevchenko/llvm/commits/112e4a35e62d26265811c7b161b76ccf6b2394aa"}]}
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