{"push_id":2648444874,"size":32,"distinct_size":31,"ref":"refs/heads/master","head":"498161a504bdeeb21ea0647422ce484c79664e1b","before":"11bebd7cab0873d04ad8f1d3ccd538f4d5b80ccb","commits":[{"sha":"abbffe98ed6a2fff519cc5590b947c9751cdd235","author":{"name":"Isla Mitchell","email":"1194182d6916a8d87dc279e1c7396e99db4d4464@arm.com"},"message":"Add support for Cortex-Ares and Cortex-A76 CPUs\n\nBoth Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit\n(DSU).  The power-down and power-up sequences are therefore mostly\nmanaged in hardware, and required software operations are simple.\n\nChange-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161\nSigned-off-by: Isla Mitchell <isla.mitchell@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/abbffe98ed6a2fff519cc5590b947c9751cdd235"},{"sha":"08268e27ab9dfe41b420f6aae33459adb6cd7f73","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Add AMU support for Cortex-Ares\n\nChange-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/08268e27ab9dfe41b420f6aae33459adb6cd7f73"},{"sha":"040b546e94a2dc3f77bb16c79a5c887de8b80caf","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Implement Cortex-Ares 1043202 erratum workaround\n\nThe workaround uses the instruction patching feature of the Ares cpu.\n\nChange-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/040b546e94a2dc3f77bb16c79a5c887de8b80caf"},{"sha":"ee7cda31c759b39af7487ddd5ab799208f288c03","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default\n\nThe upcoming patch that adds dynamic mitigation for Cortex-A76\nrequires that DYNAMIC_WORKAROUND_CVE_2018_3639=1.  On FVP, we pull in\nall the CPU files into the build which means there will be a build\nfailure if DYNAMIC_WORKAROUND_CVE_2018_3639=0.\n\nChange-Id: I2e781cbeafbf5d16eaabf76a1677e0c9f81269d2\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/ee7cda31c759b39af7487ddd5ab799208f288c03"},{"sha":"d6b798097e23bc98814ced8406f4dc63df4078c5","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76\n\nThe Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in\n\"Firmware interfaces for mitigating cache speculation vulnerabilities\nSystem Software on Arm Systems\"[0].\n\nDynamic mitigation for CVE-2018-3639 is enabled/disabled by\nsetting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`.\n\nNOTE: The generic code that implements dynamic mitigation does not\ncurrently implement the expected semantics when dispatching an SDEI\nevent to a lower EL.  This will be fixed in a separate patch.\n\n[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification\n\nChange-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/d6b798097e23bc98814ced8406f4dc63df4078c5"},{"sha":"6f03bc7753a22485ad2b531a11e96756147facbe","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"SDEI: Ensure SDEI handler executes with CVE-2018-3639 mitigation enabled\n\nWhen dynamic mitigation is used, the SDEI handler is required to\nexecute with the mitigation enabled by default, regardless of the\nmitigation state for lower ELs.  This means that if the kernel or\nhypervisor explicitly disables the mitigation and then later when the\nevent is dispatched, the dispatcher will remember the mitigation state\nfor the lower ELs but force the mitigation to be on during the SDEI\nhandler execution.  When the SDEI handler returns, it will restore the\nmitigation state.\n\nThis behaviour is described in \"Firmware interfaces for mitigating\ncache speculation vulnerabilities System Software on Arm Systems\"[0].\n\n[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification\n\nChange-Id: I8dd60b736be0aa9e832b0f92d67a401fdeb417f4\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/6f03bc7753a22485ad2b531a11e96756147facbe"},{"sha":"608529aa2425a12212ecbda80927aee3621ba11b","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Merge pull request #1397 from dp-arm/dp/cortex-a76\n\nAdd support for Cortex-A76 and Cortex-Ares","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/608529aa2425a12212ecbda80927aee3621ba11b"},{"sha":"bdcd33a858eb14a59128f142376c3735e9df65c9","author":{"name":"John Tsichritzis","email":"c5e6a94b5ed6b01ab911c6a4e005fdf814669fe4@arm.com"},"message":"MISRA rule 21.15 fix\n\n    Rule 21.15: The pointer arguments to the Standard Library functions\n    memcpy, memmove and memcmp shall be pointers to qualified or unqualified\n    versions of compatible types.\n\n    Basically that means that both pointer arguments must be of the same\n    type. However, even if the pointers passed as arguments to the above\n    functions are of the same type, Coverity still thinks it's a violation\n    if we do pointer arithmetics directly at the function call. Thus the\n    pointer arithmetic operations were moved outside of the function\n    argument.\n\n    First detected on the following configuration\n            make PLAT=fvp LOG_LEVEL=50\n\n    Change-Id: I8b912ec1bfa6f2d60857cb1bd453981fd7001b94\n    Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>","distinct":false,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/bdcd33a858eb14a59128f142376c3735e9df65c9"},{"sha":"42be6fc57e4f543a6a5a79f3a3d13192fb346fe2","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Adjust BL2_AT_EL3 memory layout\n\nFor the BL2_AT_EL3 configuration, move BL2 higher up to make more\nspace for BL31.  Adjust the BL31 limit to be up to BL2 base.  This is\nbecause BL2 is always resident for the BL2_AT_EL3 configuration and\nthus we cannot overlay it with BL31.\n\nChange-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa\nSigned-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/42be6fc57e4f543a6a5a79f3a3d13192fb346fe2"},{"sha":"529b541e8b81f68bb6ee3c6ecdb43b5cbe0a9d70","author":{"name":"Benjamin Fair","email":"ca220295824e288dcaece393af5f2ec059779d5d@ti.com"},"message":"drivers: ti: uart: Add TI specific 16550 initialization\n\nOn TI platforms the UART is disabled by default and must be explicitly\nenabled using the MDR1 register.\n\nNOTE: The original definition of\nhttp://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but\nmany TI SoCs implementing 16550 do have a quirky MDR register\nimplemented. So, this should be enabled with TI_16550_MDR_QUIRK\n\nNOTE: In such implementation, the CSR register does not exist.\n\nSigned-off-by: Benjamin Fair <b-fair@ti.com>\nSigned-off-by: Nishanth Menon <nm@ti.com>\nSigned-off-by: Andrew F. Davis <afd@ti.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/529b541e8b81f68bb6ee3c6ecdb43b5cbe0a9d70"},{"sha":"4fc1a38185341fe7860ce2097e4b39535598693c","author":{"name":"Satoshi Ikawa","email":"21196baabac3f154aa62c702030c54beb0965810@socionext.com"},"message":"uniphier: fix CCI-500 connection for LD20\n\nThe slave ports of LD20 CCI-500 are connected as follows:\n\n  S0: CA53\n  S1: CA72\n\nBe careful because the slave interface is not arranged in the\ncluster number order (CA72: cluster 0, CA53: cluster 1).\n\nRoot-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com>\nSigned-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/4fc1a38185341fe7860ce2097e4b39535598693c"},{"sha":"e109b0ffea07c6987cfb9f8668d8a90c246aab34","author":{"name":"Dimitris Papastamos","email":"5172875e934a989df22d22726b6d9d921b91fbdd@arm.com"},"message":"Merge pull request #1391 from jts-arm/misra\n\nMISRA rule 21.15 fix","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/e109b0ffea07c6987cfb9f8668d8a90c246aab34"},{"sha":"87d3aacc88f43ec162ef3983f2261b9c9296fc68","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.1\n\nRule 5.1: External identifiers shall be distinct\n\nSome of the identifier names in the GICv3 driver were so long that the\nfirst 31 characters were identical. This patch shortens these names to\nmake sure they are different.\n\nFixed for:\n    LOG_LEVEL=50 PLAT=fvp\n\nChange-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/87d3aacc88f43ec162ef3983f2261b9c9296fc68"},{"sha":"d3775d46a43a47c521193229cfcb1c0d6cb4878b","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.3 Part 1\n\nConflict with function name and variable name within that function.\nChange the name of the function from image_size to get_image_size\nto remove conflict and make the function fit the normal project\nnaming convention.\n\nRule 5.3:  An identifier declared in an inner scope shall not\n           hide an identifier declared in an outer scope\n\nFixed For:\n    make LOG_LEVEL=50 PLAT=fvp\n\nChange-Id: I1a63d2730113e2741fffa79730459c584b0224d7\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/d3775d46a43a47c521193229cfcb1c0d6cb4878b"},{"sha":"896a5902ecd9f8ffd1ad7cfd75ea646351c79fc1","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.3 Part 2\n\nUse a _ prefix for Macro arguments to prevent that argument from\nhiding variables of the same name in the outer scope\n\nRule 5.3: An identifier declared in an inner scope shall not\n          hide an identifier declared in an outer scope\n\nFixed For:\n    make LOG_LEVEL=50 PLAT=fvp\n\nChange-Id: I67b6b05cbad4aeca65ce52981b4679b340604708\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/896a5902ecd9f8ffd1ad7cfd75ea646351c79fc1"},{"sha":"7c934242e3652c4d43f1ce31187d804f627ab8a9","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.3 Part 3\n\nUse a _ prefix for macro arguments to prevent that argument from\nhiding variables of the same name in the outer scope\n\nRule 5.3: An identifier declared in an inner scope shall not\n          hide an identifier declared in an outer scope\n\nFixed For:\n    make PLAT=fvp SPD=tspd\n\nChange-Id: I2d711b9584c4cb9ba3814ecd2ca65a42b7e24179\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/7c934242e3652c4d43f1ce31187d804f627ab8a9"},{"sha":"7cb81945d5007925c59f68150ede7a20dba41e6c","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.3 Part 4\n\nUse a _ prefix for macro arguments to prevent that argument from\nhiding variables of the same name in the outer scope\n\nRule 5.3: An identifier declared in an inner scope shall not\n          hide an identifier declared in an outer scope\n\nFixed For:\n    make PLAT=fvp USE_COHERENT_MEM=0\n\nChange-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/7cb81945d5007925c59f68150ede7a20dba41e6c"},{"sha":"ff4e86f90e885ccfca1b51a88c23b47130af9292","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.3 Part 5\n\nUse a _ prefix for macro arguments to prevent that argument from\nhiding variables of the same name in the outer scope\n\nRule 5.3: An identifier declared in an inner scope shall not\n          hide an identifier declared in an outer scope\n\nFixed For:\n    make LOG_LEVEL=50 PLAT=juno\n\nChange-Id: I575fbc96e8267f2b075e88def1f6e3185394613a\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/ff4e86f90e885ccfca1b51a88c23b47130af9292"},{"sha":"40692923882928ce52b61bfae1e5507b0076f105","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.7 Part 1\n\nRule 5.7: A tag name shall be a unique identifier\n\nThere were 2 amu_ctx struct type definitions:\n    - In lib/extensions/amu/aarch64/amu.c\n    - In lib/cpus/aarch64/cpuamu.c\n\nRenamed the latter to cpuamu_ctx to avoid this name clash\n\nTo avoid violation of Rule 8.3 also change name of function\namu_ctxs to unique name (cpuamu_ctxs) since it now returns a\ndifferent type (cpuamu_ctx) than the other amu_ctxs function\n\nFixed for:\n    make LOG_LEVEL=50 PLAT=fvp\n\nChange-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/40692923882928ce52b61bfae1e5507b0076f105"},{"sha":"a138f7687159685175ee8f249dbe7ea1c22e90e1","author":{"name":"Daniel Boulby","email":"326dadf32cdcf0f6ec473c2dfe75080bda3b29ff@arm.com"},"message":"Fix MISRA Rule 5.7 Part 2\n\nFollow convention of shorter names for smaller scope to fix\nviolations of MISRA rule 5.7\n\nTo prevent violation of directive 4.5 having variable name channel\nin css_pm_scmi.c not being typographically ambiguous change macro\nargument CHANNEL in css_mhu_doorbell.h change argument to _channel\nto fit with our convention which is a permitted exception of\ndirective 4.5 for this project\n\nRule 5.7: A tag name shall be a unique identifier\n\nFixed for:\n    make LOG_LEVEL=50 PLAT=juno\n\nChange-Id: I147cdb13553e83ed7df19149b282706db115d612\nSigned-off-by: Daniel Boulby <daniel.boulby@arm.com>","distinct":true,"url":"https://api.github.com/repos/jts-arm/arm-trusted-firmware/commits/a138f7687159685175ee8f249dbe7ea1c22e90e1"}]}
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