{"action":"created","issue":{"url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/19","repository_url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs","labels_url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/19/labels{/name}","comments_url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/19/comments","events_url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/19/events","html_url":"https://github.com/LibrePCB/librepcb-rfcs/issues/19","id":333759602,"node_id":"MDU6SXNzdWUzMzM3NTk2MDI=","number":19,"title":"Loading connectivity objects from a library","user":{"login":"ouabache","id":1408476,"node_id":"MDQ6VXNlcjE0MDg0NzY=","avatar_url":"https://avatars3.githubusercontent.com/u/1408476?v=4","gravatar_id":"","url":"https://api.github.com/users/ouabache","html_url":"https://github.com/ouabache","followers_url":"https://api.github.com/users/ouabache/followers","following_url":"https://api.github.com/users/ouabache/following{/other_user}","gists_url":"https://api.github.com/users/ouabache/gists{/gist_id}","starred_url":"https://api.github.com/users/ouabache/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ouabache/subscriptions","organizations_url":"https://api.github.com/users/ouabache/orgs","repos_url":"https://api.github.com/users/ouabache/repos","events_url":"https://api.github.com/users/ouabache/events{/privacy}","received_events_url":"https://api.github.com/users/ouabache/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":8,"created_at":"2018-06-19T17:03:09Z","updated_at":"2018-06-23T08:28:38Z","closed_at":null,"author_association":"NONE","body":"One thing that gEDA's gschem does that we should copy is the ability to define bus rippers in a symbol file and load them into a schematic from a library. The alternative is to synthesize the graphic in the program but that is undesirable because you are hard coding that into your code. This makes it difficult to change without recompiling the code.\r\n\r\nThis should be done for all connectivity objects: Bus rippers,symbol pins,io_ports,junctions etc. This would give the user more control over the look of their schematics and would simplify the tools.\r\n\r\nJohn Eaton"},"comment":{"url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/comments/399652086","html_url":"https://github.com/LibrePCB/librepcb-rfcs/issues/19#issuecomment-399652086","issue_url":"https://api.github.com/repos/LibrePCB/librepcb-rfcs/issues/19","id":399652086,"node_id":"MDEyOklzc3VlQ29tbWVudDM5OTY1MjA4Ng==","user":{"login":"hephaisto","id":1156478,"node_id":"MDQ6VXNlcjExNTY0Nzg=","avatar_url":"https://avatars3.githubusercontent.com/u/1156478?v=4","gravatar_id":"","url":"https://api.github.com/users/hephaisto","html_url":"https://github.com/hephaisto","followers_url":"https://api.github.com/users/hephaisto/followers","following_url":"https://api.github.com/users/hephaisto/following{/other_user}","gists_url":"https://api.github.com/users/hephaisto/gists{/gist_id}","starred_url":"https://api.github.com/users/hephaisto/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/hephaisto/subscriptions","organizations_url":"https://api.github.com/users/hephaisto/orgs","repos_url":"https://api.github.com/users/hephaisto/repos","events_url":"https://api.github.com/users/hephaisto/events{/privacy}","received_events_url":"https://api.github.com/users/hephaisto/received_events","type":"User","site_admin":false},"created_at":"2018-06-23T08:28:38Z","updated_at":"2018-06-23T08:28:38Z","author_association":"NONE","body":"Isn't it normal, that nets with the same name are connected? So if you have a net name `ADDR[2]` whereever you defined the \"bus\" (e.g. at the CPU), having a second net segment with the name `ADDR[2]` (e.g. at a RAM block) should already connect these nets, right? From this perspective, creating a \"bus\" is just a matter of optics and documentation and could be achieved with a simple drawing tool.\r\nI'm not really familiar with the workflow when drawing such connections with a real drawing tool. I usually make all connections between different modules (logical groups) by giving net stubs the same name. This way, by allowing special characters like `[` in net names, this would already be covered by the (hopefully) currently working net handling tools."}}
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