{"push_id":2786568003,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"83ba3784b50162e2232da66ab4b07d8931dffaa6","before":"21e235dbe468bfa80bab86900ab4baeb48533a94","commits":[{"sha":"83ba3784b50162e2232da66ab4b07d8931dffaa6","author":{"name":"Vijay Hiremath","email":"006c712879a3af08bfdb5c2b8491a8b2d5fd73cd@intel.com"},"message":"icelake: Correct POWER_G3S5 exit status\n\nFor Icelake SLP_SUS_L deassertion is the exit state to go to\nPOWER_S5 state hence corrected the logic to wait on SLP_SUS_L\ndeassertion.\n\nBUG=b:111851944, b:111810925\nBRANCH=none\nTEST=ICLRVP & Dragonegg can boot to S0\n\nChange-Id: I65a04a448bb97223589f6d1338249c87ab395f42\nSigned-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>\nReviewed-on: https://chromium-review.googlesource.com/1162661\nCommit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>\nTested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>\nReviewed-by: Scott Collyer <scollyer@chromium.org>\nReviewed-by: Furquan Shaikh <furquan@chromium.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/chrome-ec/commits/83ba3784b50162e2232da66ab4b07d8931dffaa6"}]}
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