{"push_id":2388146920,"size":197,"distinct_size":197,"ref":"refs/heads/master","head":"767ba55eb3b643b8db3c33b7aa4086482afd357a","before":"fce2d38e3979d1b01238c6b7df1b2c56da8569f1","commits":[{"sha":"17209fa8d773b4a5fa6f77146d785dc9f1504e32","author":{"name":"Thomas Preud'homme","email":"be9f09d60035133c9febbd22e5307dcaeff06e22@arm.com"},"message":"Fix location of comment in EmitPopInst\n\nComment about folding return in LDM was not moved along with the\ncorresponding code in r242714. This commit fixes that.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326690 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/17209fa8d773b4a5fa6f77146d785dc9f1504e32"},{"sha":"54767673da12dc9f3a496f6963aa40d1fd26426e","author":{"name":"Nicholas Wilson","email":"d9e8d6302b9e35d512cee284042c12c396baa875@nicholaswilson.me.uk"},"message":"[WebAssembly] Attach a name to globals similarly to function naming\n\nThis allows LLD to print the name for an InputGlobal when encountering\nan error.\n\nDifferential Revision: https://reviews.llvm.org/D44033\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326691 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/54767673da12dc9f3a496f6963aa40d1fd26426e"},{"sha":"a60bc625ceb164e7af49b480d6bea17b9af8cda0","author":{"name":"Nicholas Wilson","email":"d9e8d6302b9e35d512cee284042c12c396baa875@nicholaswilson.me.uk"},"message":"[WebAssembly] Fix tests with invalid yaml (required CODE section missing)\n\nDifferential Revision: https://reviews.llvm.org/D44023\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326692 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/a60bc625ceb164e7af49b480d6bea17b9af8cda0"},{"sha":"022e5fa26f94e30bf52bcd4bfa4c72492ae2f23d","author":{"name":"Nicholas Wilson","email":"d9e8d6302b9e35d512cee284042c12c396baa875@nicholaswilson.me.uk"},"message":"[WebAssembly] Reorder reloc sections to come between symtab and name\n\nThis is required in order to enable relocs to be validated\nas they are read in.\n\nAlso update tests with new section ordering.\n\nDifferential Revision: https://reviews.llvm.org/D43940\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326694 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davide\n\nReviewed By: courbet\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D44029\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326698 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/ec1d1788ce5e1b0b46b91f932912a712b81578a4"},{"sha":"8cb107dbb81490c39d562d4ef7bb22b237779458","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Use DefInit::getDef() instead of the type's getRecord()\n\nThe former simply makes more sense: we want to access the data here in\nthe backend, not information about the type.\n\nMore importantly, removing users of RecordRecTy::getRecord() allows us\nmore freedom to refactor the frontend.\n\nChange-Id: Iee8905fd22cdb9b11c42ca03246c03d8fe4dd77f\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326699 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Since defm's do not have an associated single record,\nsupport for NAME has to be implemented differently here.\n\nOriginal test cases provided by Artem Belevich (tra)\n\nChange-Id: I933b74f328c0ff202e7dc23a35b78f3505760cc9\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D43656\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326700 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/f3b54ef25c07dc55c17f0e266d9b6c0dbb64fd86"},{"sha":"9355e1b38937283d0de561f08467426fc3940036","author":{"name":"Stefan Pintilie","email":"fa68017a9c8502c19ea366891285c8933aa418b9@ca.ibm.com"},"message":"[Power9] Add more missing instructions to the Power 9 scheduler\n\nAdding more instructions using InstRW so that we can move away from ItinRW\nand ultimately have a complete Power 9 scheduler.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326701 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/9355e1b38937283d0de561f08467426fc3940036"},{"sha":"77d8d0a7e72feec7e37fe13a2ef972ea9684b47a","author":{"name":"Alexander Timofeev","email":"bb656de38f94dc452b8764cdbebdede67ead042d@amd.com"},"message":"Pass Divergence Analysis data to Selection DAG to drive divergence\ndependent instruction selection.\n\nDifferential revision: https://reviews.llvm.org/D35267\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326703 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/77d8d0a7e72feec7e37fe13a2ef972ea9684b47a"},{"sha":"efff70ac28ac7e70b13810980c2b3ccaf2687ace","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Introduce an abstract variable resolver interface\n\nSummary:\nThe intention is to allow us to more easily restructure how resolving is\ndone, e.g. resolving multiple variables simultaneously, or using the\nresolving mechanism to implement !foreach.\n\nChange-Id: I4b976b54a32e240ad4f562f7eb86a4d663a20ea8\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D43564\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326704 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/efff70ac28ac7e70b13810980c2b3ccaf2687ace"},{"sha":"d5cc0e077d6d11455390bf894d88d6411cfa64da","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Reimplement !foreach using the resolving mechanism\n\nSummary:\nThis changes the syntax of !foreach so that the first \"parameter\" is\na new syntactic variable: !foreach(x, lst, expr) will define the\nvariable x within the scope of expr, and evaluation of the !foreach\nwill substitute elements of the given list (or dag) for x in expr.\n\nAside from leading to a nicer syntax, this allows more complex\nexpressions where x is deeply nested, or even constant expressions\nin which x does not occur at all.\n\n!foreach is currently not actually used anywhere in trunk, but I\nplan to use it in the AMDGPU backend. If out-of-tree targets are\nusing it, they can adjust to the new syntax very easily.\n\nChange-Id: Ib966694d8ab6542279d6bc358b6f4d767945a805\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits, tpr\n\nDifferential Revision: https://reviews.llvm.org/D43651\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326705 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/d5cc0e077d6d11455390bf894d88d6411cfa64da"},{"sha":"73eed0f1afd6b9135e46b4b4ca4a3fa835df5ebd","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Resolve all template args simultaneously in AddSubClass\n\nSummary:\nUse the new resolver interface more explicitly, and avoid traversing\nall the initializers multiple times.\n\nAdd a test case for a pattern that was broken by an earlier version\nof this change.\n\nAn additional change is that we now remove *all* template arguments\nafter resolving them.\n\nChange-Id: I86c828c8cc84c18b052dfe0f64c0d5cbf3c4e13c\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D43652\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326706 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/73eed0f1afd6b9135e46b4b4ca4a3fa835df5ebd"},{"sha":"83f929b89a99d02d82ff1a8c7c073c8cf847446a","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Resolve all template args simultaneously in AddSubMultiClass\n\nSummary:\nUse the new resolver interface more explicitly, and avoid traversing\nall the initializers multiple times.\n\nChange-Id: Ia4dcc6d42dd8b65e6079d318c6a202f36f320fee\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D43653\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326707 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/83f929b89a99d02d82ff1a8c7c073c8cf847446a"},{"sha":"1e9feb80869ae69697fec236f09452bf64f6ec8c","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"TableGen: Resolve all template args simultaneously in ResolveMulticlassDefARgs\n\nSummary:\nUse the new resolver interface more explicitly, and avoid traversing\nall the initializers multiple times.\n\nChange-Id: I679e86988b309d19f25e6cca8b0b14ea150198a6\n\nReviewers: arsenm, craig.topper, tra, MartinO\n\nSubscribers: wdng, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D43654\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326708 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/ROCm-Developer-Tools/llvm/commits/1e9feb80869ae69697fec236f09452bf64f6ec8c"},{"sha":"0bc0dbe2f149984438b7964e8364589aa0a50af4","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"Fuzzer: remove temporary files after we're done with them.\n\nThese were just copies of the relevant fuzzer binary with (presumably)\nmeaningful suffixes, but accounted for more than 10% of my build\ndirectory (> 8GB). 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