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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * Author: Lech Betlej <lech.betlej@linux.intel.com>\n+ */\n+\n+/**\n+ * \\file platform/cannonlake/include/platform/asm_memory_management.h\n+ * \\brief Macros for power gating memory banks specific for cAVS 1.8\n+ * \\(CannonLake)\n+ * \\author Lech Betlej <lech.betlej@linux.intel.com>\n+ */\n+#ifndef ASM_MEMORY_MANAGEMENT_H\n+#define ASM_MEMORY_MANAGEMENT_H\n+\n+#ifndef ASSEMBLY\n+#warning \"ASSEMBLY macro not defined.\"","path":"src/platform/cannonlake/include/platform/asm_memory_management.h","position":null,"original_position":41,"commit_id":"27e85ec09435c7d5d9682b5e6156c23cd694c73e","original_commit_id":"3bf7506831aaff4651c17d81e703421d35893323","user":{"login":"lbetlej","id":39951716,"node_id":"MDQ6VXNlcjM5OTUxNzE2","avatar_url":"https://avatars1.githubusercontent.com/u/39951716?v=4","gravatar_id":"","url":"https://api.github.com/users/lbetlej","html_url":"https://github.com/lbetlej","followers_url":"https://api.github.com/users/lbetlej/followers","following_url":"https://api.github.com/users/lbetlej/following{/other_user}","gists_url":"https://api.github.com/users/lbetlej/gists{/gist_id}","starred_url":"https://api.github.com/users/lbetlej/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/lbetlej/subscriptions","organizations_url":"https://api.github.com/users/lbetlej/orgs","repos_url":"https://api.github.com/users/lbetlej/repos","events_url":"https://api.github.com/users/lbetlej/events{/privacy}","received_events_url":"https://api.github.com/users/lbetlej/received_events","type":"User","site_admin":false},"body":"Done.","created_at":"2018-11-13T11:04:52Z","updated_at":"2018-11-13T11:04:52Z","html_url":"https://github.com/thesofproject/sof/pull/561#discussion_r232991664","pull_request_url":"https://api.github.com/repos/thesofproject/sof/pulls/561","author_association":"COLLABORATOR","_links":{"self":{"href":"https://api.github.com/repos/thesofproject/sof/pulls/comments/232991664"},"html":{"href":"https://github.com/thesofproject/sof/pull/561#discussion_r232991664"},"pull_request":{"href":"https://api.github.com/repos/thesofproject/sof/pulls/561"}},"in_reply_to_id":232299561},"pull_request":{"url":"https://api.github.com/repos/thesofproject/sof/pulls/561","id":229731151,"node_id":"MDExOlB1bGxSZXF1ZXN0MjI5NzMxMTUx","html_url":"https://github.com/thesofproject/sof/pull/561","diff_url":"https://github.com/thesofproject/sof/pull/561.diff","patch_url":"https://github.com/thesofproject/sof/pull/561.patch","issue_url":"https://api.github.com/repos/thesofproject/sof/issues/561","number":561,"state":"open","locked":false,"title":"Added SRAM power gating on D3 entry for cAVS 1.8 (i.e. Cannonlake).","user":{"login":"lbetlej","id":39951716,"node_id":"MDQ6VXNlcjM5OTUxNzE2","avatar_url":"https://avatars1.githubusercontent.com/u/39951716?v=4","gravatar_id":"","url":"https://api.github.com/users/lbetlej","html_url":"https://github.com/lbetlej","followers_url":"https://api.github.com/users/lbetlej/followers","following_url":"https://api.github.com/users/lbetlej/following{/other_user}","gists_url":"https://api.github.com/users/lbetlej/gists{/gist_id}","starred_url":"https://api.github.com/users/lbetlej/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/lbetlej/subscriptions","organizations_url":"https://api.github.com/users/lbetlej/orgs","repos_url":"https://api.github.com/users/lbetlej/repos","events_url":"https://api.github.com/users/lbetlej/events{/privacy}","received_events_url":"https://api.github.com/users/lbetlej/received_events","type":"User","site_admin":false},"body":"On D3 entry FW needs to power gate both LP & HP SRAM banks. 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