{"push_id":3127708542,"size":83,"distinct_size":2,"ref":"refs/heads/ti-rt-linux-4.19.y","head":"ec5d0da86044064e79db54ac0344da2a4c86fe7a","before":"46e36e8471c74d2b5c77eeadb9db71cca53410ac","commits":[{"sha":"6a2e5d16dfbc8ff60697c8195d60d8731cc63f55","author":{"name":"Sekhar Nori","email":"946cfb81282bb55c59f600e7ee3d3b2c6973f7a3@ti.com"},"message":"ti_config_fragments: add connectivity.cfg\n\nIntroduce connectivity.cfg. This is a forward port of latest\nfile from v4.14 kernel, with following configs dropped because\nthey are not recognized Kconfig symbols (yet) in v4.19 kernel.\n\nNET_CADENCE\nNET_VENDOR_EXAR\nPCI_KEYSTONE_EP\nPHY_TI_KEYSTONE_SERDES\nPHY_AM654\nNF_CONNTRACK_IPV4\nTI_PRUETH\nTI_ICSSG_PRUETH\nTI_AM65_CPSW_NUSS\nTI_AM65_CPTS\nPHY_AM654_MMC\n\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/6a2e5d16dfbc8ff60697c8195d60d8731cc63f55"},{"sha":"3f37946fe240af2ceff5161ab256a586afe7a73c","author":{"name":"Sekhar Nori","email":"946cfb81282bb55c59f600e7ee3d3b2c6973f7a3@ti.com"},"message":"ti_config_fragments/defconfig_map.txt: add connectivity.cfg\n\nAdd support for connectivity peripheral related config fragments.\n\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/3f37946fe240af2ceff5161ab256a586afe7a73c"},{"sha":"d4a38cd69c818c98b3ef6d864260bfc9d91ce720","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"HACK: soc: ti: k3: add dma descriptors pool\n\nAdd support for creating and maintaining a pool of DMA\ndescriptors. Such pools are used by networking drivers\nfor performance reasons.\n\nConsists of following squashed commits from previous\nkernels:\nk3: navss: add dma descs pool (initial)\nsoc: ti: k3: desc-pool: switch to SPDX Licensing\nsoc: ti: k3: dma_desc pool change k3_knav_pool_avail() to return num items\nsoc: ti: k3-navss-desc-pool: GPL export global functions\nk3: k3-navss-desc-pool: allow calling k3_knav_pool_create_name() more than once\n\nTODO:\nThis may not be upstream-able in current state. A more generic\nsolution or different way of achieving the same result has\nto be looked at.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Roger Quadros <rogerq@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/d4a38cd69c818c98b3ef6d864260bfc9d91ce720"},{"sha":"85a6f5fcaeca8d63aa0e10d667f11eb3804f0af8","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: ale: add support for mac-only mode\n\nNew CPSW ALE version, available on K3 AM654 SoCs family, allows to switch\nany external port to MAC only mode. When MAC only mode enabled this port be\ntreated like a MAC port for the host. All traffic received is only sent to\nthe host. The host must direct traffic to this port as the lookup engine\nwill not send traffic to the ports with the p0_maconly bit set and the\np0_no_learn also set. If p0_maconly bit is set and the p0_no_learn is not\nset, the host can send non-directed packets that can be sent to the\ndestination of a MacOnly port. It is also possible that The host can\nbroadcast to all ports including MacOnly ports in this mode.\n\nThis patch add ALE supprt for MAC only mode.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/85a6f5fcaeca8d63aa0e10d667f11eb3804f0af8"},{"sha":"811259c0d489ea232e88babb70a8702e937a6e86","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: cpsw: introduce mac sl module api\n\nMAC SL submodule has a lot of common functions between many of TI SoCs\nam335x/am437x/dra7(am57), Keystone 2 66ak2hk/e/l/g and K# AM654, but there\nalso differences especially in registers offsets and sets of supported\nfunctions.\n\nThis patch introduces MAC SL submodule API which is intended to provide\ncommon way to access MAC SL submodule and hide HW integrations details.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/811259c0d489ea232e88babb70a8702e937a6e86"},{"sha":"45af06abf676ec2b4b18b85e9f0543b62238d909","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: cpsw-phy-sel: add am654 support\n\nTI AM654 SoC contains two-port Gigabit Ethernet Switch (CPSW NUSS)\nsubsystem which require to select external Port MII interface type. This\npatch introduces support for AM654 CPSW NUSS external Port mode selection\nin cpsw-phy-sel driver.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/45af06abf676ec2b4b18b85e9f0543b62238d909"},{"sha":"b43c44262c82460e343d2ec2fa87c80eaa0486b7","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: davinci_mdio: allow init without creating pdev\n\nWhen Davinci MDIO module is integrated as part of Gigabit Ethernet Switch\n(CPSW) subsystem it shares common MMIO space, clocks and PM with CPSW, so\nit make no sense to create separate Platform device for it - instead MDIO\nbus can be created and registered directly by CPSW driver. Hence, add\npossibility to register Davinci MDIO bus directly by parent CPSW driver.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b43c44262c82460e343d2ec2fa87c80eaa0486b7"},{"sha":"eaed0d100c239af88c0d7d36354836ef1ef9376e","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"dt-binding: ti: am654: document common platform time sync cpts module\n\nDocument device tree bindings for TI AM654 SoC The Common Platform Time\nSync (CPTS) module. The CPTS module is used to facilitate host control of\ntime sync operations. Main features of CPTS module are:\n  - Supports the selection of multiple external clock sources\n  - Software control of time sync events via interrupt or polling\n  - Supports hardware timestamp push inputs (HWx_TS_PUSH)\n  - Supports timestamp counter compare output (TS_COMP)\n  - Supports timestamp counter bit output (TS_SYNC)\n  - Supports timestamp Generator function outputs (TS_GENFx)\n  - Supports 64-bit timestamp mode in ns with ppm and nudge adjustment.\n  - Depending on integration it enables compliance with the IEEE 1588-2008\nstandard for a precision clock synchronization protocol, Ethernet Enhanced\nScheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time\nMeasurement (PTM).\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/eaed0d100c239af88c0d7d36354836ef1ef9376e"},{"sha":"b533ab155cc81a934767a7ec428209e40893a47c","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: introduce am654 common platform time sync driver\n\nThe CPTS module is used to facilitate host control of time sync operations.\nMain features of CPTS module are:\n- Supports the selection of multiple external clock sources\n- Software control of time sync events via interrupt or polling\n- Supports hardware timestamp push inputs (HWx_TS_PUSH)\n- Supports timestamp counter compare output (TS_COMP)\n- Supports timestamp counter bit output (TS_SYNC)\n- Supports timestamp Generator function outputs (TS_GENFx)\n- Supports 64-bit timestamp mode in ns with ppm and nudge adjustment.\nDepending on integration it enables compliance with the IEEE 1588-2008\nstandard for a precision clock synchronization protocol, Ethernet Enhanced\nScheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time\nMeasurement (PTM).\n\nIntroduced driver provides Linux PTP hardware clock for each CPTS device\nand network packets timestamping where applicable. CPTS PTP hardware clock\nsupports following operations:\n    - Set time\n    - Get time\n    - Shift the clock by a given offset atomically\n    - Adjust clock frequency\n    - Time stamp external events\n    - Periodic output signals\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b533ab155cc81a934767a7ec428209e40893a47c"},{"sha":"0cddea256aa6904e114357f44a0e650781a80741","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"dt-binding: ti: am654: document mcu cpsw nuss\n\nDocument device tree bindings for TI AM654 SoC Gigabit Ethernet two ports\nSwitch subsystem (CPSW NUSS). The CPSW NUSS provides Ethernet packet\ncommunication for the device and can be configured as an Ethernet switch.\nCPSW NUSS features: the Reduced Gigabit Media Independent Interface\n(RGMII), Reduced Media Independent Interface (RMII), and the Management\nData Input/Output (MDIO) interface for physical layer device (PHY)\nmanagement.\n\nThe TI am654 SoC has integrated two-port Gigabit Ethernet Switch subsystem\ninto device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with\nselectable RGMII and RMII interfaces and an internal Communications Port\nProgramming Interface (CPPI) port (Host port 0).\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/0cddea256aa6904e114357f44a0e650781a80741"},{"sha":"1436aedea0d28fc33bf2e9468c3f0f7561d4a404","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"net: ethernet: ti: introduce am654 gigabit eth switch subsystem driver\n\nThe TI am654 SoC Gigabit Ethernet Switch subsystem (CPSW NUSS) has two\nports and provides Ethernet packet communication for the device and can be\nconfigured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit\nMedia Independent Interface (RGMII), Reduced Media Independent Interface\n(RMII), and the Management Data Input/Output (MDIO) interface for physical\nlayer device (PHY) management.\nThe TI am654 SoC has integrated two-port Gigabit Ethernet Switch subsystem\ninto device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with\nselectable RGMII and RMII interfaces and an internal Communications Port\nProgramming Interface (CPPI) port (Host port 0).\n\nHost Port 0 CPPI Packet Streaming Interface interface supports 8 TX\nchannels and on RX channels operating by TI am654 NAVSS Unified DMA\nPeripheral Root Complex (UDMA-P) controller.\n\nIntroduced driver provides one linux net_device to user space and supports:\n - ifconfig up/down\n - MAC address configuration\n - ethtool operation:\n   --driver\n   --change\n   --register-dump\n   --negotiate phy\n   --statistics\n   --set-eee phy\n   --show-ring\n   --show-channels\n - net_device ioctl mii-control\n - promisc mode\n - Common Platform Time Sync (CPTS) module support:\n    -- support for SIOCSHWTSTAMP/SIOCGHWTSTAMP net_device ioctls\n    --  RX : timestamps all received packets (HWTSTAMP_FILTER_ALL)\n    -- TX : timestamps only PTP packets\n    -- PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp\n    -- IEEE 1588 Annex D, Annex E and Annex F\n    -- Add ethtool .get_ts_info()\n\n - rx checksum offload support\n   CPSW NUSS can verify IPv4/IPv6 TCP/UDP packets checksum and fills\n   csum information for each packet in psdata[2] word:\n   - BIT(16) CHECKSUM_ERROR - indicates csum error\n   - BIT(17) FRAGMENT -  indicates fragmented packet\n   - BIT(18) TCP_UDP_N -  Indicates TCP packet was detected\n   - BIT(19) IPV6_VALID,  BIT(20) IPV4_VALID - indicates IPv6/IPv4 packet\n   - BIT(15, 0) CHECKSUM_ADD - This is the value that was summed\n   during the checksum computation. This value is FFFFh for non fragmented\n   IPV4/6 UDP/TCP packets with no checksum error.\n\n   The CPSW NUSS driver will pass csum info to upper layer as below:\n   if (ipv4_valid || ipv6_valid) && fragment) then\n\tskb->ip_summed = CHECKSUM_COMPLETE\n\tskb->csum = CHECKSUM_ADD\n   if (ipv4_valid || ipv6_valid) && not fragment) then\n\tskb->ip_summed = CHECKSUM_UNNECESSARY\n   if (ipv4_valid || ipv6_valid) && checksum_error) then\n\tskb->ip_summed = CHECKSUM_NONE\n   else\n\tskb->ip_summed = CHECKSUM_NONE\n\n   RX csum offload can be disabled:\n\t ethtool -K <dev> rx-checksum on|off\n\n - tx checksum offload support (disabled by default due to am65x HW bug)\n   AM65x CPSW NUSS can calculate TX packets checksum and write csum value\nin specified location in the packet. How HW should calculate csum\ndetermined in CPPI5 psdata[2] word for each packet:\n\t- BITS 31-24 CHECKSUM_RESULT: This is the packet byte number where\nthe checksum result will be placed in the egress packet.\n\t- BITS 23-16 CHECKSUM_START_BYTE: This is the packet byte number to\nstart the checksum calculation on.\n\t- BIT 15 CHECKSUM_INV - When set, a zero checksum value will be\ninverted and sent as FFFFh.\n\t- BITS 13-0 CHECKSUM_BYTECOUNT: This is the number of bytes to\ncalculate the checksum on. The outgoing Ethernet packet will have a\nchecksum inserted when this value is non-zero. The bit 0 RX_CHECKSUM_EN has\nto be set in P0_CONTROL_REG to enable TX csum offload.\n\tTX csum HW offload  can be enabled/disabled:\n\t ethtool -K <dev> tx-checksum-ip-generic on|off\n\n - multiq and switch between round robin/prio modes for cppi tx queues\n   By default Linux network stack does not assume the multiqueue network\ndevice works in fixed priority mode. As result, it will try to dispatch\npackets between HW queues fairly - basing on skb hash (and XPS map if\nenabled). So, by default, MCU CPSW TX statistic looks like below:\n\n     tx_pri0: 14\n     tx_pri1: 2\n     tx_pri2: 0\n     tx_pri3: 12\n     tx_pri4: 12\n     tx_pri5: 0\n     tx_pri6: 306127\n     tx_pri7: 0\n\n   From another side, MCU CPSW HW processes TX queues in fixed priority mode\n(7 - high prio) and this is does not corresponds to what Linux network\nstack expects as some packets might be delayed, MCU CPSW CPPI interface set\nto Round Robin mode (CPPI_P0_Pri_Ctl.p0_rx_ptype) by default.\n   Fixed priority can be used with multiq, prio and mqprio qdisc's.\n   Netdev private flag \"p0-rx-ptype-rrobin\" can be used to switch between\nRound Robin and Fixed priority modes:\n\t # ethtool --show-priv-flags eth0\n\t Private flags for eth0:\n\t p0-rx-ptype-rrobin: on\n\t # ethtool --set-priv-flags eth0 p0-rx-ptype-rrobin off\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/1436aedea0d28fc33bf2e9468c3f0f7561d4a404"},{"sha":"76b15b19d82ad773c25ca6a3a6cbbe1b9aa87c08","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"arm64: dts: k3-am6: add mcu system control module node\n\nMCU System control module support is added to the device tree to allow\ndrivers to access to their System control module registers.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/76b15b19d82ad773c25ca6a3a6cbbe1b9aa87c08"},{"sha":"3645087c025844e3fee1b5a8cc9fc4c614446b1b","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"arm64: dts: ti: k3-am6: add mcu cpsw nuss node\n\nAdd DT node for The TI am654 SoC Gigabit Ethernet two ports Switch\nsubsystem (CPSW NUSS).\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/3645087c025844e3fee1b5a8cc9fc4c614446b1b"},{"sha":"8aec71b77716580295c779549d0f718ac5ec6e6e","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs\n\nAM654 EVM base board has TI DP83867 PHY connected to external CPSW NUSS\nPort 1 in rgmii mode.\n\nHence, add pinmux and Ethernet PHY configuration for TI am654 SoC Gigabit\nEthernet two ports Switch subsystem (CPSW NUSS).\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/8aec71b77716580295c779549d0f718ac5ec6e6e"},{"sha":"7421560cb99fc6d3a511e2ad685792dd83cec6f7","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"ti_config_fragments/connectivity.cfg: enable mcu cpsw/cpts drivers\n\nEnable CPSW/CPTS NUSS driver.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/7421560cb99fc6d3a511e2ad685792dd83cec6f7"},{"sha":"c09d2d7d38b6f8395d8ffd69c4f30c1695e0ea14","author":{"name":"Grygorii Strashko","email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com"},"message":"arm64: dts: ti: AM654: add main navss cpts node\n\nAdd DT node for Main NAVSS CPTS module.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/c09d2d7d38b6f8395d8ffd69c4f30c1695e0ea14"},{"sha":"855f9a5890f909e4e55a712cc4b722139cff1ebd","author":{"name":"Sekhar Nori","email":"946cfb81282bb55c59f600e7ee3d3b2c6973f7a3@ti.com"},"message":"ti_config_fragments/v8_defconfig_map.txt: add connectivity.cfg\n\nAdd support for connectivity fragments on TI's ARMv8\nplatforms.\n\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/855f9a5890f909e4e55a712cc4b722139cff1ebd"},{"sha":"7b02ea87c4334e0137a0ecd2d610242d36acb48c","author":{"name":"LCPD Auto Merger","email":"e3b35f83d72b7ba6fb4ff25d26b632317d5f12dc@list.ti.com"},"message":"Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y\n\nTI-Feature: connectivity\nTI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git\nTI-Branch: connectivity-ti-linux-4.19.y\n\n* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:\n  ti_config_fragments/v8_defconfig_map.txt: add connectivity.cfg\n  arm64: dts: ti: AM654: add main navss cpts node\n  ti_config_fragments/connectivity.cfg: enable mcu cpsw/cpts drivers\n  arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs\n  arm64: dts: ti: k3-am6: add mcu cpsw nuss node\n  arm64: dts: k3-am6: add mcu system control module node\n  net: ethernet: ti: introduce am654 gigabit eth switch subsystem driver\n  dt-binding: ti: am654: document mcu cpsw nuss\n  net: ethernet: ti: introduce am654 common platform time sync driver\n  dt-binding: ti: am654: document common platform time sync cpts module\n  net: ethernet: ti: davinci_mdio: allow init without creating pdev\n  net: ethernet: ti: cpsw-phy-sel: add am654 support\n  net: ethernet: ti: cpsw: introduce mac sl module api\n  net: ethernet: ti: ale: add support for mac-only mode\n  HACK: soc: ti: k3: add dma descriptors pool\n  ti_config_fragments/defconfig_map.txt: add connectivity.cfg\n  ti_config_fragments: add connectivity.cfg\n\nSigned-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/7b02ea87c4334e0137a0ecd2d610242d36acb48c"},{"sha":"8f8289393b32feb9efd990ed5854e2df58cdce84","author":{"name":"LCPD Auto Merger","email":"e3b35f83d72b7ba6fb4ff25d26b632317d5f12dc@list.ti.com"},"message":"Merge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-rt-linux-4.19.y\n\nTI-Feature: ti_linux_base_rt\nTI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git\nTI-Branch: ti-linux-4.19.y\n\n* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:\n  ti_config_fragments/v8_defconfig_map.txt: add connectivity.cfg\n  arm64: dts: ti: AM654: add main navss cpts node\n  ti_config_fragments/connectivity.cfg: enable mcu cpsw/cpts drivers\n  arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs\n  arm64: dts: ti: k3-am6: add mcu cpsw nuss node\n  arm64: dts: k3-am6: add mcu system control module node\n  net: ethernet: ti: introduce am654 gigabit eth switch subsystem driver\n  dt-binding: ti: am654: document mcu cpsw nuss\n  net: ethernet: ti: introduce am654 common platform time sync driver\n  dt-binding: ti: am654: document common platform time sync cpts module\n  net: ethernet: ti: davinci_mdio: allow init without creating pdev\n  net: ethernet: ti: cpsw-phy-sel: add am654 support\n  net: ethernet: ti: cpsw: introduce mac sl module api\n  net: ethernet: ti: ale: add support for mac-only mode\n  HACK: soc: ti: k3: add dma descriptors pool\n  ti_config_fragments/defconfig_map.txt: add connectivity.cfg\n  ti_config_fragments: add connectivity.cfg\n\nSigned-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/8f8289393b32feb9efd990ed5854e2df58cdce84"},{"sha":"cd3870c91c5d5b63d341a862b9e18c5e7ca08301","author":{"name":"Peter Ujfalusi","email":"e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com"},"message":"ASoC: davinci-mcasp: Add support for FIFO usage caused delay reporting\n\ncommit 5fcb457ac2fdc62c5ff6d3962c958b1301bc5ea1 upstream.\n\nMcASP have write and read FIFO, each 64 words deep.\n\nFrom the WFIFOS/RFIFOS registers we can read the amount of data currently\nin the FIFO which can be directly reported as delay.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/cd3870c91c5d5b63d341a862b9e18c5e7ca08301"}]}
{"actor":{"display_login":"RobertCNelson"}}