{"push_id":2705914983,"size":88,"distinct_size":12,"ref":"refs/heads/signal_minimal_windows_v3","head":"493fd3e15ec7e0057e05b4f4cad0d22ab026fad6","before":"13ebd0a3fa629a91d11731c9a244cdf7d079669b","commits":[{"sha":"57ff152c6dead464d012d1f92e8b2440be85dd9d","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Create unit tests for TR_SingleBitContainer\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/57ff152c6dead464d012d1f92e8b2440be85dd9d"},{"sha":"0dfb4e6b9a934440f774bc236da92735aad64318","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Update README to include community links\n\nAdd a section describing ways contributors can interact with the\nEclipse OMR community.\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/0dfb4e6b9a934440f774bc236da92735aad64318"},{"sha":"fa3789e639a9641e232dbe0e8f9e557bff658a30","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Misc. VMThread reclamation cleanup\n\nRemove miscellaneous code left dead from recent VMThread reclamation\nrefactoring.\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/fa3789e639a9641e232dbe0e8f9e557bff658a30"},{"sha":"993da67ca342e8fc5fcb9ed23b49d0520fc41f72","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Remove VMThread reclamation parameter from generateLabelInstruction\n\nChange the APIs to generateLabelInstruction to avoid the deprecated\nVMThread parameter.\n\nTwo APIs were left that accept a VMThread parameter that simply map\nto a non-VMThread accepting equivalent until downstream projects\ncan be refactored.\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/993da67ca342e8fc5fcb9ed23b49d0520fc41f72"},{"sha":"c7359385bd853a68fd960ead5a75fdb7bd1e6908","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Misc. Machine class cleanup\n\n* remove deprecated colouring global register allocator functionality\n* remove unused cache of register numbers by kind and modify\n  architecture constructors\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/c7359385bd853a68fd960ead5a75fdb7bd1e6908"},{"sha":"3e10d7ad9f0e54493c445e23cd4b4a7851500b73","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Initial version of OMRInstruction files\n\nThis commit implements the initial version of OMRInstruction files\nfor aarch64.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/3e10d7ad9f0e54493c445e23cd4b4a7851500b73"},{"sha":"abb34bc4ef50b03ce6a92dda2ad2763d6537e316","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Remove deprecated restricted register support from Z\n\nSigned-off-by: Daryl Maier <maier@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/abb34bc4ef50b03ce6a92dda2ad2763d6537e316"},{"sha":"701ec813603e0653237f1e089ec16e07175184ef","author":{"name":"Liqun Liu","email":"b265cbee828723647d102c4fd6760c85f56fd9f9@ca.ibm.com"},"message":"Use the right way to check if an argument has fixed type\n\nWe should ask `classIsFixed()` on the argument to check if it has fixed class constraint.\n\nSigned-off-by: Liqun Liu <liqunl@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/701ec813603e0653237f1e089ec16e07175184ef"},{"sha":"3eeeffe234fd1fe1e954d269a8714f3373358b5c","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add a data structure to store signal handler info [win64amd]\n\nWe want to restore the signal handlers after the OMR port library\nshutdowns. So, we need to cache the original signal handler.\n\nhandlerInfo is added to store {originalHandler, restore} for every\nsignal on win64amd. restore will be set to 1 after the original signal\nhandler is cached.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/3eeeffe234fd1fe1e954d269a8714f3373358b5c"},{"sha":"02c649cb2498b833fc464c060a135e59f0035095","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add registerSignalHandlerWithOS [win64amd]\n\nregisterSignalHandlerWithOS registers the signal handler with the OS on\nwin64amd platform. Also, it caches the original signal handler.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/02c649cb2498b833fc464c060a135e59f0035095"},{"sha":"92c7af1a28fe18b6364b318da54873f6edc769dd","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add registerHandlerMonitor [win64amd]\n\nAdded registerHandlerMonitor to synchronize calls to\nregisterSignalHandlerWithOS.\n\ninitializeSignalTools updated to initialize registerHandlerMonitor, and\ndestroySignalTools updated to free registerHandlerMonitor.\n\nIn initializeSignalTools, asyncMonitor and masterExceptionMonitor were\ninitialized using the same name, portLibrary_omrsig_async_monitor. Added\na change to initialize masterExceptionMonitor using the name,\nportLibrary_omrsig_master_exception_monitor.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/92c7af1a28fe18b6364b318da54873f6edc769dd"},{"sha":"2bf4aa9bfd717afdf5a52c8450a476242af8e72a","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add implementation of omrsig_register_os_handler [win64amd]\t\n\nomrsig_register_os_handler registers a signal handler with the OS.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/2bf4aa9bfd717afdf5a52c8450a476242af8e72a"},{"sha":"ce95791ecbaff566439e91c13f2e643c2bd8b08c","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add wakeUpASyncReporter semaphore [win64amd]\n\nwakeUpASyncReporter semaphore will coordinate between master async\nsignal handler and async signal reporter thread.\n\ninitializeSignalTools updated to initialize wakeUpASyncReporter, and\ndestroySignalTools updated to free wakeUpASyncReporter.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/ce95791ecbaff566439e91c13f2e643c2bd8b08c"},{"sha":"34622126f8f033f2859e9373bf83c93bf5a41238","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add signalCounts [win64amd]\n\nsignalCounts will keep track of unprocessed signals.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/34622126f8f033f2859e9373bf83c93bf5a41238"},{"sha":"81e3d5af4f1acf774b142699392fe191d5568e5e","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add masterASynchSignalHandler [win64amd]\n\nmasterASynchSignalHandler updates signalCounts after a signal is\nreceived, and re-registers masterASynchSignalHandler.\n\nupdateSignalCount is added to update signal counts. Currently, it is\nonly invoked from masterASynchSignalHandler. In the future, it will be\ncalled from consoleCtrlHandler.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/81e3d5af4f1acf774b142699392fe191d5568e5e"},{"sha":"2eee5d9561e79afcd5a0431ae2dafb6695a4fb3b","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add implementation of omrsig_is_master_signal_handler [win64amd]\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/2eee5d9561e79afcd5a0431ae2dafb6695a4fb3b"},{"sha":"d6ef54543b426f774e284f7aec52bbed3ca70c80","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Initialize and clean handlerInfo [win64amd]\n\nIn omrsig_startup, handlerInfo[osSignalNo].restore is initialized to 0.\n\nIn sig_full_shutdown, handlerInfo[osSignalNo].originalHandler is\nregistered with the OS, and handlerInfo[osSignalNo].restore is reset to\n0.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/d6ef54543b426f774e284f7aec52bbed3ca70c80"},{"sha":"6d696d31014f82360285c6ba560142e2ae41533b","author":{"name":"Babneet Singh","email":"8abd1ff3f747df23e2285ffa6b8768f665774ab2@ca.ibm.com"},"message":"Add removeAsyncHandlers [win64amd]\n\nremoveAsyncHandlers removes the elements in asyncHandlerList, and frees\nthe associated memory.\n\nremoveAsyncHandlers is invoked from sig_full_shutdown.\n\nSigned-off-by: Babneet Singh <sbabneet@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/6d696d31014f82360285c6ba560142e2ae41533b"},{"sha":"48845564f042a37363aa06505cd60b4297bfefa9","author":{"name":"Aleksandar Micic","email":"298dda9593d6eb8fc6f51007550c14e933a91a98@ca.ibm.com"},"message":"Implicit master for CS STW\n\nStop-the-World Concurrent Scavenger phases of a cycle will now use\nimplicit master thread (mutator thread that triggered the phase through\nAllocation Failure).\n\nMasterGCThread class is modified to now support both implicit and\nexplicit master GC thread for STW phases. The later (for now) is still\nused for Balanced GC (in OpenJ9).\n\nAnother optional behavior is whether to acquire or not VM access during\nconcurrent phase. The default is not to (again, still used by Balanced\nGC, during concurrent marking), while CS acquires it (it must because it\nmoves objects).\n\nThe benefit of having implicit master is simpler start/end of a STW\nincrement, since there is no need for use of assume/relinquish exclusive\naccess API, which in various ways complicates some corner cases of VM\naccess synchornization (like hand-off or simultanious safe-access and\nexclusive VM access ) with also complex GC scenarios (where two\ndifferent STW increments/cycle are executed back to back, like percolate\nGC).\n\nAnother changes (and simplification) is that the transition from first\nSTW phase and concurrent phase of a CS cycle will not have the deferred\nVM access 'protocol'. Simply, at the end of STW, exclusive VM access\nwill be released completely (including master GC thread releasing VM\naccess, instead of deferring the release). Then master GC thread will\nsimply acquire VM access prior to starting the concurrent phase. No\nspecial tricks or APIs are used. Master GC thread will continue to keep\nVM access during the whole concurrent phase, although in future for\nfairness, it may occassionally try to release it even before finishing\nthe phase. So, there is now a gap between first STW and concurrent\nphase, where master GC holds neither exclussive VM access nor thread VM\naccess, and other parties are ok to acquire exclusive VM access (or\nsafeAccess) at that time (for example to walk heap and replace classes).\nThe same gap also exists (used to exist even before), between the end of\nthe concurrent phase and start of the second (last) STW phase. \n\nClearly, concurrent phase of CS will continue to use explict master GC\nthread.\n\nAnother change is a fix to a startup scenario, where explicit master\nthread during attach-thread procedure acts as a mutator, and if (rarely)\nhappens during already active concurrent CS phase, the GC specific\nbuffers (like barrier ones) would be populated but never flushed (at the\ntime of flushing the thread would already turn into a GC thread and not\ntreated properly as a mutator). The fix is to explicitely flush these\nbuffers after attaching and before really becoming a GC thread. This\nused to be a problem only with slave threads, but now that STW phase\nruns with implicit master, similar problem occurs while brining up the\nexplicit master. The old fix is removed, and this new fix is now applied\non both master and slave thread.\n\nSigned-off-by: Aleksandar Micic <amicic@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/48845564f042a37363aa06505cd60b4297bfefa9"},{"sha":"a0fe72df7fa46da56749f24ec40bc7273ef44123","author":{"name":"Keith W. Campbell","email":"95f8b4a83822d17dd9d3a4fe1dcf2f0c5c806590@ca.ibm.com"},"message":"Remove useless typedefs\n\nSigned-off-by: Keith W. Campbell <keithc@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/babsingh/omr/commits/a0fe72df7fa46da56749f24ec40bc7273ef44123"}]}
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