{"push_id":2969160182,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"6b3ffde226e882d11bf7d435d0b1ce31fb8f81b1","before":"288fa0017001ec499b064887137c1186f979514d","commits":[{"sha":"47bf9d871356847ddfd33892757c1f9a86243970","author":{"name":"Dillon Huff","email":"9c13e86ac918213c05aedcfed120a4bda70fe397@gmail.com"},"message":"Creating if else tb","distinct":true,"url":"https://api.github.com/repos/dillonhuff/DHLS/commits/47bf9d871356847ddfd33892757c1f9a86243970"},{"sha":"04472becdd7f912405e6f272df9933af54071377","author":{"name":"Dillon Huff","email":"9c13e86ac918213c05aedcfed120a4bda70fe397@gmail.com"},"message":"Need to add wire widths to verilog output instead of just default widths of 32. Also need to save instruction results","distinct":true,"url":"https://api.github.com/repos/dillonhuff/DHLS/commits/04472becdd7f912405e6f272df9933af54071377"},{"sha":"cb62943baf5588a4fa3c56cd8f0b8b5d1a08bdf0","author":{"name":"Dillon Huff","email":"9c13e86ac918213c05aedcfed120a4bda70fe397@gmail.com"},"message":"Need to print out registers for intermediate values","distinct":true,"url":"https://api.github.com/repos/dillonhuff/DHLS/commits/cb62943baf5588a4fa3c56cd8f0b8b5d1a08bdf0"},{"sha":"6b3ffde226e882d11bf7d435d0b1ce31fb8f81b1","author":{"name":"Dillon Huff","email":"9c13e86ac918213c05aedcfed120a4bda70fe397@gmail.com"},"message":"Now printing out storage dummy line","distinct":true,"url":"https://api.github.com/repos/dillonhuff/DHLS/commits/6b3ffde226e882d11bf7d435d0b1ce31fb8f81b1"}]}
{"actor":{"display_login":"dillonhuff"}}