{"push_id":2921774794,"size":3,"distinct_size":3,"ref":"refs/heads/_v9,3_3__powerpc_sysfs_Add_topology_smallcore_thread_siblings__list__mbox_next","head":"de0ae8a0cdfa047bc4451bf9f34a1ea3b6af4885","before":"c3afed97925768f11f7fa8e0f34d67f27c9a5a21","commits":[{"sha":"801bd9cb3abea7ee50ec6e25375d68f57afa64b4","author":{"name":"Gautham R. Shenoy","email":"c13571dbffa0eb89c7f8eebdce482897b0f5a685@linux.vnet.ibm.com"},"message":"powerpc: Detect the presence of big-cores via \"ibm, thread-groups\"\n\nOn IBM POWER9, the device tree exposes a property array identifed by\n\"ibm,thread-groups\" which will indicate which groups of threads share\na particular set of resources.\n\nAs of today we only have one form of grouping identifying the group of\nthreads in the core that share the L1 cache, translation cache and\ninstruction data flow.\n\nThis patch adds helper functions to parse the contents of\n\"ibm,thread-groups\" and populate a per-cpu variable to cache\ninformation about siblings of each CPU that share the L1, traslation\ncache and instruction data-flow.\n\nIt also defines a new global variable named \"has_big_cores\" which\nindicates if the cores on this configuration have multiple groups of\nthreads that share L1 cache.\n\nFor each online CPU, it maintains a cpu_smallcore_mask, which\nindicates the online siblings which share the L1-cache with it.\n\nSigned-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/801bd9cb3abea7ee50ec6e25375d68f57afa64b4"},{"sha":"1ac821d87c13dadd51033923d3217f4bab0309ab","author":{"name":"Gautham R. Shenoy","email":"c13571dbffa0eb89c7f8eebdce482897b0f5a685@linux.vnet.ibm.com"},"message":"powerpc: Use cpu_smallcore_sibling_mask at SMT level on bigcores\n\nPOWER9 SMT8 cores consist of two groups of threads, where threads in\neach group shares L1-cache. The scheduler is not aware of this\ndistinction as the current sched-domain hierarchy has all the threads\nof the core defined at the SMT domain.\n\n\tSMT  [Thread siblings of the SMT8 core]\n\tDIE  [CPUs in the same die]\n\tNUMA [All the CPUs in the system]\n\nDue to this, we can observe run-to-run variance when we run a\nmulti-threaded benchmark bound to a single core based on how the\nscheduler spreads the software threads across the two groups in the\ncore.\n\nWe fix this in this patch by defining each group of threads which\nshare L1-cache to be the SMT level. The group of threads in the SMT8\ncore is defined to be the CACHE level. The sched-domain hierarchy\nafter this patch will be :\n\n\tSMT\t[Thread siblings in the core that share L1 cache]\n\tCACHE \t[Thread siblings that are in the SMT8 core]\n\tDIE  \t[CPUs in the same die]\n\tNUMA \t[All the CPUs in the system]\n\nSigned-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/1ac821d87c13dadd51033923d3217f4bab0309ab"},{"sha":"de0ae8a0cdfa047bc4451bf9f34a1ea3b6af4885","author":{"name":"Gautham R. Shenoy","email":"c13571dbffa0eb89c7f8eebdce482897b0f5a685@linux.vnet.ibm.com"},"message":"powerpc/sysfs: Add topology/smallcore_thread_siblings[_list]\n\nThis patch adds two sysfs attributes named smallcore_thread_siblings\nand smallcore_thread_siblings_list to the \"topology\" attribute group\nfor each CPU device.\n\nThe read-only attributes\n/sys/device/system/cpu/cpuN/topology/smallcore_thread_siblings and\n/sys/device/system/cpu/cpuN/topology/smallcore_thread_siblings_list\nwill the online siblings of CPU N that share the L1 cache with it on\nbig-core configurations in cpumask format and cpu-list format\nrespectively.\n\nSigned-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/de0ae8a0cdfa047bc4451bf9f34a1ea3b6af4885"}]}
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