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<sergii.romantsov@globallogic.com>\nReviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/97fcccb25ed5f55139c03ebc1c71742f0f25f683"},{"sha":"69874e9a6a61d1af92e4d70adaefe1308582c3a1","author":{"name":"Lionel Landwerlin","email":"9463032a5b99ffad10f36631678a833369a311b5@intel.com"},"message":"intel/genxml: turn SLM Enable bit into boolean\n\nSigned-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/69874e9a6a61d1af92e4d70adaefe1308582c3a1"},{"sha":"f73f748323ef5a421ffd8fa0f02afd9627e31023","author":{"name":"Eric Anholt","email":"96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net"},"message":"v3d: Fix SRC_ALPHA_SATURATE blending for RTs without alpha.\n\nFixes\ndEQP-GLES3.functional.fragment_ops.blend.default_framebuffer.rgb_func_alpha_func.dst.src_alpha_saturate_src_alpha_saturate\nand friends with --deqp-egl-config-name=rgb565d0s0\n\nCc: \"18.2\" <mesa-stable@lists.freedesktop.org>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/f73f748323ef5a421ffd8fa0f02afd9627e31023"},{"sha":"a91b158bd9e1b6bc08f1d5ac350cd8b68e372042","author":{"name":"Eric Anholt","email":"96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net"},"message":"v3d: Fix setup of the VCM cache size.\n\nThere were two bugs working together to make things mostly work: I wasn't\ndividing the VPM output size available by the size of a batch (vertex),\nbut I also had the size of the VPM reduced by a factor of 8.\n\nFixes dEQP-GLES3.functional.vertex_array_objects.all_attributes and it\nseems also my intermittent varying failures.\n\nFixes: 1561e4984eb0 (\"v3d: Emit the VCM_CACHE_SIZE packet.\")","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/a91b158bd9e1b6bc08f1d5ac350cd8b68e372042"},{"sha":"f9e630e23dfa3de815026a08e7e767e2ed90da0b","author":{"name":"Jason Ekstrand","email":"b186559eaedf698788888c8a2559b4efb4db10d6@intel.com"},"message":"i965: Workaround the gen9 hw astc5x5 sampler bug\n\ngen9 hardware has a bug in the sampler cache that can cause GPU hangs\nwhenever an texture with aux compression enabled is in the sampler cache\ntogether with an ASTC5x5 texture.  Because we can't control what the\nclient binds at any given time, we have two options: resolve the CCS or\ndecompresss the ASTC.  Doing a CCS or HiZ resolve is far less drastic\nand will likely have a smaller performance impact.\n\nCc: mesa-stable@lists.freedesktop.org\nReviewed-by: Kristian H. Kristensen <hoegsberg@google.com>\nTested-by: Tapani Pälli <tapani.palli@intel.com>\nReviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/f9e630e23dfa3de815026a08e7e767e2ed90da0b"},{"sha":"f6a9f44529457bb16ddcfe3e9bf6095d767c68c8","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs: Add release notes for 18.1.8","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/f6a9f44529457bb16ddcfe3e9bf6095d767c68c8"},{"sha":"d514f556114a6f69c02a7fc5fd6befa0c5079390","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs/relnotes: Add sha256 sums for mesa 18.1.8","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/d514f556114a6f69c02a7fc5fd6befa0c5079390"},{"sha":"aa4386ebfed6a76badae9e1ecf783a372375f072","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs: update calendar, add news item and link release notes for X.Y.Z\n\nSigned-off-by: Dylan Baker <dylan@pnwbakers.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/aa4386ebfed6a76badae9e1ecf783a372375f072"},{"sha":"80825abb5d1a7491035880253ffd531c55acae6b","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"move u_math to src/util\n\nCurrently we have two sets of functions for bit counts, one in gallium\nand one in core mesa. The ones in core mesa are header only in many\ncases, since they reduce to \"#define _mesa_bitcount popcount\", but they\nprovide a fallback implementation. This is important because 32bit msvc\ndoesn't have popcountll, just popcount; so when nir (for example)\nincludes the core mesa header it doesn't (and shouldn't) link with core\nmesa. To fix this we'll promote the version out of gallium util, then\nreplace the core mesa uses with the util version, since nir (and other\nnon-core mesa users) can and do link with mesautils.\n\nAcked-by: Eric Engestrom <eric.engestrom@intel.com>\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/80825abb5d1a7491035880253ffd531c55acae6b"},{"sha":"8396043f304bb2a752130230055605c5c966e89f","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"Replace uses of _mesa_bitcount with util_bitcount\n\nand _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem\nin nir for platforms that don't have popcount or popcountll, such as\n32bit msvc.\n\nv2: - Fix additional uses of _mesa_bitcount added after this was\n      originally written\n\nAcked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)\nAcked-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/8396043f304bb2a752130230055605c5c966e89f"},{"sha":"a84fd58f48fa332b1c5a545d9b7e2440b8784656","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/u_cpu_detect: fix a race condition on initialization\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/a84fd58f48fa332b1c5a545d9b7e2440b8784656"},{"sha":"ce432e259d0e73299b7a86b0732efd27340d995f","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/u_cpu_detect: fix parsing the CPU family\n\nAccording to:\nhttps://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf\n\nAlso Intel:\nhttps://www.microbe.cz/docs/CPUID.pdf\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/ce432e259d0e73299b7a86b0732efd27340d995f"},{"sha":"15fa2c5e359149a0b67b8572cd7dab87626b48ae","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/15fa2c5e359149a0b67b8572cd7dab87626b48ae"},{"sha":"6d477bc5460eec14c6a0d047a0384c9ce5c7609b","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium/os_thread: simplify helper pipe_current_thread_get_time_nano\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/6d477bc5460eec14c6a0d047a0384c9ce5c7609b"},{"sha":"e5e3b5cdcc38ce1111b134e6fe5bc4d00c8c715f","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"gallium: add pipe_context::set_context_param for tuning perf on AMD Zen (v2)\n\nState trackers will not use the new param directly, but will instead use\na helper in MakeCurrent that does the right thing.\n\nv2: rework the interface\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/e5e3b5cdcc38ce1111b134e6fe5bc4d00c8c715f"},{"sha":"8d473f555a0c3c94cffd18e68a13274488dcfb17","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"st/mesa: pin driver threads to a specific L3 cache on AMD Zen (v2)\n\nv2: use set_context_param\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":false,"url":"https://api.github.com/repos/chewitt/mesa/commits/8d473f555a0c3c94cffd18e68a13274488dcfb17"}]}
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