{"action":"created","issue":{"url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/146","repository_url":"https://api.github.com/repos/SpinalHDL/SpinalHDL","labels_url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/146/labels{/name}","comments_url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/146/comments","events_url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/146/events","html_url":"https://github.com/SpinalHDL/SpinalHDL/issues/146","id":359167562,"node_id":"MDU6SXNzdWUzNTkxNjc1NjI=","number":146,"title":"VHDL support in SpinalSim using GHDL as a backend","user":{"login":"1138-4EB","id":6628437,"node_id":"MDQ6VXNlcjY2Mjg0Mzc=","avatar_url":"https://avatars1.githubusercontent.com/u/6628437?v=4","gravatar_id":"","url":"https://api.github.com/users/1138-4EB","html_url":"https://github.com/1138-4EB","followers_url":"https://api.github.com/users/1138-4EB/followers","following_url":"https://api.github.com/users/1138-4EB/following{/other_user}","gists_url":"https://api.github.com/users/1138-4EB/gists{/gist_id}","starred_url":"https://api.github.com/users/1138-4EB/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/1138-4EB/subscriptions","organizations_url":"https://api.github.com/users/1138-4EB/orgs","repos_url":"https://api.github.com/users/1138-4EB/repos","events_url":"https://api.github.com/users/1138-4EB/events{/privacy}","received_events_url":"https://api.github.com/users/1138-4EB/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2018-09-11T18:31:12Z","updated_at":"2018-09-12T10:46:36Z","closed_at":null,"author_association":"NONE","body":"While reading https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/, I wondered whether any effort has been done in order to replicate the workflow with VHDL sources. [ghdl/ghdl](https://github.com/ghdl/ghdl) can be used to compile VHDL files to C (shared) objects, just as [Verilator](https://www.veripool.org/wiki/verilator) is used with Verilog sources.\r\n\r\nI am actually seeking to generate and compile a VHDL version of [Murax SoC](https://github.com/SpinalHDL/VexRiscv#murax-soc), to then simulate the execution of some of the example programs."},"comment":{"url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/comments/420602094","html_url":"https://github.com/SpinalHDL/SpinalHDL/issues/146#issuecomment-420602094","issue_url":"https://api.github.com/repos/SpinalHDL/SpinalHDL/issues/146","id":420602094,"node_id":"MDEyOklzc3VlQ29tbWVudDQyMDYwMjA5NA==","user":{"login":"Dolu1990","id":4832082,"node_id":"MDQ6VXNlcjQ4MzIwODI=","avatar_url":"https://avatars0.githubusercontent.com/u/4832082?v=4","gravatar_id":"","url":"https://api.github.com/users/Dolu1990","html_url":"https://github.com/Dolu1990","followers_url":"https://api.github.com/users/Dolu1990/followers","following_url":"https://api.github.com/users/Dolu1990/following{/other_user}","gists_url":"https://api.github.com/users/Dolu1990/gists{/gist_id}","starred_url":"https://api.github.com/users/Dolu1990/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Dolu1990/subscriptions","organizations_url":"https://api.github.com/users/Dolu1990/orgs","repos_url":"https://api.github.com/users/Dolu1990/repos","events_url":"https://api.github.com/users/Dolu1990/events{/privacy}","received_events_url":"https://api.github.com/users/Dolu1990/received_events","type":"User","site_admin":false},"created_at":"2018-09-12T10:46:36Z","updated_at":"2018-09-12T10:46:36Z","author_association":"MEMBER","body":"Actualy, there is this interface in the spinal.sim sources : \r\nhttps://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/SimRaw.scala#L15\r\nwhich as to be implemented for a given target simulator\r\nFor Verilator it's implemented as following : \r\nhttps://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/SimVerilator.scala\r\n+\r\nhttps://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/VerilatorBackend.scala\r\n\r\nSo in the case of verilator it wasn't a crazy amount of work. Then i have no idea how the ghdl shared object interface appear :)"}}
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