{"action":"created","comment":{"url":"https://api.github.com/repos/freechipsproject/firrtl/pulls/comments/175972903","pull_request_review_id":105593861,"id":175972903,"diff_hunk":"@@ -18,134 +19,301 @@ case class NoDedupAnnotation(target: ModuleName) extends SingleTargetAnnotation[\n   def duplicate(n: ModuleName) = NoDedupAnnotation(n)\n }\n \n-// Only use on legal Firrtl. Specifically, the restriction of\n-//  instance loops must have been checked, or else this pass can\n-//  infinitely recurse\n+/** Only use on legal Firrtl.\n+  *\n+  * Specifically, the restriction of instance loops must have been checked, or else this pass can\n+  *  infinitely recurse\n+  */\n class DedupModules extends Transform {\n-  def inputForm = HighForm\n-  def outputForm = HighForm\n-  // Orders the modules of a circuit from leaves to root\n-  // A module will appear *after* all modules it instantiates\n-  private def buildModuleOrder(c: Circuit): Seq[String] = {\n-    val moduleOrder = mutable.ArrayBuffer.empty[String]\n-    def hasInstance(b: Statement): Boolean = {\n-      var has = false\n-      def onStmt(s: Statement): Statement = s map onStmt match {\n-        case DefInstance(i, n, m) =>\n-          if(!(moduleOrder contains m)) has = true\n-          s\n-        case WDefInstance(i, n, m, t) =>\n-          if(!(moduleOrder contains m)) has = true\n-          s\n-        case _ => s\n-      }\n-      onStmt(b)\n-      has\n+  def inputForm: CircuitForm = HighForm\n+  def outputForm: CircuitForm = HighForm\n+\n+  /**\n+    * Deduplicate a Circuit\n+    * @param state Input Firrtl AST\n+    * @return A transformed Firrtl AST\n+    */\n+  def execute(state: CircuitState): CircuitState = {\n+    val noDedups = state.annotations.collect { case NoDedupAnnotation(ModuleName(m, c)) => m }\n+    val (newC, renameMap) = run(state.circuit, noDedups)\n+    state.copy(circuit = newC, renames = Some(renameMap))\n+  }\n+\n+  /**\n+    * Deduplicates a circuit, and records renaming\n+    * @param c Circuit to dedup\n+    * @param noDedups Modules not to dedup\n+    * @return Deduped Circuit and corresponding RenameMap\n+    */\n+  def run(c: Circuit, noDedups: Seq[String]): (Circuit, RenameMap) = {\n+\n+    // RenameMap\n+    val renameMap = RenameMap()\n+    renameMap.setCircuit(c.main)\n+\n+    // Maps module name to corresponding dedup module\n+    val dedupMap = DedupModules.deduplicate(c, noDedups.toSet, renameMap)\n+\n+    // Use old module list to preserve ordering\n+    val dedupedModules = c.modules.map(m => dedupMap(m.name)).distinct\n+\n+    val cname = CircuitName(c.main)\n+    renameMap.addMap(dedupMap.map { case (from, to) =>\n+      logger.debug(s\"[Dedup] $from -> ${to.name}\")\n+      ModuleName(from, cname) -> List(ModuleName(to.name, cname))\n+    })\n+\n+    (InferTypes.run(c.copy(modules = dedupedModules)), renameMap)\n+  }\n+}\n+\n+/**\n+  * Utility functions for [[DedupModules]]\n+  */\n+object DedupModules {\n+  /**\n+    * Change's a module's internal signal names, types, infos, and modules.\n+    * Populates renameMap.","path":"src/main/scala/firrtl/transforms/Dedup.scala","position":91,"original_position":91,"commit_id":"b9d305f17241ba56959fa82b4a10c7a90e7c7c81","original_commit_id":"7c8285a5808fe54953528cd067dfde35d60cb567","user":{"login":"jackkoenig","id":8584418,"avatar_url":"https://avatars3.githubusercontent.com/u/8584418?v=4","gravatar_id":"","url":"https://api.github.com/users/jackkoenig","html_url":"https://github.com/jackkoenig","followers_url":"https://api.github.com/users/jackkoenig/followers","following_url":"https://api.github.com/users/jackkoenig/following{/other_user}","gists_url":"https://api.github.com/users/jackkoenig/gists{/gist_id}","starred_url":"https://api.github.com/users/jackkoenig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jackkoenig/subscriptions","organizations_url":"https://api.github.com/users/jackkoenig/orgs","repos_url":"https://api.github.com/users/jackkoenig/repos","events_url":"https://api.github.com/users/jackkoenig/events{/privacy}","received_events_url":"https://api.github.com/users/jackkoenig/received_events","type":"User","site_admin":false},"body":"Where's the renameMap being populated?","created_at":"2018-03-21T02:21:12Z","updated_at":"2018-03-21T02:21:12Z","html_url":"https://github.com/freechipsproject/firrtl/pull/766#discussion_r175972903","pull_request_url":"https://api.github.com/repos/freechipsproject/firrtl/pulls/766","author_association":"CONTRIBUTOR","_links":{"self":{"href":"https://api.github.com/repos/freechipsproject/firrtl/pulls/comments/175972903"},"html":{"href":"https://github.com/freechipsproject/firrtl/pull/766#discussion_r175972903"},"pull_request":{"href":"https://api.github.com/repos/freechipsproject/firrtl/pulls/766"}}},"pull_request":{"url":"https://api.github.com/repos/freechipsproject/firrtl/pulls/766","id":175958064,"html_url":"https://github.com/freechipsproject/firrtl/pull/766","diff_url":"https://github.com/freechipsproject/firrtl/pull/766.diff","patch_url":"https://github.com/freechipsproject/firrtl/pull/766.patch","issue_url":"https://api.github.com/repos/freechipsproject/firrtl/issues/766","number":766,"state":"open","locked":false,"title":"GroupModule Transform","user":{"login":"azidar","id":5377148,"avatar_url":"https://avatars1.githubusercontent.com/u/5377148?v=4","gravatar_id":"","url":"https://api.github.com/users/azidar","html_url":"https://github.com/azidar","followers_url":"https://api.github.com/users/azidar/followers","following_url":"https://api.github.com/users/azidar/following{/other_user}","gists_url":"https://api.github.com/users/azidar/gists{/gist_id}","starred_url":"https://api.github.com/users/azidar/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/azidar/subscriptions","organizations_url":"https://api.github.com/users/azidar/orgs","repos_url":"https://api.github.com/users/azidar/repos","events_url":"https://api.github.com/users/azidar/events{/privacy}","received_events_url":"https://api.github.com/users/azidar/received_events","type":"User","site_admin":false},"body":"This pass takes a GroupAnnotation of multiple signals in a module, and will group them into their own module (and then instantiate and connect to the new module).\r\n\r\nReviewer Checklist:\r\n- [x] Revert my reverts of sbt bumps\r\n- [x] Remove WireHelper stub\r\n- [x] Discuss orderedLinearization, probably remove it\r\n- [x] Add checks for DefInstance and WDefInstanceConnector\r\n- [x] Add blacklist to documentation in DiGraph\r\n- [x] Add spaces around the @\r\n- [x] Add spaces around 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