{"action":"opened","number":63,"pull_request":{"url":"https://api.github.com/repos/timvideos/litex-buildenv/pulls/63","id":216467851,"node_id":"MDExOlB1bGxSZXF1ZXN0MjE2NDY3ODUx","html_url":"https://github.com/timvideos/litex-buildenv/pull/63","diff_url":"https://github.com/timvideos/litex-buildenv/pull/63.diff","patch_url":"https://github.com/timvideos/litex-buildenv/pull/63.patch","issue_url":"https://api.github.com/repos/timvideos/litex-buildenv/issues/63","number":63,"state":"open","locked":false,"title":"Updating submodules.","user":{"login":"mithro","id":21212,"node_id":"MDQ6VXNlcjIxMjEy","avatar_url":"https://avatars2.githubusercontent.com/u/21212?v=4","gravatar_id":"","url":"https://api.github.com/users/mithro","html_url":"https://github.com/mithro","followers_url":"https://api.github.com/users/mithro/followers","following_url":"https://api.github.com/users/mithro/following{/other_user}","gists_url":"https://api.github.com/users/mithro/gists{/gist_id}","starred_url":"https://api.github.com/users/mithro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mithro/subscriptions","organizations_url":"https://api.github.com/users/mithro/orgs","repos_url":"https://api.github.com/users/mithro/repos","events_url":"https://api.github.com/users/mithro/events{/privacy}","received_events_url":"https://api.github.com/users/mithro/received_events","type":"User","site_admin":false},"body":"```\r\n * edid-decode changed from b2da151 to 5eeb151\r\n    * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB <Hans Verkuil>\r\n\r\n * litedram changed from 7a5ac75 to e5696ad\r\n    * e5696ad - frontend/ecc: add enable csr <Florent Kermarrec>\r\n    * e6ef89a - frontend/axi: optimize burst2beat timings <Florent Kermarrec>\r\n    * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings <Florent Kermarrec>\r\n    * 041817d - frontend/ecc: use csr instead of signal for control <Florent Kermarrec>\r\n    * b145b0c - frontend/axi: fix write response implementation <Florent Kermarrec>\r\n    * d23dbf6 - phy: add nranks to all phys <Florent Kermarrec>\r\n    * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec>\r\n    * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec>\r\n    * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec>\r\n    * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec>\r\n    * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec>\r\n    * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec>\r\n    * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec>\r\n    * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec>\r\n    * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec>\r\n    * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec>\r\n    * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec>\r\n    *   412e9a5 - Merge pull request #38 from enjoy-digital/multirank <enjoy-digital>\r\n    |\\\r\n    | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec>\r\n    | * d4f434d - dfii: send command to all ranks <Florent Kermarrec>\r\n    | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec>\r\n    * |   d9c2430 - Merge pull request #36 from JohnSully/timing_1 <enjoy-digital>\r\n    |\\ \\\r\n    | |/\r\n    |/|\r\n    | * efd7a47 - Fix failing timing <>\r\n    * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec>\r\n    |/\r\n    * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec>\r\n    * 1fa73e4 - test: update <Florent Kermarrec>\r\n    * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec>\r\n    * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec>\r\n    * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec>\r\n    * 700f76c - frontend/axi: add resp signals <Florent Kermarrec>\r\n    * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec>\r\n    * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec>\r\n    * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec>\r\n    * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec>\r\n    * ebba39d - README: update <Florent Kermarrec>\r\n    * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec>\r\n    * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec>\r\n    * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec>\r\n    * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec>\r\n    * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec>\r\n    * dce4ede - README: update <Florent Kermarrec>\r\n    * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec>\r\n    * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec>\r\n    * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec>\r\n    * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec>\r\n    * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec>\r\n    * bc8a9ce - README: update <Florent Kermarrec>\r\n    * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec>\r\n    * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec>\r\n    * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec>\r\n    * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec>\r\n    * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec>\r\n    * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec>\r\n    * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec>\r\n    * d5d6737 - frontend/axi: fix read id <Florent Kermarrec>\r\n    * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec>\r\n    * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec>\r\n    * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec>\r\n    * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec>\r\n\r\n * liteeth changed from 24b0d2b to 3d86844\r\n    * 3d86844 - core/mac/sram: fix code refactoring <Florent Kermarrec>\r\n    * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec>\r\n    * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec>\r\n    * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec>\r\n\r\n * litepcie changed from a97a691 to 3e8de2d\r\n    * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec>\r\n    * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec>\r\n\r\n * litesata changed from 002cd25 to fb72044\r\n    * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec>\r\n\r\n * litescope changed from f26e36e to 686db4f\r\n    *   686db4f - Merge pull request #12 from xobs/default-length <enjoy-digital>\r\n    |\\\r\n    | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross>\r\n    |/\r\n    * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec>\r\n    * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec>\r\n    * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec>\r\n\r\n * liteusb changed from e841c56 to 0a9110f\r\n    * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec>\r\n\r\n * litevideo changed from 7b4240f to 13d85a1\r\n    * 13d85a1 - README: update <Florent Kermarrec>\r\n\r\n * litex changed from 7a14b75c to 537b0e90\r\n    *   537b0e90 - Merge pull request #101 from cr1901/icestorm-migen-pull <enjoy-digital>\r\n    |\\\r\n    | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. <William D. Jones>\r\n    * | 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec>\r\n    * | a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec>\r\n    * | 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec>\r\n    * | 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec>\r\n    * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec>\r\n    * | df3f003e - soc_sdram: update with litedram <Florent Kermarrec>\r\n    |/\r\n    *   bebc667d - Merge pull request #99 from cr1901/mk-copy-main-ram <enjoy-digital>\r\n    |\\\r\n    | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones>\r\n    * |   69716852 - Merge pull request #100 from cr1901/tinyprog-fix <enjoy-digital>\r\n    |\\ \\\r\n    | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones>\r\n    | |/\r\n    * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec>\r\n    * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec>\r\n    * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen>\r\n    * |   d9d0320d - Merge pull request #98 from jfng/fix_typo <enjoy-digital>\r\n    |\\ \\\r\n    | * | 22c01313 - fix typo and unused include <Jean-François Nguyen>\r\n    |/ /\r\n    * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec>\r\n    * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec>\r\n    * | 8f377307 - add Minerva support <Jean-François Nguyen>\r\n    * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec>\r\n    |/\r\n    *   c5a2d6f3 - Merge pull request #96 from cr1901/tinyfpga_bx <Tim Ansell>\r\n    |\\\r\n    | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>\r\n    * |   3cb754da - Merge pull request #95 from cr1901/lm32-lite <Tim Ansell>\r\n    |\\ \\\r\n    | * | ed507d61 - Add lm32 \"lite\" variant, remove mult/div from \"minimal\" and update compiler flags accordingly. <William D. Jones>\r\n    | |/\r\n    * | 28cd2da2 - README: update <Florent Kermarrec>\r\n    |/\r\n    * 05c7b9da - Merge pull request #94 from cr1901/nextpnr <enjoy-digital>\r\n    * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones>\r\n\r\n * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c\r\n    * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. <whitequark>\r\n    * b2740d9 - build.lattice.icestorm: write build script even on dry run. <whitequark>\r\n    * 2a7e33e - Emit `default_nettype none. <David Craven>\r\n    * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>\r\n    * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens>\r\n    * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (#124) <William D. Jones>\r\n\r\nFull submodule status\r\n--\r\n 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)\r\n a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)\r\n e5696ad3ef516df8033149f748e5ede93b54b57d litedram (remotes/origin/HEAD)\r\n 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD)\r\n 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD)\r\n fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD)\r\n 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD)\r\n 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)\r\n 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)\r\n 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD)\r\n ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)\r\n```","created_at":"2018-09-18T22:56:54Z","updated_at":"2018-09-18T22:56:54Z","closed_at":null,"merged_at":null,"merge_commit_sha":null,"assignee":null,"assignees":[],"requested_reviewers":[],"requested_teams":[],"labels":[],"milestone":null,"commits_url":"https://api.github.com/repos/timvideos/litex-buildenv/pulls/63/commits","review_comments_url":"https://api.github.com/repos/timvideos/litex-buildenv/pulls/63/comments","review_comment_url":"https://api.github.com/repos/timvideos/litex-buildenv/pulls/comments{/number}","comments_url":"https://api.github.com/repos/timvideos/litex-buildenv/issues/63/comments","statuses_url":"https://api.github.com/repos/timvideos/litex-buildenv/statuses/aea41b3e36effe3acc483d89978a2e7090ec0c0d","head":{"label":"mithro:litex-upgrade","ref":"litex-upgrade","sha":"aea41b3e36effe3acc483d89978a2e7090ec0c0d","user":{"login":"mithro","id":21212,"node_id":"MDQ6VXNlcjIxMjEy","avatar_url":"https://avatars2.githubusercontent.com/u/21212?v=4","gravatar_id":"","url":"https://api.github.com/users/mithro","html_url":"https://github.com/mithro","followers_url":"https://api.github.com/users/mithro/followers","following_url":"https://api.github.com/users/mithro/following{/other_user}","gists_url":"https://api.github.com/users/mithro/gists{/gist_id}","starred_url":"https://api.github.com/users/mithro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mithro/subscriptions","organizations_url":"https://api.github.com/users/mithro/orgs","repos_url":"https://api.github.com/users/mithro/repos","events_url":"https://api.github.com/users/mithro/events{/privacy}","received_events_url":"https://api.github.com/users/mithro/received_events","type":"User","site_admin":false},"repo":{"id":118239861,"node_id":"MDEwOlJlcG9zaXRvcnkxMTgyMzk4NjE=","name":"litex-buildenv","full_name":"mithro/litex-buildenv","private":false,"owner":{"login":"mithro","id":21212,"node_id":"MDQ6VXNlcjIxMjEy","avatar_url":"https://avatars2.githubusercontent.com/u/21212?v=4","gravatar_id":"","url":"https://api.github.com/users/mithro","html_url":"https://github.com/mithro","followers_url":"https://api.github.com/users/mithro/followers","following_url":"https://api.github.com/users/mithro/following{/other_user}","gists_url":"https://api.github.com/users/mithro/gists{/gist_id}","starred_url":"https://api.github.com/users/mithro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mithro/subscriptions","organizations_url":"https://api.github.com/users/mithro/orgs","repos_url":"https://api.github.com/users/mithro/repos","events_url":"https://api.github.com/users/mithro/events{/privacy}","received_events_url":"https://api.github.com/users/mithro/received_events","type":"User","site_admin":false},"html_url":"https://github.com/mithro/litex-buildenv","description":"An environment for building LiteX based FPGA designs. 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