{"action":"opened","issue":{"url":"https://api.github.com/repos/golang/go/issues/26538","repository_url":"https://api.github.com/repos/golang/go","labels_url":"https://api.github.com/repos/golang/go/issues/26538/labels{/name}","comments_url":"https://api.github.com/repos/golang/go/issues/26538/comments","events_url":"https://api.github.com/repos/golang/go/issues/26538/events","html_url":"https://github.com/golang/go/issues/26538","id":343439396,"node_id":"MDU6SXNzdWUzNDM0MzkzOTY=","number":26538,"title":"internal/cpu: MIPS[64] feature detection","user":{"login":"smasher164","id":12636891,"node_id":"MDQ6VXNlcjEyNjM2ODkx","avatar_url":"https://avatars0.githubusercontent.com/u/12636891?v=4","gravatar_id":"","url":"https://api.github.com/users/smasher164","html_url":"https://github.com/smasher164","followers_url":"https://api.github.com/users/smasher164/followers","following_url":"https://api.github.com/users/smasher164/following{/other_user}","gists_url":"https://api.github.com/users/smasher164/gists{/gist_id}","starred_url":"https://api.github.com/users/smasher164/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/smasher164/subscriptions","organizations_url":"https://api.github.com/users/smasher164/orgs","repos_url":"https://api.github.com/users/smasher164/repos","events_url":"https://api.github.com/users/smasher164/events{/privacy}","received_events_url":"https://api.github.com/users/smasher164/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2018-07-22T21:15:33Z","updated_at":"2018-07-22T21:15:33Z","closed_at":null,"author_association":"CONTRIBUTOR","body":"This might already be in the works, but certain mathematical functions can be sped up by taking advantage of built-in MIPS instructions. In my case, an FMA intrinsic (#25819) can use `MADDF.D fd, fs, ft`, which is available to a subset of mips64r6. The cp0.Config0, cp0.Config1, and cp1.FIR registers contain the necessary information to detect this feature. Unfortunately, reading from cp0 requires the privileged instruction mfc0.\r\n\r\nThat means that the following code to detect FMA support on mips64 will receive a SIGILL on the marked line:\r\n```Go\r\nTEXT ·isFMASupported(SB),NOSPLIT,$0\r\n#ifndef GOMIPS64_softfloat\r\n    // CP0.Config0[14:13] == 0b10 <==> Release 6\r\n    MOVW M16, R8 // <-- mfc0 causes a SIGILL\r\n    SRL $13, R8\r\n    AND $3, R8\r\n    MOVW $2, R9\r\n    BNE R9, R8, nosupport\r\n    // CP0.Config1[1:0] == 1 <==> FPU enabled\r\n    // mfc0 8, 16, 1\r\n    WORD $0x40088001\r\n    AND $1, R8\r\n    BEQ R0, R9, nosupport\r\n    // CP1.FIR[18:17] == 1 <==> Double-precision operations supported\r\n    // CFC1 $0, R8\r\n    MOVW FCR0, R8\r\n    SRL $17, R8\r\n    AND $1, R8\r\n    MOVB R8, ret(FP)\r\nnosupport:\r\n#endif\r\n    RET\r\n```\r\nIf `internal/cpu` exports the required Config registers as described in sections 9.42 and 9.43 in https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00091-2B-MIPS64PRA-AFP-05.04.pdf, runtime specialization of MIPS code will become much simpler."}}
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