{"push_id":2735154101,"size":21,"distinct_size":21,"ref":"refs/heads/master","head":"da417eb8ed4bbaf149c31d197eb56fc8a5abbf68","before":"4c6d0de7bad46fc15fd34d394dffda3766e3a6a1","commits":[{"sha":"60ee3bd8dbe70189cab18af733c42187c9b317c7","author":{"name":"Zhang, Chao B","email":"fed49a7a524fbe970930fd44cd2de5a9d4952d81@intel.com"},"message":"SecurityPkg:Tcg: Fix comment typos\n\n\"Triggle\" is a typo. Replace it with \"Trigger\"\n\nCc: Long Qin <qin.long@intel.com>\nCc: Jiewen Yao <jiewen.yao@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Chao Zhang <chao.b.zhang@intel.com>\nReviewed-by: Long Qin <qin.long@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/60ee3bd8dbe70189cab18af733c42187c9b317c7"},{"sha":"d900d7c9857a676d9271a0ab499c12b379dc3652","author":{"name":"Yonghong Zhu","email":"78d981fe33a016071af5222c56d5cf77f30fb0b2@intel.com"},"message":"BaseTools: Remove the duplicate Pcd items\n\nThe case is the Pcd item both used in 1 module inf and 1 lib inf, and\nin the DSC component section, it override the Pcd value.\nIn the module, the pcd value is the override value, but in the lib inf\nthe pcd value is the value that in the DSC PCD section's value, then it\ncause the Pcd value is different in the module and lib. but actually we\nonly need use the Pcd value in the module to decide whether it use the\nsame value.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Yonghong Zhu <yonghong.zhu@intel.com>\nReviewed-by: Liming Gao <liming.gao@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/d900d7c9857a676d9271a0ab499c12b379dc3652"},{"sha":"6936ee0342d25bea9f44499444ba1e4df6fc2200","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Relocate uCode to memory to save time.\n\nRead uCode from memory has better performance than from flash.\nBut it needs extra effort to let BSP copy uCode from flash to\nmemory. Also BSP already enable cache in SEC phase, so it use\nless time to relocate uCode from flash to memory. After\nverification, if system has more than one processor, it will\nreduce some time if load uCode from memory.\n\nThis change enable this optimization.\n\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nReviewed-by: Laszlo Ersek <lersek@redhat.com>\nRegression-tested-by: Laszlo Ersek <lersek@redhat.com>\nReviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/6936ee0342d25bea9f44499444ba1e4df6fc2200"},{"sha":"2a08913443bb3fff0056cc555e260b2c3fdd2120","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Use BSP uCode for APs if possible.\n\nSearch uCode costs much time, if AP has same processor type\nwith BSP, AP can use BSP saved uCode info to get better performance.\n\nThis change enables this solution.\n\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nAcked-by: Laszlo Ersek <lersek@redhat.com>\nRegression-tested-by: Laszlo Ersek <lersek@redhat.com>\nReviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/2a08913443bb3fff0056cc555e260b2c3fdd2120"},{"sha":"f63a3e286765f47b79a73d56f8d687c4f3733979","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Load uCode once for each core.\n\nThe SDM requires only one thread per core to load the\nmicrocode.\n\nThis change enables this solution.\n\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nAcked-by: Laszlo Ersek <lersek@redhat.com>\nRegression-tested-by: Laszlo Ersek <lersek@redhat.com>\nReviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/f63a3e286765f47b79a73d56f8d687c4f3733979"},{"sha":"58942277bcbf41abda5f6e3a1c89d571105d5983","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Fix S3 resume hang issue.\n\nWhen resume from S3 and CPU loop mode is MWait mode,\nif driver calls APs to do task at EndOfPei point, the\nAPs can't been wake up and bios hang at that point.\n\nThe root cause is PiSmmCpuDxeSmm driver wakes up APs\nwith HLT mode during S3 resume phase to do SMM relocation.\nAfter this task, PiSmmCpuDxeSmm driver not restore APs\ncontext which make CpuMpPei driver saved wake up buffer\nnot works.\n\nThe solution for this issue is let CpuMpPei driver hook\nS3SmmInitDone ppi notification. In this notify function,\nit check whether Cpu Loop mode is not HLT mode. If yes,\nCpuMpPei driver will set a flag to force BSP use INIT-SIPI\n-SIPI command to wake up the APs.\n\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nReviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/58942277bcbf41abda5f6e3a1c89d571105d5983"},{"sha":"a3fffb4f5e1535e8e542669925eed489fdce6b62","author":{"name":"Laszlo Ersek","email":"7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com"},"message":"OvmfPkg/AcpiPlatformDxe: clean up libs and protos in \"AcpiPlatformDxe.inf\"\n\nNone of the source files referenced by \"AcpiPlatformDxe.inf\" #include\n\"MdePkg/Include/Library/DxeServicesLib.h\" or use interfaces declared\ntherein, so drop DxeServicesLib from [LibraryClasses].\n\n\"AcpiPlatformDxe.inf\" references \"AcpiPlatform.c\", which installs ACPI\ntables built into the firmware image from under \"OvmfPkg/AcpiTables/\", in\ncase dynamically generated ACPI tables are not available from Xen or QEMU.\nFor this, the driver consumes gEfiFirmwareVolume2ProtocolGuid. Account for\nthat in [Protocols].\n\nCc: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nCc: Jordan Justen <jordan.l.justen@intel.com>\nCc: Steven Shi <steven.shi@intel.com>\nReported-by: Steven Shi <steven.shi@intel.com>\nRef: https://bugzilla.tianocore.org/show_bug.cgi?id=1014\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Laszlo Ersek <lersek@redhat.com>\nReviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/a3fffb4f5e1535e8e542669925eed489fdce6b62"},{"sha":"e52838d358d5062c4b1ed8e87bdc3d0f527095d3","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Optimize get processor number performance.\n\nCurrent function has low performance because it calls GetApicId\nin the loop, so it maybe called more than once.\n\nNew logic call GetApicId once and base on this value to search\nthe processor.\n\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nCc: Jeff Fan <vanjeff_919@hotmail.com>\nCc: Laszlo Ersek <lersek@redhat.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nReviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>\nReviewed-by: Laszlo Ersek <lersek@redhat.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/e52838d358d5062c4b1ed8e87bdc3d0f527095d3"},{"sha":"a234383c5bc28c5545b2988edc59f0cbdb123afd","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Remove useless code.\n\nRemove the useless code error added by change\n58942277bcbf41abda5f6e3a1c89d571105d5983.\n\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Ruiyu Ni <ruiyu.ni@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Eric Dong <eric.dong@intel.com>\nReviewed-by: Laszlo Ersek <lersek@redhat.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/a234383c5bc28c5545b2988edc59f0cbdb123afd"},{"sha":"9b7242f5dec7649b878a4058f893103885520bf7","author":{"name":"Eric Dong","email":"fa9eeec52367040ac98013bc4b2913db170588f8@intel.com"},"message":"UefiCpuPkg/MpInitLib: Fix VS2012 build failure\n\nCc: Eric Dong <eric.dong@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Dandan Bi <dandan.bi@intel.com>\nReviewed-by: Eric Dong <eric.dong@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/9b7242f5dec7649b878a4058f893103885520bf7"},{"sha":"b72f4873726b679fb4681ac26abfae227aaa13f1","author":{"name":"Jian J Wang","email":"01d7c53c587e21672fb6c249cfdc88bbd3aecc19@intel.com"},"message":"UefiCpuPkg/CpuDxe: fix incorrect check of SMM mode\n\nCurrent IsInSmm() method makes use of gEfiSmmBase2ProtocolGuid.InSmm() to\ncheck if current processor is in SMM mode or not. But this is not correct\nbecause gEfiSmmBase2ProtocolGuid.InSmm() can only detect if the caller is\nrunning in SMRAM or from SMM driver. It cannot guarantee if the caller is\nrunning in SMM mode. Because SMM mode will load its own page table, adding\nan extra check of saved DXE page table base address against current CR3\nregister value can help to get the correct answer for sure (in SMM mode or\nnot in SMM mode).\n\nThere's indiscriminate uses of Context.X64 and Context.Ia32 in code which\nis not a good coding practice and will cause potential issue. In addition,\nthe related structure type definition is not packed and has also potential\nissue. This will not be covered by this patch but be tracked by a bug below.\n\n  https://bugzilla.tianocore.org/show_bug.cgi?id=1039\n\nThis is an issue caused by check-in at\n\n  2a1408d1d739ead00c96397549be7a9fc53c9c6e\n\nCc: Eric Dong <eric.dong@intel.com>\nCc: Laszlo Ersek <lersek@redhat.com>\nCc: Jiewen Yao <jiewen.yao@intel.com>\nCc: Star Zeng <star.zeng@intel.com>\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Jian J Wang <jian.j.wang@intel.com>\nReviewed-by: Eric Dong <eric.dong@intel.com>\nRegression-tested-by: Laszlo Ersek <lersek@redhat.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/b72f4873726b679fb4681ac26abfae227aaa13f1"},{"sha":"2cde4bbadc09a6822e1e653fc4ef46a7106bfe79","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg: Delete StandaloneMmPkg file.\n\nThis patch deletes \"StandaloneMmPkg\" which was created as a file\nintially. This patch enables creation of \"StandaloneMmPkg\" as a folder.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/2cde4bbadc09a6822e1e653fc4ef46a7106bfe79"},{"sha":"e85162acb9f3ff3bdb87b6575fe9b29e99160ab6","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg/FvLib: Add a common FV Library for management mode.\n\nThis patch implements a firmware volume library that can be used by the\nStandalone management mode core module to parse the firmware volume.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/e85162acb9f3ff3bdb87b6575fe9b29e99160ab6"},{"sha":"880086a2b59075563cff2cf1af58910a273cd30d","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg/MemLib: Add Standalone MM instance of memory check library.\n\nMM memory check library library implementation. This library consumes\nMM_ACCESS_PROTOCOL to get MMRAM information. In order to use this\nlibrary instance, the platform should produce all MMRAM range via\nMM_ACCESS_PROTOCOL, including the range for firmware (like MM Core\nand MM driver) and/or specific dedicated hardware.\n\nThis patch provides services for MM Memory Operation.\nThe management mode Mem Library provides function for checking if buffer\nis outside MMRAM and valid. It also provides functions for copy data\nfrom MMRAM to non-MMRAM, from non-MMRAM to MMRAM,\nfrom non-MMRAM to non-MMRAM, or set data in non-MMRAM.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/880086a2b59075563cff2cf1af58910a273cd30d"},{"sha":"2c868eef731586de781adb96a1ce837de76c0dae","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg/MemoryAllocationLib: Add MM memory allocation library.\n\nThis patch implements management mode memory allocation services.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/2c868eef731586de781adb96a1ce837de76c0dae"},{"sha":"70a51d7187de5b3c8e18c5582449e4ea680e3c2a","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg/HobLib: Add HOB Library for management mode.\n\nThe Standalone MM environment is initialized during the SEC phase on ARM\nStandard Platforms. The MM Core driver implements an entry point module\nwhich is architecture specific and runs prior to the generic core driver\ncode. The former creates a Hob list that the latter consumes. This\nhappens in the same phase.\n\nThis patch implements a Hob library that can be used by the entry point\nmodule to produce a Hob list and by the core driver code to consume it.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Achin Gupta <achin.gupta@arm.com>\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/70a51d7187de5b3c8e18c5582449e4ea680e3c2a"},{"sha":"0f4db639bb2a16a09a82f2b5b77a7c2aba7f8ae8","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg: MM driver entry point library.\n\nThis patch implements module entry point library for Standalone\nmanagement mode (MM) Drivers.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>\nReviewed-by: Jiewen Yao <Jiewen.yao@intel.com>\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/0f4db639bb2a16a09a82f2b5b77a7c2aba7f8ae8"},{"sha":"6b46d77243e02d23ce922803998e01277fe9f399","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg/Core: Implementation of Standalone MM Core Module.\n\nManagement Mode (MM) is a generic term used to describe a secure\nexecution environment provided by the CPU and related silicon that is\nentered when the CPU detects a MMI. For x86 systems, this can be\nimplemented with System Management Mode (SMM). For ARM systems, this can\nbe implemented with TrustZone (TZ).\nA MMI can be a CPU instruction or interrupt. Upon detection of a MMI, a\nCPU will jump to the MM Entry Point and save some portion of its state\n(the \"save state\") such that execution can be resumed.\nThe MMI can be generated synchronously by software or asynchronously by\na hardware event. Each MMI source can be detected, cleared and disabled.\nSome systems provide for special memory (Management Mode RAM or MMRAM)\nwhich is set aside for software running in MM. Usually the MMRAM is\nhidden during normal CPU execution, but this is not required. Usually,\nafter MMRAM is hidden it cannot be exposed until the next system reset.\n\nThe MM Core Interface Specification describes three pieces of the PI\nManagement Mode architecture:\n1. MM Dispatch\n   During DXE, the DXE Foundation works with the MM Foundation to\n   schedule MM drivers for execution in the discovered firmware volumes.\n2. MM Initialization\n   MM related code opens MMRAM, creates the MMRAM memory map, and\n   launches the MM Foundation, which provides the necessary services to\n   launch MM-related drivers. Then, sometime before boot, MMRAM is\n   closed and locked. This piece may be completed during the\n   SEC, PEI or DXE phases.\n3. MMI Management\n   When an MMI generated, the MM environment is created and then the MMI\n\n   sources are detected and MMI handlers called.\n\nThis patch implements the MM Core.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Jiewen Yao <jiewen.yao@intel.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/6b46d77243e02d23ce922803998e01277fe9f399"},{"sha":"184558d072dc8a76cb224205840605b512321e28","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg: Add an AArch64 specific entry point library.\n\nThe Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard\nPlatforms and is initialised during the SEC phase. ARM Trusted firmware\nin EL3 is responsible for initialising the architectural context for\nS-EL0 and loading the Standalone MM image. The memory allocated to this\nimage is marked as RO+X. Heap memory is marked as RW+XN.\n\nCertain actions have to be completed prior to executing the generic code\nin the Standalone MM Core module. These are:\n\n1. Memory permission attributes for each section of the Standalone MM\n   Core module need to be changed prior to accessing any RW data.\n\n2. A Hob list has to be created with information that allows the MM\n   environment to initialise and dispatch drivers.\n\nFurthermore, this module is responsible for handing over runtime MM\nevents to the Standalone MM CPU driver and returning control to ARM\nTrusted Firmware upon event completion. Hence it needs to know the CPU\ndriver entry point.\n\nThis patch implements an entry point module that ARM Trusted Firmware\njumps to in S-EL0. It then performs the above actions before calling the\nStandalone MM Foundation entry point and handling subsequent MM events.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>\nSigned-off-by: Achin Gupta <achin.gupta@arm.com>\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/184558d072dc8a76cb224205840605b512321e28"},{"sha":"275d4bd4399f7af6b905c310358da9305fbbc3e7","author":{"name":"Supreeth Venkatesh","email":"e636ad8a3c68a860c3594da0efc73a6a46c31f2f@arm.com"},"message":"StandaloneMmPkg: Add CPU driver suitable for ARM Platforms.\n\nThis patch adds a simple CPU driver that exports the\nEFI_MM_CONFIGURATION_PROTOCOL to allow registration of the Standalone\nMM Foundation entry point. It preserves the existing notification\nmechanism for the configuration protocol.\n\nContributed-under: TianoCore Contribution Agreement 1.1\nSigned-off-by: Sughosh Ganu <sughosh.ganu@arm.com>\nSigned-off-by: Achin Gupta <achin.gupta@arm.com>\nSigned-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>\nReviewed-by: Achin Gupta <achin.gupta@arm.com>","distinct":true,"url":"https://api.github.com/repos/warexify/edk2/commits/275d4bd4399f7af6b905c310358da9305fbbc3e7"}]}
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