{"push_id":3182741505,"size":68,"distinct_size":68,"ref":"refs/heads/master","head":"2c1f016e634bf79faf45e81c14c955c711bc202f","before":"d00dd9c2dd3f2e623f4db48d66d3b54b858842dd","commits":[{"sha":"66b5a4e9c4d7de79c9396cf5ed117a4e5cfcf386","author":{"name":"Philippe Waroquiers","email":"be6130e42bf08db18b2438a4f2a12b62b8acc0fc@skynet.be"},"message":"Fix 399301 - Use inlined frames in Massif XTree output.\n\nAuthor: Nicholas Nethercote <nnethercote@mozilla.com>\n\nUse inlined frames in Massif XTree output.\n\n    This makes Massif's output much easier to follow.\n\n    The commit also removes a -1 used on all Massif stack frame addresses.\n    There was a big comment questioning the presence of that -1, and with it\n    gone the addresses now match those produced by DHAT.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/66b5a4e9c4d7de79c9396cf5ed117a4e5cfcf386"},{"sha":"7820fc268fae4353118b6355f1d4b9e1b7eeebec","author":{"name":"Philippe Waroquiers","email":"be6130e42bf08db18b2438a4f2a12b62b8acc0fc@skynet.be"},"message":"Fix dependencies between libcoregrind*.a and *m_main.o/*m_libcsetjmp.o\n\nThe primary and secondary coregrind libraries must be updated\nwhen m_main.c or m_libcsetjmp.c are changed.\n\nA dependency was missing between libcoregrind*.a and libnolto_coregrind*.a,\nand so tools were not relinked when m_main.c or m_libcsetjmp.c were\nchanged.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/7820fc268fae4353118b6355f1d4b9e1b7eeebec"},{"sha":"8a6fe39d2a374f5cfffbd052467f35bf115797a4","author":{"name":"Philippe Waroquiers","email":"be6130e42bf08db18b2438a4f2a12b62b8acc0fc@skynet.be"},"message":"Make white space style more consistent, no functional impact.\n\nConsistently use a space between function name and function arg list.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/8a6fe39d2a374f5cfffbd052467f35bf115797a4"},{"sha":"1d42a625abd8b6d24186e6bda2b401ee24a118c4","author":{"name":"Philippe Waroquiers","email":"be6130e42bf08db18b2438a4f2a12b62b8acc0fc@skynet.be"},"message":"Make white space style more consistent, no functional impact.\n\nBut this time, rather consistently use *no* space between function name and\nfunction arg list.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/1d42a625abd8b6d24186e6bda2b401ee24a118c4"},{"sha":"71002d8a5111d02ce8049c55017a8d948c820e35","author":{"name":"Andreas Arnez","email":"b084e43d53a276329e0351a2aa437c439bfbe747@linux.ibm.com"},"message":"Bug 400490 s390x: Fix register allocation for VRs vs FPRs\n\nOn s390x, if vector registers are available, they are fed to the register\nallocator as if they were separate from the floating-point registers.  But\nin fact the FPRs are embedded in the VRs.  So for instance, if both f3 and\nv3 are allocated and used at the same time, corruption will result.\n\nThis is fixed by offering only the non-overlapping VRs, v16 to v31, to the\nregister allocator instead.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/71002d8a5111d02ce8049c55017a8d948c820e35"},{"sha":"9545e9f96beda6e9f2205bdb3c3e96edaf8d9e2b","author":{"name":"Andreas Arnez","email":"b084e43d53a276329e0351a2aa437c439bfbe747@linux.ibm.com"},"message":"Bug 400491 s390x: Sign-extend immediate operand of LOCHI and friends\n\nThe VEX implementation of each of the z/Architecture instructions LOCHI,\nLOCHHI, and LOCGHI treats the immediate 16-bit operand as an unsigned\ninteger instead of a signed integer.  This is fixed.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/9545e9f96beda6e9f2205bdb3c3e96edaf8d9e2b"},{"sha":"50bd2282bce101012a5668b670cb185375600d2d","author":{"name":"Andreas Arnez","email":"b084e43d53a276329e0351a2aa437c439bfbe747@linux.ibm.com"},"message":"Bug 397187 s390x: Add vector register support for vgdb\n\nOn s390x machines with a vector facility, Valgrind's gdbserver didn't\nrepresent the vector registers.  This is fixed.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/50bd2282bce101012a5668b670cb185375600d2d"},{"sha":"18d4bf8f0cbee0f47e35258b34e88a19c5da33fa","author":{"name":"Nicholas Nethercote","email":"ab5cc54e596b116de7a8f9daadb57d1970be9a4d@mozilla.com"},"message":"Fix Cachegrind's --help message.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/18d4bf8f0cbee0f47e35258b34e88a19c5da33fa"},{"sha":"7f1dd9d5aec1f1fd4eb0ae3a311358a914f1d73f","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"get_otrack_shadow_offset_wrk for ppc32 and ppc64: add missing cases for XER_OV32, XER_CA32 and C_FPCC.\n\nThe missing cases were discovered whilst testing fixes for bug 386945, but are\notherwise unrelated to that bug.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/7f1dd9d5aec1f1fd4eb0ae3a311358a914f1d73f"},{"sha":"4271989815b5fc933c1e29bc75507c2726dc3738","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"Add some new IROps to support improved Memcheck analysis of strlen etc.\n\nThis is part of the fix for bug 386945.  It adds the following IROps, plus\ntheir supporting type- and printing- fragments:\n\nIop_Reverse8sIn32_x1: 32-bit byteswap.  A fancy name, but it is consistent\nwith naming for the other swapping IROps that already exist.\n\nIop_PopCount64, Iop_PopCount32: population count\n\nIop_ClzNat64, Iop_ClzNat32, Iop_CtzNat64, Iop_CtzNat32: counting leading and\ntrailing zeroes, with \"natural\" (Nat) semantics for a zero input, meaning, in\nthe case of zero input, return the number of bits in the word.  These\nfunctionally overlap with the existing Iop_Clz64, Iop_Clz32, Iop_Ctz64,\nIop_Ctz32.  The existing operations are undefined in case of a zero input.\nAdding these new variants avoids the complexity of having to change the\ndeclared semantics of the existing operations.  Instead they are deprecated\nbut still available for use.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/4271989815b5fc933c1e29bc75507c2726dc3738"},{"sha":"97d336b79e36f6c99d8b07f49ebc9b780e6df84e","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"Add ppc host-side isel and instruction support for IROps added in previous commit.\n\nVEX/priv/host_ppc_defs.c, VEX/priv/host_ppc_defs.h:\n\nDont emit cnttz{w,d}.  We may need them on a target which doesn't support\nthem.  Instead we can generate a fairly reasonable alternative sequence with\ncntlz{w,d} instead.\n\nAdd support for emitting popcnt{w,d}.\n\nVEX/priv/host_ppc_isel.c\n\nAdd support for: Iop_ClzNat32 Iop_ClzNat64\n\nRedo support for: Iop_Ctz{32,64} and their Nat equivalents, so as to not use\ncnttz{w,d}, as mentioned above.\n\nAdd support for: Iop_PopCount64 Iop_PopCount32 Iop_Reverse8sIn32_x1","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/97d336b79e36f6c99d8b07f49ebc9b780e6df84e"},{"sha":"e221eca26be6b2396e3fcbf4117e630fc22e79f6","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"Add Memcheck support for IROps added in 42719898.\n\nmemcheck/mc_translate.c:\n\nAdd mkRight{32,64} as right-travelling analogues to mkLeft{32,64}.\n\ndoCmpORD: for the cases of a signed comparison against zero, compute\ndefinedness of the 3 result bits (lt,gt,eq) separately, and, for the lt and eq\nbits, do it exactly accurately.\n\nexpensiveCountTrailingZeroes: no functional change.  Re-analyse/verify and add\ncomments.\n\nexpensiveCountLeadingZeroes: add.  Very similar to\nexpensiveCountTrailingZeroes.\n\nAdd some comments to mark unary ops which are self-shadowing.\n\nRoute Iop_Ctz{,Nat}{32,64} through expensiveCountTrailingZeroes.\nRoute Iop_Clz{,Nat}{32,64} through expensiveCountLeadingZeroes.\n\nAdd instrumentation for Iop_PopCount{32,64} and Iop_Reverse8sIn32_x1.\n\nmemcheck/tests/vbit-test/irops.c\n\nAdd dummy new entries for all new IROps, just enough to make it compile and\nrun.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/e221eca26be6b2396e3fcbf4117e630fc22e79f6"},{"sha":"81d9832226d6e3d1ee78ee3133189d7b520e7eea","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"ppc front end: use new IROps added in 42719898.\n\nThis pertains to bug 386945.\n\nVEX/priv/guest_ppc_toIR.c:\n\ngen_POPCOUNT: use Iop_PopCount{32,64} where possible.\n\ngen_vpopcntd_mode32: use Iop_PopCount32.\n\nfor cntlz{w,d}, use Iop_CtzNat{32,64}.\n\ngen_byterev32: use Iop_Reverse8sIn32_x1 instead of lengthy sequence.\n\nverbose_Clz32: remove (was unused anyway).","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/81d9832226d6e3d1ee78ee3133189d7b520e7eea"},{"sha":"cb5d7e047598bff6d0f1d707a70d9fb1a1c7f0e2","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"VEX/priv/ir_opt.c\n\nfold_Expr: transform PopCount64(And64(Add64(x,-1),Not64(x))) into CtzNat64(x).\n\nThis is part of the fix for bug 386945.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/cb5d7e047598bff6d0f1d707a70d9fb1a1c7f0e2"},{"sha":"27fe22378da38424102c5292b782cacdd9d7b9e4","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"Add support for Iop_{Sar,Shr}8 on ppc.  --expensive-definedness-checks=yes needs them.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/27fe22378da38424102c5292b782cacdd9d7b9e4"},{"sha":"ddfc274b24a1ae3b57166ada1fe97acb433b9b79","author":{"name":"Andreas Arnez","email":"b084e43d53a276329e0351a2aa437c439bfbe747@linux.vnet.ibm.com"},"message":"s390x: More fixes for z13 support\n\nThis patch addresses the following:\n\n* Fix the implementation of LOCGHI.  Previously Valgrind performed 32-bit\n  sign extension instead of 64-bit sign extension on the immediate value.\n\n* Advertise VXRS in HWCAP.  If no VXRS are advertised, but the program\n  uses vector registers, this could cause problems with a glibc built with\n  \"-march=z13\".","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/ddfc274b24a1ae3b57166ada1fe97acb433b9b79"},{"sha":"7c26e71c096addf193502334c69b06abe3d86766","author":{"name":"Philippe Waroquiers","email":"be6130e42bf08db18b2438a4f2a12b62b8acc0fc@skynet.be"},"message":"Always output all leak kinds in a xtree leak result file.\n\n- The option --xtree-leak=yes (to output leak result in xtree format)\n  automatically activates the option --show-leak-kinds=all,\n  as xtree visualisation tools such as kcachegrind can in any case\n  select what kind of leak to visualise.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/7c26e71c096addf193502334c69b06abe3d86766"},{"sha":"f2c03ce3babe51eecbf03735f726c4028a162857","author":{"name":"Julian Seward","email":"ddfc93b89978d7702166fc4882790701017975d7@acm.org"},"message":"Bug 401112 - LLVM 5.0 generates comparison against partially initialized data.\n\nThis generalises the existing spec rules for W of 32 bits:\n\n             W  <u   0---(N-1)---0 1 0---0  or\n\n(that is, B/NB after SUBL, where dep2 has the above form), to also cover\n\n             W  <=u  0---(N-1)---0 0 1---1\n\n(that is, BE/NBE after SUBL, where dept2 has the specified form).\n\nPatch from Nicolas B. Pierron (nicolas.b.pierron@nbp.name).","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/f2c03ce3babe51eecbf03735f726c4028a162857"},{"sha":"600a0099a1eb2335a3f9563534c112e11817002b","author":{"name":"Vadim Barkov","email":"61bffb32366a7a75000ecfa082db7b959a0bcd5b@gmail.com"},"message":"Bug 385411 s390x: Add z13 vector floating point support\n\nThis adds support for the z/Architecture vector FP instructions that were\nintroduced with z13.\n\nThe patch was contributed by Vadim Barkov, with some clean-up and minor\nadjustments by Andreas Arnez.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/600a0099a1eb2335a3f9563534c112e11817002b"},{"sha":"86bd889458883295b73c36696ec64dea9338a7a3","author":{"name":"Vadim Barkov","email":"61bffb32366a7a75000ecfa082db7b959a0bcd5b@gmail.com"},"message":"Bug 385411 s390x: Tests and internals for z13 vector FP support\n\nAdd test cases for the z13 vector FP support.  Bring s390-opcodes.csv\nup-to-date, reflecting that the z13 vector instructions are now supported.\nAlso remove the non-support disclaimer for the vector facility from\nREADME.s390.\n\nThe patch was contributed by Vadim Barkov, with some clean-up and minor\nadjustments by Andreas Arnez.","distinct":true,"url":"https://api.github.com/repos/Echelon9/valgrind/commits/86bd889458883295b73c36696ec64dea9338a7a3"}]}
{"actor":{"display_login":"Echelon9"}}