{"action":"created","comment":{"url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/comments/226983758","pull_request_review_id":166798967,"id":226983758,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDIyNjk4Mzc1OA==","diff_hunk":"@@ -195,41 +195,639 @@ public static double InvSqrtEstimate(double x)\n             ulong result = x_sign | (result_exp << 52) | fraction;\n             return BitConverter.Int64BitsToDouble((long)result);\n         }\n+    }\n+\n+    static class ASoftFloat16_32\n+    {\n+        public static float FPConvert(ushort ValueBits, AThreadState State)\n+        {\n+            Debug.WriteLineIf(State.Fpcr != 0, $\"ASoftFloat16_32.FPConvert: State.Fpcr = 0x{State.Fpcr:X8}\");\n+\n+            double Real = ValueBits.FPUnpackCV(out FPType Type, out bool Sign, State);\n+\n+            float Result;\n+\n+            if (Type == FPType.SNaN || Type == FPType.QNaN)\n+            {\n+                if (State.GetFpcrFlag(FPCR.DN))\n+                {\n+                    Result = FPDefaultNaN();\n+                }\n+                else\n+                {\n+                    Result = FPConvertNaN(ValueBits);\n+                }\n+\n+                if (Type == FPType.SNaN)\n+                {\n+                    FPProcessException(FPExc.InvalidOp, State);\n+                }\n+            }\n+            else if (Type == FPType.Infinity)\n+            {\n+                Result = FPInfinity(Sign);\n+            }\n+            else if (Type == FPType.Zero)\n+            {\n+                Result = FPZero(Sign);\n+            }\n+            else\n+            {\n+                Result = FPRoundCV(Real, State);\n+            }\n+\n+            return Result;\n+        }\n+\n+        private enum FPType\n+        {\n+            Nonzero,\n+            Zero,\n+            Infinity,\n+            QNaN,\n+            SNaN\n+        }\n+\n+        private enum FPExc\n+        {\n+            InvalidOp,\n+            DivideByZero,\n+            Overflow,\n+            Underflow,\n+            Inexact,\n+            InputDenorm = 7\n+        }\n+\n+        private enum FPRounding\n+        {\n+            TIEEVEN,\n+            POSINF,\n+            NEGINF,\n+            ZERO\n+        };\n+\n+        private enum FPCR\n+        {\n+            UFE   = 11,\n+            RMode = 22,\n+            FZ    = 24,\n+            DN    = 25,\n+            AHP   = 26\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static float FPDefaultNaN()\n+        {\n+            return -float.NaN;\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static float FPInfinity(bool Sign)\n+        {\n+            return Sign ? float.NegativeInfinity : float.PositiveInfinity;\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static float FPZero(bool Sign)\n+        {\n+            return Sign ? -0f : +0f;\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static float FPMaxNormal(bool Sign)\n+        {\n+            return Sign ? float.MinValue : float.MaxValue;\n+        }\n+\n+        private static double FPUnpackCV(this ushort ValueBits, out FPType Type, out bool Sign, AThreadState State)\n+        {\n+            Sign = (~(uint)ValueBits & 0x8000u) == 0u;\n+\n+            uint Exp16  = ((uint)ValueBits & 0x7C00u) >> 10;\n+            uint Frac16 =  (uint)ValueBits & 0x03FFu;\n+\n+            double Real;\n+\n+            if (Exp16 == 0u)\n+            {\n+                if (Frac16 == 0u)\n+                {\n+                    Type = FPType.Zero;\n+                    Real = 0d;\n+                }\n+                else\n+                {\n+                    Type = FPType.Nonzero; // Subnormal.\n+                    Real = Math.Pow(2d, -14) * ((double)Frac16 * Math.Pow(2d, -10));\n+                }\n+            }\n+            else if (Exp16 == 0x1Fu && !State.GetFpcrFlag(FPCR.AHP))\n+            {\n+                if (Frac16 == 0u)\n+                {\n+                    Type = FPType.Infinity;\n+                    Real = Math.Pow(2d, 1000);\n+                }\n+                else\n+                {\n+                    Type = (~Frac16 & 0x0200u) == 0u ? FPType.QNaN : FPType.SNaN;\n+                    Real = 0d;\n+                }\n+            }\n+            else\n+            {\n+                Type = FPType.Nonzero; // Normal.\n+                Real = Math.Pow(2d, (int)Exp16 - 15) * (1d + (double)Frac16 * Math.Pow(2d, -10));\n+            }\n \n-        public static float ConvertHalfToSingle(ushort x)\n+            return Sign ? -Real : Real;\n+        }\n+\n+        private static float FPRoundCV(double Real, AThreadState State)\n         {\n-            uint x_sign = (uint)(x >> 15) & 0x0001;\n-            uint x_exp = (uint)(x >> 10) & 0x001F;\n-            uint x_mantissa = (uint)x & 0x03FF;\n+            const int UFCBit = 3;  // Underflow cumulative floating-point exception bit.\n+\n+            const int MinimumExp = -126;\n \n-            if (x_exp == 0 && x_mantissa == 0)\n+            const int E = 8;\n+            const int F = 23;\n+\n+            bool   Sign;\n+            double Mantissa;\n+\n+            if (Real < 0d)\n+            {\n+                Sign     = true;\n+                Mantissa = -Real;\n+            }\n+            else\n             {\n-                // Zero\n-                return BitConverter.Int32BitsToSingle((int)(x_sign << 31));\n+                Sign     = false;\n+                Mantissa = Real;\n             }\n \n-            if (x_exp == 0x1F)\n+            int Exponent = 0;\n+\n+            while (Mantissa < 1d)\n             {\n-                // NaN or Infinity\n-                return BitConverter.Int32BitsToSingle((int)((x_sign << 31) | 0x7F800000 | (x_mantissa << 13)));\n+                Mantissa *= 2d;\n+                Exponent--;\n             }\n \n-            int exponent = (int)x_exp - 15;\n+            while (Mantissa >= 2d)\n+            {\n+                Mantissa /= 2d;\n+                Exponent++;\n+            }\n \n-            if (x_exp == 0)\n+            if (State.GetFpcrFlag(FPCR.FZ) && Exponent < MinimumExp)\n             {\n-                // Denormal\n-                x_mantissa <<= 1;\n-                while ((x_mantissa & 0x0400) == 0)\n+                State.Fpsr |= 1 << UFCBit;\n+\n+                return FPZero(Sign);\n+            }\n+\n+            uint BiasedExp = (uint)Max(Exponent - MinimumExp + 1, 0);\n+            if (BiasedExp == 0u) Mantissa /= Math.Pow(2d, MinimumExp - Exponent);\n+\n+            uint IntMant = (uint)Math.Floor(Mantissa * Math.Pow(2d, F));\n+            double Error = Mantissa * Math.Pow(2d, F) - (double)IntMant;\n+\n+            if (BiasedExp == 0u && (Error != 0d || State.GetFpcrFlag(FPCR.UFE)))\n+            {\n+                FPProcessException(FPExc.Underflow, State);\n+            }\n+\n+            bool OverflowToInf;\n+            bool RoundUp;\n+\n+            switch (FPRoundingMode(State))\n+            {\n+                default:\n+                case FPRounding.TIEEVEN:\n+                    RoundUp       = (Error > 0.5d || (Error == 0.5d && (IntMant & 1u) == 1u));\n+                    OverflowToInf = true;\n+                    break;\n+\n+                case FPRounding.POSINF:\n+                    RoundUp       = (Error != 0d && !Sign);\n+                    OverflowToInf = !Sign;\n+                    break;\n+\n+                case FPRounding.NEGINF:\n+                    RoundUp       = (Error != 0d && Sign);\n+                    OverflowToInf = Sign;\n+                    break;\n+\n+                case FPRounding.ZERO:\n+                    RoundUp       = false;\n+                    OverflowToInf = false;\n+                    break;\n+            }\n+\n+            if (RoundUp)\n+            {\n+                IntMant++;\n+\n+                if (IntMant == (uint)Math.Pow(2d, F))\n+                {\n+                    BiasedExp = 1u;\n+                }\n+\n+                if (IntMant == (uint)Math.Pow(2d, F + 1))\n+                {\n+                    BiasedExp++;\n+                    IntMant >>= 1;\n+                }\n+            }\n+\n+            float Result;\n+\n+            if (BiasedExp >= (uint)Math.Pow(2d, E) - 1u)\n+            {\n+                Result = OverflowToInf ? FPInfinity(Sign) : FPMaxNormal(Sign);\n+\n+                FPProcessException(FPExc.Overflow, State);\n+\n+                Error = 1d;\n+            }\n+            else\n+            {\n+                Result = BitConverter.Int32BitsToSingle(\n+                    (int)((Sign ? 1u : 0u) << 31 | (BiasedExp & 0xFFu) << 23 | (IntMant & 0x007FFFFFu)));\n+            }\n+\n+            if (Error != 0d)\n+            {\n+                FPProcessException(FPExc.Inexact, State);\n+            }\n+\n+            return Result;\n+\n+            int Max(int Left, int Right) => Left >= Right ? Left : Right;\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static float FPConvertNaN(ushort ValueBits)\n+        {\n+            return BitConverter.Int32BitsToSingle(\n+                (int)(((uint)ValueBits & 0x8000u) << 16 | 0x7FC00000u | ((uint)ValueBits & 0x01FFu) << 13));\n+        }\n+\n+        private static void FPProcessException(FPExc Exc, AThreadState State)\n+        {\n+            int Enable = (int)Exc + 8;\n+\n+            if ((State.Fpcr & (1 << Enable)) != 0)\n+            {\n+                throw new NotImplementedException(\"floating-point trap handling\");\n+            }\n+            else\n+            {\n+                State.Fpsr |= 1 << (int)Exc;\n+            }\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static FPRounding FPRoundingMode(AThreadState State)\n+        {\n+            return (FPRounding)((State.Fpcr >> (int)FPCR.RMode) & 3);\n+        }\n+\n+        [MethodImpl(MethodImplOptions.AggressiveInlining)]\n+        private static bool GetFpcrFlag(this AThreadState State, FPCR Fpcr)\n+        {\n+            return (State.Fpcr & (1 << (int)Fpcr)) != 0;\n+        }\n+    }\n+\n+    static class ASoftFloat32_16\n+    {\n+        public static ushort FPConvert(float Value, AThreadState State)\n+        {\n+            Debug.WriteLineIf(State.Fpcr != 0, $\"ASoftFloat32_16.FPConvert: State.Fpcr = 0x{State.Fpcr:X8}\");\n+\n+            double Real = Value.FPUnpackCV(out FPType Type, out bool Sign, State, out uint ValueBits);\n+\n+            bool AltHp = State.GetFpcrFlag(FPCR.AHP);\n+\n+            ushort ResultBits;\n+\n+            if (Type == FPType.SNaN || Type == FPType.QNaN)\n+            {\n+                if (AltHp)\n+                {\n+                    ResultBits = FPZero(Sign);\n+                }\n+                else if (State.GetFpcrFlag(FPCR.DN))\n+                {\n+                    ResultBits = FPDefaultNaN();\n+                }\n+                else\n+                {\n+                    ResultBits = FPConvertNaN(ValueBits);\n+                }\n+\n+                if (Type == FPType.SNaN || AltHp)\n+                {\n+                    FPProcessException(FPExc.InvalidOp, State);\n+                }\n+            }\n+            else if (Type == FPType.Infinity)\n+            {\n+                if (AltHp)\n+                {\n+                    ResultBits = (ushort)((Sign ? 1u : 0u) << 15 | 0x7FFFu);\n+\n+                    FPProcessException(FPExc.InvalidOp, State);\n+                }\n+                else\n+                {\n+                    ResultBits = FPInfinity(Sign);\n+                }\n+            }\n+            else if (Type == FPType.Zero)\n+            {\n+                ResultBits = FPZero(Sign);\n+            }\n+            else\n+            {\n+                ResultBits = FPRoundCV(Real, State);\n+            }\n+\n+            return ResultBits;\n+        }\n+\n+        private enum FPType","path":"ChocolArm64/Instruction/ASoftFloat.cs","position":382,"original_position":382,"commit_id":"2f197cd40d516273ec44a7c0486951cdefe8826e","original_commit_id":"2f197cd40d516273ec44a7c0486951cdefe8826e","user":{"login":"gdkchan","id":5624669,"node_id":"MDQ6VXNlcjU2MjQ2Njk=","avatar_url":"https://avatars0.githubusercontent.com/u/5624669?v=4","gravatar_id":"","url":"https://api.github.com/users/gdkchan","html_url":"https://github.com/gdkchan","followers_url":"https://api.github.com/users/gdkchan/followers","following_url":"https://api.github.com/users/gdkchan/following{/other_user}","gists_url":"https://api.github.com/users/gdkchan/gists{/gist_id}","starred_url":"https://api.github.com/users/gdkchan/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/gdkchan/subscriptions","organizations_url":"https://api.github.com/users/gdkchan/orgs","repos_url":"https://api.github.com/users/gdkchan/repos","events_url":"https://api.github.com/users/gdkchan/events{/privacy}","received_events_url":"https://api.github.com/users/gdkchan/received_events","type":"User","site_admin":false},"body":"We shouldn't need to repeat those on every class. My suggestion is moving those enums to ChocolArm64.State, each one on a separate file.","created_at":"2018-10-22T13:14:35Z","updated_at":"2018-10-22T13:23:00Z","html_url":"https://github.com/Ryujinx/Ryujinx/pull/468#discussion_r226983758","pull_request_url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/468","author_association":"MEMBER","_links":{"self":{"href":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/comments/226983758"},"html":{"href":"https://github.com/Ryujinx/Ryujinx/pull/468#discussion_r226983758"},"pull_request":{"href":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/468"}}},"pull_request":{"url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/468","id":224555766,"node_id":"MDExOlB1bGxSZXF1ZXN0MjI0NTU1NzY2","html_url":"https://github.com/Ryujinx/Ryujinx/pull/468","diff_url":"https://github.com/Ryujinx/Ryujinx/pull/468.diff","patch_url":"https://github.com/Ryujinx/Ryujinx/pull/468.patch","issue_url":"https://api.github.com/repos/Ryujinx/Ryujinx/issues/468","number":468,"state":"open","locked":false,"title":"Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests.","user":{"login":"LDj3SNuD","id":35856442,"node_id":"MDQ6VXNlcjM1ODU2NDQy","avatar_url":"https://avatars3.githubusercontent.com/u/35856442?v=4","gravatar_id":"","url":"https://api.github.com/users/LDj3SNuD","html_url":"https://github.com/LDj3SNuD","followers_url":"https://api.github.com/users/LDj3SNuD/followers","following_url":"https://api.github.com/users/LDj3SNuD/following{/other_user}","gists_url":"https://api.github.com/users/LDj3SNuD/gists{/gist_id}","starred_url":"https://api.github.com/users/LDj3SNuD/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/LDj3SNuD/subscriptions","organizations_url":"https://api.github.com/users/LDj3SNuD/orgs","repos_url":"https://api.github.com/users/LDj3SNuD/repos","events_url":"https://api.github.com/users/LDj3SNuD/events{/privacy}","received_events_url":"https://api.github.com/users/LDj3SNuD/received_events","type":"User","site_admin":false},"body":"","created_at":"2018-10-21T17:20:13Z","updated_at":"2018-10-22T13:22:59Z","closed_at":null,"merged_at":null,"merge_commit_sha":"718ca8b938bc30fbb7959577b0d1d9a1c35285b0","assignee":null,"assignees":[],"requested_reviewers":[],"requested_teams":[],"labels":[{"id":826894430,"node_id":"MDU6TGFiZWw4MjY4OTQ0MzA=","url":"https://api.github.com/repos/Ryujinx/Ryujinx/labels/cpu","name":"cpu","color":"cfd3d7","default":false}],"milestone":null,"commits_url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/468/commits","review_comments_url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/468/comments","review_comment_url":"https://api.github.com/repos/Ryujinx/Ryujinx/pulls/comments{/number}","comments_url":"https://api.github.com/repos/Ryujinx/Ryujinx/issues/468/comments","statuses_url":"https://api.github.com/repos/Ryujinx/Ryujinx/statuses/2f197cd40d516273ec44a7c0486951cdefe8826e","head":{"label":"LDj3SNuD:master","ref":"master","sha":"2f197cd40d516273ec44a7c0486951cdefe8826e","user":{"login":"LDj3SNuD","id":35856442,"node_id":"MDQ6VXNlcjM1ODU2NDQy","avatar_url":"https://avatars3.githubusercontent.com/u/35856442?v=4","gravatar_id":"","url":"https://api.github.com/users/LDj3SNuD","html_url":"https://github.com/LDj3SNuD","followers_url":"https://api.github.com/users/LDj3SNuD/followers","following_url":"https://api.github.com/users/LDj3SNuD/following{/other_user}","gists_url":"https://api.github.com/users/LDj3SNuD/gists{/gist_id}","starred_url":"https://api.github.com/users/LDj3SNuD/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/LDj3SNuD/subscriptions","organizations_url":"https://api.github.com/users/LDj3SNuD/orgs","repos_url":"https://api.github.com/users/LDj3SNuD/repos","events_url":"https://api.github.com/users/LDj3SNuD/events{/privacy}","received_events_url":"https://api.github.com/users/LDj3SNuD/received_events","type":"User","site_admin":false},"repo":{"id":154033008,"node_id":"MDEwOlJlcG9zaXRvcnkxNTQwMzMwMDg=","name":"Ryujinx","full_name":"LDj3SNuD/Ryujinx","private":false,"owner":{"login":"LDj3SNuD","id":35856442,"node_id":"MDQ6VXNlcjM1ODU2NDQy","avatar_url":"https://avatars3.githubusercontent.com/u/35856442?v=4","gravatar_id":"","url":"https://api.github.com/users/LDj3SNuD","html_url":"https://github.com/LDj3SNuD","followers_url":"https://api.github.com/users/LDj3SNuD/followers","following_url":"https://api.github.com/users/LDj3SNuD/following{/other_user}","gists_url":"https://api.github.com/users/LDj3SNuD/gists{/gist_id}","starred_url":"https://api.github.com/users/LDj3SNuD/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/LDj3SNuD/subscriptions","organizations_url":"https://api.github.com/users/LDj3SNuD/orgs","repos_url":"https://api.github.com/users/LDj3SNuD/repos","events_url":"https://api.github.com/users/LDj3SNuD/events{/privacy}","received_events_url":"https://api.github.com/users/LDj3SNuD/received_events","type":"User","site_admin":false},"html_url":"https://github.com/LDj3SNuD/Ryujinx","description":"Experimental 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