{"push_id":3180958776,"size":1,"distinct_size":1,"ref":"refs/heads/active-devel","head":"ff8cf64323279dd3e3a1700059bc7b0f1f766c61","before":"dc62a9680ca7eb94c80d81557ee925f39336d3a4","commits":[{"sha":"ff8cf64323279dd3e3a1700059bc7b0f1f766c61","author":{"name":"db4ple","email":"348273f5291666148e1624a4ffc0e529d1844487@github.com"},"message":"Enabled 32bit ADC/DAC sample transfers\n\nWe now run the codec(s) with their full data width (24bits)\n(transfer size 32bit I2S data). Purpose is to have a little more margin\nif your frontend does not deliver high enough IQ levels. It may or may\nnot improve the reception. It has almost no effect on performance since\nwe, as before, run most of the processing with floating point math.\nA little extra work is on the DMA and SAI hardware (transfer amount doubled.\nAnd a little conversion is necessary for now.\n\nOn platforms with 2 codecs you can select AUDIO and IQ bit width (16/32)\nin any combination, on single codec devices (mcHF)\nboth have to be identical.\n\nOn STM32F4 we have an ugly hack to fix our inability to get proper 32bit via\nDMA. The current approach is required for a working solution\nas we have issues when working on the DMA buffers directly for swapping (we have to fix the\nMPU config for that to work, I guess)\n\nRAM usage grows by 0.5 (mcHF) to 1k (OVI40).\nUSB I/O still uses only 16bits (also for IQ data).\nAudio driver load does not increase measurably.","distinct":true,"url":"https://api.github.com/repos/db4ple/UHSDR/commits/ff8cf64323279dd3e3a1700059bc7b0f1f766c61"}]}
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