{"push_id":2616223978,"size":35,"distinct_size":35,"ref":"refs/heads/xprise-clang","head":"f332b02939055b5952f4216ea15a051239e6d0d5","before":"0f3eddbfb774985eb5758f8a463a4818b7b8f199","commits":[{"sha":"c8e086ea90db6434b7e89bae86b403db725cf8b3","author":{"name":"Riley Andrews","email":"11e4191b1ae5cae13d3da02c22f40620ad984fdf@google.com"},"message":"arm64: crypto: Change priority of arm64 aes cipher.\n\n(cherry pick from commit d802476e8db2eb616d47d0a06310276532cc2ffa)\n\nChange-Id: I0c614e0eca71b65945ff8bd17c65b03a02918b18\nSigned-off-by: Riley Andrews <riandrews@google.com>\nSigned-off-by: Mark Salyzyn <salyzyn@google.com>\nBug: 23181629","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/c8e086ea90db6434b7e89bae86b403db725cf8b3"},{"sha":"53a985b8c094cca353b8b6bbc98dd8166243f6a0","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"arm64/crypto: use crypto instructions to generate AES key schedule\n\n(cherry pick from commit 12ac3efe74f888a13cb4df88b38bb01e8034dea8)\n\nThis patch implements the AES key schedule generation using ARMv8\nCrypto Instructions. It replaces the table based C implementation\nin aes_generic.ko, which means we can drop the dependency on that\nmodule.\n\nTested-by: Steve Capper <steve.capper@linaro.org>\nAcked-by: Steve Capper <steve.capper@linaro.org>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Mark Salyzyn <salyzyn@google.com>\nBug: 23181629","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/53a985b8c094cca353b8b6bbc98dd8166243f6a0"},{"sha":"3b10a5ac38b78a165ecdd1be538dfc21c523de26","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"arm64: crypto: increase AES interleave to 4x\n\nThis patch increases the interleave factor for parallel AES modes\nto 4x. This improves performance on Cortex-A57 by ~35%. This is\ndue to the 3-cycle latency of AES instructions on the A57's\nrelatively deep pipeline (compared to Cortex-A53 where the AES\ninstruction latency is only 2 cycles).\n\nAt the same time, disable inline expansion of the core AES functions,\nas the performance benefit of this feature is negligible.\n\n  Measured on AMD Seattle (using tcrypt.ko mode=500 sec=1):\n\n  Baseline (2x interleave, inline expansion)\n  ------------------------------------------\n  testing speed of async cbc(aes) (cbc-aes-ce) decryption\n  test 4 (128 bit key, 8192 byte blocks): 95545 operations in 1 seconds\n  test 14 (256 bit key, 8192 byte blocks): 68496 operations in 1 seconds\n\n  This patch (4x interleave, no inline expansion)\n  -----------------------------------------------\n  testing speed of async cbc(aes) (cbc-aes-ce) decryption\n  test 4 (128 bit key, 8192 byte blocks): 124735 operations in 1 seconds\n  test 14 (256 bit key, 8192 byte blocks): 92328 operations in 1 seconds\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/3b10a5ac38b78a165ecdd1be538dfc21c523de26"},{"sha":"b03e61f8c8ebca4eb32670cb9c2c742913720b77","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"arm64/crypto: issue aese/aesmc instructions in pairs\n\nThis changes the AES core transform implementations to issue aese/aesmc\n(and aesd/aesimc) in pairs. This enables a micro-architectural optimization\nin recent Cortex-A5x cores that improves performance by 50-90%.\n\nMeasured performance in cycles per byte (Cortex-A57):\n\n                CBC enc         CBC dec         CTR\n  before        3.64            1.34            1.32\n  after         1.95            0.85            0.93\n\nNote that this results in a ~5% performance decrease for older cores.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/b03e61f8c8ebca4eb32670cb9c2c742913720b77"},{"sha":"fe17ccb397592269cc36bb401b78f2c3d1e9bbcf","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha1-ce - move SHA-1 ARMv8 implementation to base layer\n\nThis removes all the boilerplate from the existing implementation,\nand replaces it with calls into the base layer.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/fe17ccb397592269cc36bb401b78f2c3d1e9bbcf"},{"sha":"e9c6501f265ff466a887c96fd6eecdb0abdb27ae","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha2-ce - move SHA-224/256 ARMv8 implementation to base layer\n\nThis removes all the boilerplate from the existing implementation,\nand replaces it with calls into the base layer.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/e9c6501f265ff466a887c96fd6eecdb0abdb27ae"},{"sha":"1d98742a889c5734bc44d4a7516bf87847ea4728","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha1-ce - prevent asm code finalization in final() path\n\nEnsure that the asm code finalization path is not triggered when\ninvoked via final(), since it already takes care of that itself.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/1d98742a889c5734bc44d4a7516bf87847ea4728"},{"sha":"df42da05e5d3a10aab01a0a103ee3f76e94ca52a","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha2-ce - prevent asm code finalization in final() path\n\nEnsure that the asm code finalization path is not triggered when\ninvoked via final(), since it already takes care of that itself.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/df42da05e5d3a10aab01a0a103ee3f76e94ca52a"},{"sha":"1b0311bcc47223c077d87a8164159d21ce23febc","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"arm64: crypto: reduce priority of core AES cipher\n\nThe asynchronous, merged implementations of AES in CBC, CTR and XTS\nmodes are preferred when available (i.e., when instantiating ablkciphers\nexplicitly). However, the synchronous core AES cipher combined with the\ngeneric CBC mode implementation will produce a 'cbc(aes)' blkcipher that\nis callable asynchronously as well. To prevent this implementation from\nbeing used when the accelerated asynchronous implemenation is also\navailable, lower its priority to 250 (i.e., below the asynchronous\nmodule's priority of 300).\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/1b0311bcc47223c077d87a8164159d21ce23febc"},{"sha":"931b8cf0c8faed580f726d742f092d723420f290","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha1 - implement base layer for SHA-1\n\nTo reduce the number of copies of boilerplate code throughout\nthe tree, this patch implements generic glue for the SHA-1\nalgorithm. This allows a specific arch or hardware implementation\nto only implement the special handling that it needs.\n\nThe users need to supply an implementation of\n\n  void (sha1_block_fn)(struct sha1_state *sst, u8 const *src, int blocks)\n\nand pass it to the SHA-1 base functions. For easy casting between the\nprototype above and existing block functions that take a 'u32 state[]'\nas their first argument, the 'state' member of struct sha1_state is\nmoved to the base of the struct.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\nSigned-off-by: Francisco Franco <franciscofranco.1990@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/931b8cf0c8faed580f726d742f092d723420f290"},{"sha":"3d9e60f916eaf82955215b34dd06004a44c21498","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha256 - implement base layer for SHA-256\n\nTo reduce the number of copies of boilerplate code throughout\nthe tree, this patch implements generic glue for the SHA-256\nalgorithm. This allows a specific arch or hardware implementation\nto only implement the special handling that it needs.\n\nThe users need to supply an implementation of\n\n  void (sha256_block_fn)(struct sha256_state *sst, u8 const *src, int blocks)\n\nand pass it to the SHA-256 base functions. For easy casting between the\nprototype above and existing block functions that take a 'u32 state[]'\nas their first argument, the 'state' member of struct sha256_state is\nmoved to the base of the struct.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\nSigned-off-by: Francisco Franco <franciscofranco.1990@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/3d9e60f916eaf82955215b34dd06004a44c21498"},{"sha":"f8b9e1b80309cf4ec3bdb36fab5c187bb1299dd9","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha512 - implement base layer for SHA-512\n\nTo reduce the number of copies of boilerplate code throughout\nthe tree, this patch implements generic glue for the SHA-512\nalgorithm. This allows a specific arch or hardware implementation\nto only implement the special handling that it needs.\n\nThe users need to supply an implementation of\n\n  void (sha512_block_fn)(struct sha512_state *sst, u8 const *src, int blocks)\n\nand pass it to the SHA-512 base functions. For easy casting between the\nprototype above and existing block functions that take a 'u64 state[]'\nas their first argument, the 'state' member of struct sha512_state is\nmoved to the base of the struct.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\nSigned-off-by: Francisco Franco <franciscofranco.1990@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/f8b9e1b80309cf4ec3bdb36fab5c187bb1299dd9"},{"sha":"9c5b2612b58e7548655dcf25e1d8f733d7cd6964","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha1-generic - move to generic glue implementation\n\nThis updated the generic SHA-1 implementation to use the generic\nshared SHA-1 glue code.\n\nIt also implements a .finup hook crypto_sha1_finup() and exports\nit to other modules. The import and export() functions and the\n.statesize member are dropped, since the default implementation\nis perfectly suitable for this module.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/9c5b2612b58e7548655dcf25e1d8f733d7cd6964"},{"sha":"7a52bfe056ff409b837adbce2e4f891a9f51c15d","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha256-generic - move to generic glue implementation\n\nThis updates the generic SHA-256 implementation to use the\nnew shared SHA-256 glue code.\n\nIt also implements a .finup hook crypto_sha256_finup() and exports\nit to other modules. The import and export() functions and the\n.statesize member are dropped, since the default implementation\nis perfectly suitable for this module.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/7a52bfe056ff409b837adbce2e4f891a9f51c15d"},{"sha":"fe15db3c2c8293800f6a4422cbc1bafea518418a","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: sha512-generic - move to generic glue implementation\n\nThis updated the generic SHA-512 implementation to use the\ngeneric shared SHA-512 glue code.\n\nIt also implements a .finup hook crypto_sha512_finup() and exports\nit to other modules. The import and export() functions and the\n.statesize member are dropped, since the default implementation\nis perfectly suitable for this module.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/fe15db3c2c8293800f6a4422cbc1bafea518418a"},{"sha":"24bdd332151c020629f2899766eb6281951b2992","author":{"name":"Jeremy Linton","email":"5fd20647ba5fc84c5334ca74068125bbbd19ac4e@arm.com"},"message":"UPSTREAM: arm/arm64: crypto: assure that ECB modes don't require an IV\n\nECB modes don't use an initialization vector. The kernel\n/proc/crypto interface doesn't reflect this properly.\n\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Jeremy Linton <jeremy.linton@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\n(cherry picked from bee038a4bd2efe8188cc80dfdad706a9abe568ad)\nSigned-off-by: Eric Biggers <ebiggers@google.com>\nChange-Id: Ief9558d2b41be58a2d845d2033a141b5ef7b585f","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/24bdd332151c020629f2899766eb6281951b2992"},{"sha":"a751f4b2b96f88abd1856e9d5303de189a601717","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512\n\nThis integrates both the accelerated scalar and the NEON implementations\nof SHA-224/256 as well as SHA-384/512 from the OpenSSL project.\n\nRelative performance compared to the respective generic C versions:\n\n                 |  SHA256-scalar  | SHA256-NEON* |  SHA512  |\n     ------------+-----------------+--------------+----------+\n     Cortex-A53  |      1.63x      |     1.63x    |   2.34x  |\n     Cortex-A57  |      1.43x      |     1.59x    |   1.95x  |\n     Cortex-A73  |      1.26x      |     1.56x    |     ?    |\n\nThe core crypto code was authored by Andy Polyakov of the OpenSSL\nproject, in collaboration with whom the upstream code was adapted so\nthat this module can be built from the same version of sha512-armv8.pl.\n\nThe version in this patch was taken from OpenSSL commit 32bbb62ea634\n(\"sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.\")\n\n* The core SHA algorithm is fundamentally sequential, but there is a\n  secondary transformation involved, called the schedule update, which\n  can be performed independently. The NEON version of SHA-224/SHA-256\n  only implements this part of the algorithm using NEON instructions,\n  the sequential part is always done using scalar instructions.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/a751f4b2b96f88abd1856e9d5303de189a601717"},{"sha":"2ce4174371f963c1f91a55075956d8912bcf94f9","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/sha2 - add generated .S files to .gitignore\n\nAdd the files that are generated by the recently merged OpenSSL\nSHA-256/512 implementation to .gitignore so Git disregards them\nwhen showing untracked files.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/2ce4174371f963c1f91a55075956d8912bcf94f9"},{"sha":"78ddf5f3525cb7d62ff09230b7ced20d4ab16135","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/crct10dif - port x86 SSE implementation to arm64\n\nThis is a transliteration of the Intel algorithm implemented\nusing SSE and PCLMULQDQ instructions that resides in the file\narch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only\noperate on buffers that are 16 byte aligned (but of any size)\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/78ddf5f3525cb7d62ff09230b7ced20d4ab16135"},{"sha":"1cc71546eeca7545a5e639f8b04b708fa5da40f7","author":{"name":"Ard Biesheuvel","email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org"},"message":"crypto: arm64/crc32 - accelerated support based on x86 SSE implementation\n\nThis is a combination of the the Intel algorithm implemented using SSE\nand PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and\nthe new CRC32 extensions introduced for both 32-bit and 64-bit ARM in\nversion 8 of the architecture. Two versions of the above combo are\nprovided, one for CRC32 and one for CRC32C.\n\nThe PMULL/NEON algorithm is faster, but operates on blocks of at least\n64 bytes, and on multiples of 16 bytes only. For the remaining input,\nor for all input on systems that lack the PMULL 64x64->128 instructions,\nthe CRC32 instructions will be used.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Haseo97/kernel_xiaomi_vince/commits/1cc71546eeca7545a5e639f8b04b708fa5da40f7"}]}
{"actor":{"display_login":"Haseo97"}}