{"push_id":2494184556,"size":21,"distinct_size":0,"ref":"refs/heads/master","head":"a27fc14219f2e3c4a46ba9177b04d9b52c875532","before":"60cc43fc888428bb2f18f08997432d426a243338","commits":[{"sha":"ff2969c479d97c6221a9835ee0ab4c44513badc6","author":{"name":"Tomer Maimon","email":"a00679c30ec7148c6c650c8a7e373936dfd8d2b8@gmail.com"},"message":"dt-binding: timer: document NPCM7xx timer DT bindings\n\nAdded device tree binding documentation for Nuvoton NPCM7xx timer.\n\nSigned-off-by: Tomer Maimon <tmaimon77@gmail.com>\nAcked-by: Rob Herring <robh@kernel.org>\nReviewed-by: Brendan Higgins <brendanhiggins@google.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/ff2969c479d97c6221a9835ee0ab4c44513badc6"},{"sha":"1c00289ecd12471ba9733e61aaf1d39883a77b16","author":{"name":"Tomer Maimon","email":"a00679c30ec7148c6c650c8a7e373936dfd8d2b8@gmail.com"},"message":"clocksource/drivers/npcm: Add NPCM7xx timer driver\n\nAdd Nuvoton BMC NPCM7xx timer driver.\n\nThe clocksource Enable 24-bit TIMER0 and TIMER1 counters,\nwhile TIMER0 serve as clockevent and TIMER1 serve as clocksource.\n\nSigned-off-by: Tomer Maimon <tmaimon77@gmail.com>\nReviewed-by: Brendan Higgins <brendanhiggins@xxxxxxxxxx>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/1c00289ecd12471ba9733e61aaf1d39883a77b16"},{"sha":"cc01456a0d9a3cbfec85cf23f2ce53323e8fc973","author":{"name":"Anson Huang","email":"4d6e5019b57e6819e5be9063452c1647eb43e037@nxp.com"},"message":"dt-bindings: timer: tpm: fix typo of clock name\n\nThe clock name should be ipg instead of igp.\n\nSigned-off-by: Anson Huang <Anson.Huang@nxp.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/cc01456a0d9a3cbfec85cf23f2ce53323e8fc973"},{"sha":"16328e7bd428937f557a984d8b3378387c17a930","author":{"name":"Anson Huang","email":"4d6e5019b57e6819e5be9063452c1647eb43e037@nxp.com"},"message":"clocksource/drivers/imx-tpm: Fix typo of clock name\n\nThe clock name should be ipg instead of igp.\n\nSigned-off-by: Anson Huang <Anson.Huang@nxp.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/16328e7bd428937f557a984d8b3378387c17a930"},{"sha":"506a7be93ff773d5d4cf75a59f342865605b4910","author":{"name":"Anson Huang","email":"4d6e5019b57e6819e5be9063452c1647eb43e037@nxp.com"},"message":"clocksource/drivers/imx-tpm: Correct some registers operation flow\n\nAccording to i.MX7ULP reference manual, TPM_SC_CPWMS can ONLY be written when\ncounter is disabled, TPM_SC_TOF is write-1-clear, TPM_C0SC_CHF is also\nwrite-1-clear, correct these registers initialization flow;\n\nSigned-off-by: Anson Huang <Anson.Huang@nxp.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/506a7be93ff773d5d4cf75a59f342865605b4910"},{"sha":"0136c741ff40e03323419feec05fcd594f36a463","author":{"name":"Anson Huang","email":"4d6e5019b57e6819e5be9063452c1647eb43e037@nxp.com"},"message":"clocksource/drivers/imx-tpm: Add different counter width support\n\nDifferent TPM modules have different width counters which is 16-bit or 32-bit,\nthe counter width can be read from TPM_PARAM register bit[23:16], this patch\nadds dynamic check for counter width to support both 16-bit and 32-bit TPM\nmodules.\n\nSigned-off-by: Anson Huang <Anson.Huang@nxp.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/0136c741ff40e03323419feec05fcd594f36a463"},{"sha":"90c7c0c24e2232bbc74c6752c67bf1dfc6b4ced1","author":{"name":"Thomas Gleixner","email":"00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de"},"message":"Merge branch 'clockevents/4.17' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core\n\nPull clockevent updates from Daniel Lezcano:\n\n - Fix timer name and register flow for imx's timer tmp and handle\n   different counter width (Anson Huang)\n\n - Add the NPCM7xx timer support (Tomer Maimon)","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/90c7c0c24e2232bbc74c6752c67bf1dfc6b4ced1"},{"sha":"386c6ddbda180676b7d9fc375d54a7bdd353d39e","author":{"name":"KarimAllah Ahmed","email":"558cc378579f2fcab9c4d24e2576c3762d4edbef@amazon.de"},"message":"X86/VMX: Disable VMX preemption timer if MWAIT is not intercepted\n\nThe VMX-preemption timer is used by KVM as a way to set deadlines for the\nguest (i.e. timer emulation). That was safe till very recently when\ncapability KVM_X86_DISABLE_EXITS_MWAIT to disable intercepting MWAIT was\nintroduced. According to Intel SDM 25.5.1:\n\n\"\"\"\nThe VMX-preemption timer operates in the C-states C0, C1, and C2; it also\noperates in the shutdown and wait-for-SIPI states. If the timer counts down\nto zero in any state other than the wait-for SIPI state, the logical\nprocessor transitions to the C0 C-state and causes a VM exit; the timer\ndoes not cause a VM exit if it counts down to zero in the wait-for-SIPI\nstate. The timer is not decremented in C-states deeper than C2.\n\"\"\"\n\nNow once the guest issues the MWAIT with a c-state deeper than\nC2 the preemption timer will never wake it up again since it stopped\nticking! Usually this is compensated by other activities in the system that\nwould wake the core from the deep C-state (and cause a VMExit). For\nexample, if the host itself is ticking or it received interrupts, etc!\n\nSo disable the VMX-preemption timer if MWAIT is exposed to the guest!\n\nCc: Paolo Bonzini <pbonzini@redhat.com>\nCc: Radim Krčmář <rkrcmar@redhat.com>\nCc: kvm@vger.kernel.org\nSigned-off-by: KarimAllah Ahmed <karahmed@amazon.de>\nFixes: 4d5422cea3b61f158d58924cbb43feada456ba5c\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/386c6ddbda180676b7d9fc375d54a7bdd353d39e"},{"sha":"4d5f26ee310237552a36aa14ceee96d6659153cd","author":{"name":"Colin Ian King","email":"d100aa70785e45ee8deab668147d941941915c21@canonical.com"},"message":"kvm: selftests: fix spelling mistake: \"divisable\" and \"divisible\"\n\nTrivial fix to spelling mistakes in comment and message text\n\nSigned-off-by: Colin Ian King <colin.king@canonical.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/4d5f26ee310237552a36aa14ceee96d6659153cd"},{"sha":"8e9b29b61851ba452e33373743fadb52778e9075","author":{"name":"KarimAllah Ahmed","email":"558cc378579f2fcab9c4d24e2576c3762d4edbef@amazon.de"},"message":"X86/KVM: Do not allow DISABLE_EXITS_MWAIT when LAPIC ARAT is not available\n\nIf the processor does not have an \"Always Running APIC Timer\" (aka ARAT),\nwe should not give guests direct access to MWAIT. The LAPIC timer would\nstop ticking in deep C-states, so any host deadlines would not wakeup the\nhost kernel.\n\nThe host kernel intel_idle driver handles this by switching to broadcast\nmode when ARAT is not available and MWAIT is issued with a deep C-state\nthat would stop the LAPIC timer. When MWAIT is passed through, we can not\ntell when MWAIT is issued.\n\nSo just disable this capability when LAPIC ARAT is not available. I am not\neven sure if there are any CPUs with VMX support but no LAPIC ARAT or not.\n\nCc: Paolo Bonzini <pbonzini@redhat.com>\nCc: Radim Krčmář <rkrcmar@redhat.com>\nReported-by: Wanpeng Li <kernellwp@gmail.com>\nSigned-off-by: KarimAllah Ahmed <karahmed@amazon.de>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/8e9b29b61851ba452e33373743fadb52778e9075"},{"sha":"2698d82e519413c6ad287e6f14b29e0373ed37f8","author":{"name":"hu huajun","email":"b4d8c45c1ec8b8ae96181ce0dbb9cfdfd37b8d24@linux.alibaba.com"},"message":"KVM: X86: fix incorrect reference of trace_kvm_pi_irte_update\n\nIn arch/x86/kvm/trace.h, this function is declared as host_irq the\nfirst input, and vcpu_id the second, instead of otherwise.\n\nSigned-off-by: hu huajun <huhuajun@linux.alibaba.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/2698d82e519413c6ad287e6f14b29e0373ed37f8"},{"sha":"f0f4cf5b306620282db0c59ff963012e1973e025","author":{"name":"Krish Sadhukhan","email":"5dfdd34eb2d2c95b216f4788d0d55a5c8821ebfa@oracle.com"},"message":"x86: Add check for APIC access address for vmentry of L2 guests\n\nAccording to the sub-section titled 'VM-Execution Control Fields' in the\nsection titled 'Basic VM-Entry Checks' in Intel SDM vol. 3C, the following\nvmentry check must be enforced:\n\n    If the 'virtualize APIC-accesses' VM-execution control is 1, the\n    APIC-access address must satisfy the following checks:\n\n\t- Bits 11:0 of the address must be 0.\n\t- The address should not set any bits beyond the processor's\n\t  physical-address width.\n\nThis patch adds the necessary check to conform to this rule. If the check\nfails, we cause the L2 VMENTRY to fail which is what the associated unit\ntest (following patch) expects.\n\nReviewed-by: Mihai Carabas <mihai.carabas@oracle.com>\nReviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>\nReviewed-by: Jim Mattson <jmattson@google.com>\nReviewed-by: Wanpeng Li <wanpengli@tencent.com>\nSigned-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/f0f4cf5b306620282db0c59ff963012e1973e025"},{"sha":"4e1acd7b31a03f24cc6108d37d005e6b1d48c5d3","author":{"name":"Peng Hao","email":"8c0002d22ae9f34a326723c818121ff67611b65b@zte.com.cn"},"message":"kvm: selftests: add -std=gnu99 cflags\n\nlib/kvm_util.c: In function ‘kvm_memcmp_hva_gva’:\nlib/kvm_util.c:332:2: error: ‘for’ loop initial declarations are only allowed in C99 mode\n\nSo add -std=gnu99 to CFLAGS\n\nSigned-off-by: Peng Hao <peng.hao2@zte.com.cn>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/4e1acd7b31a03f24cc6108d37d005e6b1d48c5d3"},{"sha":"c7cd882469fc5042a5c84122b4062d7f53076db7","author":{"name":"Helge Deller","email":"5b1e7895819cf7d6bc77091b09bbfd6d330a4e74@gmx.de"},"message":"parisc: Fix missing binfmt_elf32.o build error\n\nCommit 71d577db01a5 (\"parisc: Switch to generic COMPAT_BINFMT_ELF\")\nremoved the binfmt_elf32.c source file, but missed to drop the object\nfile from the list of object files the Makefile, which then results in a\nbuild error.\n\nFixes: 71d577db01a5 (\"parisc: Switch to generic COMPAT_BINFMT_ELF\")\nReported-by: Guenter Roeck <linux@roeck-us.net>\nTested-by: Guenter Roeck <linux@roeck-us.net>\nSigned-off-by: Helge Deller <deller@gmx.de>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/c7cd882469fc5042a5c84122b4062d7f53076db7"},{"sha":"e79f245ddec17bbd89d73cd0169dba4be46c9b55","author":{"name":"KarimAllah Ahmed","email":"558cc378579f2fcab9c4d24e2576c3762d4edbef@amazon.de"},"message":"X86/KVM: Properly update 'tsc_offset' to represent the running guest\n\nUpdate 'tsc_offset' on vmentry/vmexit of L2 guests to ensure that it always\ncaptures the TSC_OFFSET of the running guest whether it is the L1 or L2\nguest.\n\nCc: Paolo Bonzini <pbonzini@redhat.com>\nCc: Radim Krčmář <rkrcmar@redhat.com>\nCc: kvm@vger.kernel.org\nCc: linux-kernel@vger.kernel.org\nReviewed-by: Jim Mattson <jmattson@google.com>\nSuggested-by: Paolo Bonzini <pbonzini@redhat.com>\nSigned-off-by: KarimAllah Ahmed <karahmed@amazon.de>\n[AMD changes, fix update_ia32_tsc_adjust_msr. - Paolo]\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/e79f245ddec17bbd89d73cd0169dba4be46c9b55"},{"sha":"dd259935e4eec844dc3e5b8a7cd951cd658b4fb6","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"kvm: x86: move MSR_IA32_TSC handling to x86.c\n\nThis is not specific to Intel/AMD anymore.  The TSC offset is available\nin vcpu->arch.tsc_offset.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/dd259935e4eec844dc3e5b8a7cd951cd658b4fb6"},{"sha":"d5edb7f8e7ab9fd5fd54a77d957b1733f117a813","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"kvm: selftests: add vmx_tsc_adjust_test\n\nThe test checks the behavior of setting MSR_IA32_TSC in a nested guest,\nand the TSC_OFFSET VMCS field in general.  It also introduces the testing\ninfrastructure for Intel nested virtualization.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/d5edb7f8e7ab9fd5fd54a77d957b1733f117a813"},{"sha":"e6f39e87b6439939a14cb7fdd94086a082b63b87","author":{"name":"Joerg Roedel","email":"61aff96566804ea1da8a65de5bcc892ce07caceb@suse.de"},"message":"x86/ldt: Fix support_pte_mask filtering in map_ldt_struct()\n\nThe |= operator will let us end up with an invalid PTE. Use\nthe correct &= instead.\n\n[ The bug was also independently reported by Shuah Khan ]\n\nFixes: fb43d6cb91ef ('x86/mm: Do not auto-massage page protections')\nAcked-by: Andy Lutomirski <luto@kernel.org>\nAcked-by: Dave Hansen <dave.hansen@linux.intel.com>\nSigned-off-by: Joerg Roedel <jroedel@suse.de>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/e6f39e87b6439939a14cb7fdd94086a082b63b87"},{"sha":"e6d9bfdeb4395fa5397996b2c3111b5909f41a1b","author":{"name":"Linus Torvalds","email":"69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org"},"message":"Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm\n\nPull kvm fixes from Paolo Bonzini:\n \"Bug fixes, plus a new test case and the associated infrastructure for\n  writing nested virtualization tests\"\n\n* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:\n  kvm: selftests: add vmx_tsc_adjust_test\n  kvm: x86: move MSR_IA32_TSC handling to x86.c\n  X86/KVM: Properly update 'tsc_offset' to represent the running guest\n  kvm: selftests: add -std=gnu99 cflags\n  x86: Add check for APIC access address for vmentry of L2 guests\n  KVM: X86: fix incorrect reference of trace_kvm_pi_irte_update\n  X86/KVM: Do not allow DISABLE_EXITS_MWAIT when LAPIC ARAT is not available\n  kvm: selftests: fix spelling mistake: \"divisable\" and \"divisible\"\n  X86/VMX: Disable VMX preemption timer if MWAIT is not intercepted","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/e6d9bfdeb4395fa5397996b2c3111b5909f41a1b"},{"sha":"d95c8844399885cd511c6f6395621cc1a9fe2e68","author":{"name":"Linus Torvalds","email":"69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org"},"message":"Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip\n\nPull missed timer updates from Thomas Gleixner:\n \"This is a branch which got forgotten during the merge window, but it\n  contains only fixes and hardware enablement. No fundamental changes.\n\n   - Various fixes for the imx-tpm clocksource driver\n\n   - A new timer driver for the NCPM7xx SoC family\"\n\n* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:\n  clocksource/drivers/imx-tpm: Add different counter width support\n  clocksource/drivers/imx-tpm: Correct some registers operation flow\n  clocksource/drivers/imx-tpm: Fix typo of clock name\n  dt-bindings: timer: tpm: fix typo of clock name\n  clocksource/drivers/npcm: Add NPCM7xx timer driver\n  dt-binding: timer: document NPCM7xx timer DT bindings","distinct":false,"url":"https://api.github.com/repos/malaterre/linux/commits/d95c8844399885cd511c6f6395621cc1a9fe2e68"}]}
{"actor":{"display_login":"malaterre"}}