{"push_id":2427490741,"size":44,"distinct_size":0,"ref":"refs/heads/linaro/linux-linaro-lsk-v4.14-test","head":"103afaebcbf03b628aa51f5889125288574c04f9","before":"f2df431469d047a50dd7050cbf2c662c75a7759b","commits":[{"sha":"4e6b36a2f7046223154c345d00db44e0715e78df","author":{"name":"Laura Abbott","email":"1a58644182d4410bcfd1b17f9f7459a41bdc05dd@redhat.com"},"message":"mm: Introduce lm_alias\n\ncommit 568c5fe5a54 upstream.\n\nCertain architectures may have the kernel image mapped separately to\nalias the linear map. Introduce a macro lm_alias to translate a kernel\nimage symbol into its linear alias. This is used in part with work to\nadd CONFIG_DEBUG_VIRTUAL support for arm64.\n\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nTested-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Laura Abbott <labbott@redhat.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/4e6b36a2f7046223154c345d00db44e0715e78df"},{"sha":"d51c36850fa1b1200b94a37657fc96222beb33b6","author":{"name":"Ard Biesheuvel","email":"80b89d4a5c0c8f00cebbb9c7d8a672c776f22af1@linaro.org"},"message":"arm64: alternatives: apply boot time fixups via the linear mapping\n\ncommit 5ea5306c323 upstream.\n\nOne important rule of thumb when desiging a secure software system is\nthat memory should never be writable and executable at the same time.\nWe mostly adhere to this rule in the kernel, except at boot time, when\nregions may be mapped RWX until after we are done applying alternatives\nor making other one-off changes.\n\nFor the alternative patching, we can improve the situation by applying\nthe fixups via the linear mapping, which is never mapped with executable\npermissions. So map the linear alias of .text with RW- permissions\ninitially, and remove the write permissions as soon as alternative\npatching has completed.\n\nReviewed-by: Laura Abbott <labbott@redhat.com>\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nTested-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\treplace update_mapping_prot with old create_mapping_late\n\tarch/arm64/mm/mmu.c","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/d51c36850fa1b1200b94a37657fc96222beb33b6"},{"sha":"d2a0f22f8f281cb15f8ed15df0e7754de252e351","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: barrier: Add CSDB macros to control data-value prediction\n\ncommit 669474e772b9 upstream.\n\nFor CPUs capable of data value prediction, CSDB waits for any outstanding\npredictions to architecturally resolve before allowing speculative execution\nto continue. Provide macros to expose it to the arch code.\n\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tarch/arm64/include/asm/assembler.h\n\tno psb_csync in arch/arm64/include/asm/barrier.h","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/d2a0f22f8f281cb15f8ed15df0e7754de252e351"},{"sha":"a97bea1a3559e899dea495bad8c7942cf0a81829","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"arm64: Implement array_index_mask_nospec()\n\ncommit 022620eed3d0 upstream.\n\nProvide an optimised, assembly implementation of array_index_mask_nospec()\nfor arm64 so that the compiler is not in a position to transform the code\nin ways which affect its ability to inhibit speculation (e.g. by introducing\nconditional branches).\n\nThis is similar to the sequence used by x86, modulo architectural differences\nin the carry/borrow flags.\n\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/a97bea1a3559e899dea495bad8c7942cf0a81829"},{"sha":"4791ce8e1a1b8b067109d764402e4c1c171f6e0c","author":{"name":"Yury Norov","email":"91b2ad6dde64993a0c4e481083844ac462b6dd15@caviumnetworks.com"},"message":"arm64: move TASK_* definitions to <asm/processor.h>\n\ncommit eef94a3d09aab upstream.\n\nILP32 series [1] introduces the dependency on <asm/is_compat.h> for\nTASK_SIZE macro. Which in turn requires <asm/thread_info.h>, and\n<asm/thread_info.h> include <asm/memory.h>, giving a circular dependency,\nbecause TASK_SIZE is currently located in <asm/memory.h>.\n\nIn other architectures, TASK_SIZE is defined in <asm/processor.h>, and\nmoving TASK_SIZE there fixes the problem.\n\nDiscussion: https://patchwork.kernel.org/patch/9929107/\n\n[1] https://github.com/norov/linux/tree/ilp32-next\n\nCC: Will Deacon <will.deacon@arm.com>\nCC: Laura Abbott <labbott@redhat.com>\nCc: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nCc: Catalin Marinas <catalin.marinas@arm.com>\nCc: James Morse <james.morse@arm.com>\nSuggested-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Yury Norov <ynorov@caviumnetworks.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tno ptrace.h in arch/arm64/kernel/entry.S","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/4791ce8e1a1b8b067109d764402e4c1c171f6e0c"},{"sha":"dfcbfcab59d98b9911d4be4d574b5c043d3bbd6f","author":{"name":"Catalin Marinas","email":"6aa257b0f6444d48b36b727fdf3f5c1074b85fd0@arm.com"},"message":"arm64: Factor out PAN enabling/disabling into separate uaccess_* macros\n\ncommit bd38967d406 upstream.\n\nThis patch moves the directly coded alternatives for turning PAN on/off\ninto separate uaccess_{enable,disable} macros or functions. The asm\nmacros take a few arguments which will be used in subsequent patches.\n\nNote that any (unlikely) access that the compiler might generate between\nuaccess_enable() and uaccess_disable(), other than those explicitly\nspecified by the user access code, will not be protected by PAN.\n\nCc: Will Deacon <will.deacon@arm.com>\nCc: James Morse <james.morse@arm.com>\nCc: Kees Cook <keescook@chromium.org>\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/dfcbfcab59d98b9911d4be4d574b5c043d3bbd6f"},{"sha":"86781238cc4db1da55e21249bafed1cc7d2f8b28","author":{"name":"Catalin Marinas","email":"6aa257b0f6444d48b36b727fdf3f5c1074b85fd0@arm.com"},"message":"arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro\n\ncommit f33bcf03e6 upstream\n\nThis patch takes the errata workaround code out of cpu_do_switch_mm into\na dedicated post_ttbr0_update_workaround macro which will be reused in a\nsubsequent patch.\n\nCc: Will Deacon <will.deacon@arm.com>\nCc: James Morse <james.morse@arm.com>\nCc: Kees Cook <keescook@chromium.org>\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/86781238cc4db1da55e21249bafed1cc7d2f8b28"},{"sha":"d07276d685e0417c1c21ef043ecf7099b2946128","author":{"name":"Mark Rutland","email":"7bbc68f29a82fb2eb4daac9d4df0c3f473a4ef26@arm.com"},"message":"arm64: uaccess: consistently check object sizes\n\ncommit 76624175dca upstream.\n\nCurrently in arm64's copy_{to,from}_user, we only check the\nsource/destination object size if access_ok() tells us the user access\nis permissible.\n\nHowever, in copy_from_user() we'll subsequently zero any remainder on\nthe destination object. If we failed the access_ok() check, that applies\nto the whole object size, which we didn't check.\n\nTo ensure that we catch that case, this patch hoists check_object_size()\nto the start of copy_from_user(), matching __copy_from_user() and\n__copy_to_user(). To make all of our uaccess copy primitives consistent,\nthe same is done to copy_to_user().\n\nCc: Catalin Marinas <catalin.marinas@arm.com>\nAcked-by: Kees Cook <keescook@chromium.org>\nSigned-off-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/d07276d685e0417c1c21ef043ecf7099b2946128"},{"sha":"54fbdd604f2eebd0b0f3ebc355544185a4103bf6","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"arm64: Make USER_DS an inclusive limit\n\ncommit 51369e398d0d upstream.\n\nCurrently, USER_DS represents an exclusive limit while KERNEL_DS is\ninclusive. In order to do some clever trickery for speculation-safe\nmasking, we need them both to behave equivalently - there aren't enough\nbits to make KERNEL_DS exclusive, so we have precisely one option. This\nalso happens to correct a longstanding false negative for a range\nending on the very top byte of kernel memory.\n\nMark Rutland points out that we've actually got the semantics of\naddresses vs. segments muddled up in most of the places we need to\namend, so shuffle the {USER,KERNEL}_DS definitions around such that we\ncan correct those properly instead of just pasting \"-1\"s everywhere.\n\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\n(cherry picked from commit 83b20dff71ea949431cf57c6aebaaf7ebd5c1991)\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tforce replace __range_ok and add asm/processor.h\n\tin arch/arm64/include/asm/uaccess.h\n\tusing old macro TI_ADDR_LIMIT instead of TSK_TI_ADDR_LIMIT\n\tin arch/arm64/kernel/entry.S\n\tmanual change USER_DS to TASK_SIZE in arch/arm64/mm/fault.c","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/54fbdd604f2eebd0b0f3ebc355544185a4103bf6"},{"sha":"a2c02bdb7d5ff2018381d926bcaa6a7020ce3358","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"arm64: Use pointer masking to limit uaccess speculation\n\ncommit 4d8efc2d5ee4 upstream.\n\nSimilarly to x86, mitigate speculation past an access_ok() check by\nmasking the pointer against the address limit before use.\n\nEven if we don't expect speculative writes per se, it is plausible that\na CPU may still speculate at least as far as fetching a cache line for\nwriting, hence we also harden put_user() and clear_user() for peace of\nmind.\n\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/a2c02bdb7d5ff2018381d926bcaa6a7020ce3358"},{"sha":"3a1d63f571cc9b50d361ea5807d888019a4a05c6","author":{"name":"Dave Martin","email":"efb8cc9d02b9c95845d8a14436d3a7276e72ae4e@arm.com"},"message":"arm64: syscallno is secretly an int, make it official\n\ncommit 35d0e6fb4d upstream.\n\nThe upper 32 bits of the syscallno field in thread_struct are\nhandled inconsistently, being sometimes zero extended and sometimes\nsign-extended.  In fact, only the lower 32 bits seem to have any\nreal significance for the behaviour of the code: it's been OK to\nhandle the upper bits inconsistently because they don't matter.\n\nCurrently, the only place I can find where those bits are\nsignificant is in calling trace_sys_enter(), which may be\nunintentional: for example, if a compat tracer attempts to cancel a\nsyscall by passing -1 to (COMPAT_)PTRACE_SET_SYSCALL at the\nsyscall-enter-stop, it will be traced as syscall 4294967295\nrather than -1 as might be expected (and as occurs for a native\ntracer doing the same thing).  Elsewhere, reads of syscallno cast\nit to an int or truncate it.\n\nThere's also a conspicuous amount of code and casting to bodge\naround the fact that although semantically an int, syscallno is\nstored as a u64.\n\nLet's not pretend any more.\n\nIn order to preserve the stp x instruction that stores the syscall\nnumber in entry.S, this patch special-cases the layout of struct\npt_regs for big endian so that the newly 32-bit syscallno field\nmaps onto the low bits of the stored value.  This is not beautiful,\nbut benchmarking of the getpid syscall on Juno suggests indicates a\nminor slowdown if the stp is split into an stp x and stp w.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/3a1d63f571cc9b50d361ea5807d888019a4a05c6"},{"sha":"e4faaf1819502d2d040b555bff42929d68afd28f","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: entry: Ensure branch through syscall table is bounded under speculation\n\ncommit 6314d90e6493 upstream.\n\nIn a similar manner to array_index_mask_nospec, this patch introduces an\nassembly macro (mask_nospec64) which can be used to bound a value under\nspeculation. This macro is then used to ensure that the indirect branch\nthrough the syscall table is bounded under speculation, with out-of-range\naddresses speculating as calls to sys_io_setup (0).\n\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/e4faaf1819502d2d040b555bff42929d68afd28f"},{"sha":"321ca404e0fc9e34d4e425c93517cbff985c90c3","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: uaccess: Prevent speculative use of the current addr_limit\n\ncommit c2f0ad4fc089 upstream.\n\nA mispredicted conditional call to set_fs could result in the wrong\naddr_limit being forwarded under speculation to a subsequent access_ok\ncheck, potentially forming part of a spectre-v1 attack using uaccess\nroutines.\n\nThis patch prevents this forwarding from taking place, but putting heavy\nbarriers in set_fs after writing the addr_limit.\n\nReviewed-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tno set_thread_flag(TIF_FSCHECK) in arch/arm64/include/asm/uaccess.h","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/321ca404e0fc9e34d4e425c93517cbff985c90c3"},{"sha":"f54cfe875bdcbc5737982653940aff39d273bccd","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: uaccess: Don't bother eliding access_ok checks in __{get, put}_user\n\ncommit 84624087dd7e upstream.\n\naccess_ok isn't an expensive operation once the addr_limit for the current\nthread has been loaded into the cache. Given that the initial access_ok\ncheck preceding a sequence of __{get,put}_user operations will take\nthe brunt of the miss, we can make the __* variants identical to the\nfull-fat versions, which brings with it the benefits of address masking.\n\nThe likely cost in these sequences will be from toggling PAN/UAO, which\nwe can address later by implementing the *_unsafe versions.\n\nReviewed-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tkeep __{get/put}_user_unaligned in arch/arm64/include/asm/uaccess.h","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/f54cfe875bdcbc5737982653940aff39d273bccd"},{"sha":"0c4548eb5ec92d2e89f86bbbe46d6acf6a5cb1d3","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: uaccess: Mask __user pointers for __arch_{clear, copy_*}_user\n\nRewritting from commit f71c2ffcb20d upstream. On LTS 4.9, there has no\nraw_copy_from/to_user, neither __copy_user_flushcache, and it isn't good\nidead to pick up them. The following is origin commit log, that's also\napplicable for the new patch.\n\n    Like we've done for get_user and put_user, ensure that user pointers\n    are masked before invoking the underlying __arch_{clear,copy_*}_user\n    operations.\n\n    Signed-off-by: Will Deacon <will.deacon@arm.com>\n    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>\n\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/0c4548eb5ec92d2e89f86bbbe46d6acf6a5cb1d3"},{"sha":"dbd2b2078ceaac6a7860b33c6f0a93acc2f7bb3e","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: futex: Mask __user pointers prior to dereference\n\ncommit 91b2d3442f6a upstream.\n\nThe arm64 futex code has some explicit dereferencing of user pointers\nwhere performing atomic operations in response to a futex command. This\npatch uses masking to limit any speculative futex operations to within\nthe user address space.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts:\n\tchange on old futex_atomic_op_inuser function instead of\n\tarch_futex_atomic_op_inuser in arch/arm64/include/asm/futex.h","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/dbd2b2078ceaac6a7860b33c6f0a93acc2f7bb3e"},{"sha":"10a3a99f2c58122f8a45d8944bbc34c08a807665","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"drivers/firmware: Expose psci_get_version through psci_ops structure\n\ncommit d68e3ba5303f upstream.\n\nEntry into recent versions of ARM Trusted Firmware will invalidate the CPU\nbranch predictor state in order to protect against aliasing attacks.\n\nThis patch exposes the PSCI \"VERSION\" function via psci_ops, so that it\ncan be invoked outside of the PSCI driver where necessary.\n\nAcked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/10a3a99f2c58122f8a45d8944bbc34c08a807665"},{"sha":"ba36e8b491dba985cd6152c611d60f2147346812","author":{"name":"James Morse","email":"3f3c71a988a3895b9a80f00dbeb25517110f1863@arm.com"},"message":"arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early\n\ncommit edf298cfce47 upstream.\nAlex Shi rewrite this commit on func this_cpu_has_cap(). The following commit\nlog is still meaningful.\n\n    this_cpu_has_cap() tests caps->desc not caps->matches, so it stops\n    walking the list when it finds a 'silent' feature, instead of\n    walking to the end of the list.\n\n    Prior to v4.6's 644c2ae198412 (\"arm64: cpufeature: Test 'matches' pointer\n    to find the end of the list\") we always tested desc to find the end of\n    a capability list. This was changed for dubious things like PAN_NOT_UAO.\n    v4.7's e3661b128e53e (\"arm64: Allow a capability to be checked on\n    single CPU\") added this_cpu_has_cap() using the old desc style test.\n\n    CC: Suzuki K Poulose <suzuki.poulose@arm.com>\n    Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>\n    Acked-by: Marc Zyngier <marc.zyngier@arm.com>\n    Signed-off-by: James Morse <james.morse@arm.com>\n    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>\n    Signed-off-by: Will Deacon <will.deacon@arm.com>\n\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/ba36e8b491dba985cd6152c611d60f2147346812"},{"sha":"7f532d35072092a0b319420cf3875da5f0dbee75","author":{"name":"Marc Zyngier","email":"3404add73d8af5dc5183acdd46985971473febc7@arm.com"},"message":"arm64: cpu_errata: Allow an erratum to be match for all revisions of a core\n\ncommit 06f1494f837 upstream.\n\nSome minor erratum may not be fixed in further revisions of a core,\nleading to a situation where the workaround needs to be updated each\ntime an updated core is released.\n\nIntroduce a MIDR_ALL_VERSIONS match helper that will work for all\nversions of that MIDR, once and for all.\n\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nAcked-by: Mark Rutland <mark.rutland@arm.com>\nAcked-by: Daniel Lezcano <daniel.lezcano@linaro.org>\nReviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/7f532d35072092a0b319420cf3875da5f0dbee75"},{"sha":"d3e6b013c32031960a2445d806ac9a142827a6b4","author":{"name":"Suzuki K Poulose","email":"239e6ad0fed873c6240fa61c5ed99f611cd6b279@arm.com"},"message":"arm64: Run enable method for errata work arounds on late CPUs\n\ncommit 55b35d070c25 upstream.\n\nWhen a CPU is brought up after we have finalised the system\nwide capabilities (i.e, features and errata), we make sure the\nnew CPU doesn't need a new errata work around which has not been\ndetected already. However we don't run enable() method on the new\nCPU for the errata work arounds already detected. This could\ncause the new CPU running without potential work arounds.\nIt is upto the \"enable()\" method to decide if this CPU should\ndo something about the errata.\n\nFixes: commit 6a6efbb45b7d95c84 (\"arm64: Verify CPU errata work arounds on hotplugged CPU\")\nCc: Will Deacon <will.deacon@arm.com>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Andre Przywara <andre.przywara@arm.com>\nCc: Dave Martin <dave.martin@arm.com>\nSigned-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":false,"url":"https://api.github.com/repos/mifl/android_kernel_qcom_msm-3.18/commits/d3e6b013c32031960a2445d806ac9a142827a6b4"}]}
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