{"action":"created","issue":{"url":"https://api.github.com/repos/rust-lang/rust/issues/50154","repository_url":"https://api.github.com/repos/rust-lang/rust","labels_url":"https://api.github.com/repos/rust-lang/rust/issues/50154/labels{/name}","comments_url":"https://api.github.com/repos/rust-lang/rust/issues/50154/comments","events_url":"https://api.github.com/repos/rust-lang/rust/issues/50154/events","html_url":"https://github.com/rust-lang/rust/issues/50154","id":316562383,"number":50154,"title":"Small SIMD test fails with --release but passes without","user":{"login":"danielrh","id":47249,"avatar_url":"https://avatars1.githubusercontent.com/u/47249?v=4","gravatar_id":"","url":"https://api.github.com/users/danielrh","html_url":"https://github.com/danielrh","followers_url":"https://api.github.com/users/danielrh/followers","following_url":"https://api.github.com/users/danielrh/following{/other_user}","gists_url":"https://api.github.com/users/danielrh/gists{/gist_id}","starred_url":"https://api.github.com/users/danielrh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/danielrh/subscriptions","organizations_url":"https://api.github.com/users/danielrh/orgs","repos_url":"https://api.github.com/users/danielrh/repos","events_url":"https://api.github.com/users/danielrh/events{/privacy}","received_events_url":"https://api.github.com/users/danielrh/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2018-04-22T09:06:06Z","updated_at":"2018-04-22T18:45:45Z","closed_at":null,"author_association":"NONE","body":"Full repro here:\r\nhttps://github.com/danielrh/simd_playground run with `cargo test --release`\r\nfailing test is here:\r\n```rust\r\n#![feature(stdsimd)]\r\nmod test {\r\n#[test]\r\nfn baseline() {\r\nuse std::simd::*;\r\n   let symbol = 2i16;\r\n   let inc = 1i16;\r\n   let data = i16x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64);\r\n   let one_to_16 = i16x16::new(1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);\r\n   let increment_v = i16x16::splat(inc);\r\n   let mask_v = unsafe {\r\n            ::std::arch::x86_64::_mm256_cmpgt_epi16(::std::arch::x86_64::__m256i::from_bits(one_to_16),\r\n                                                   ::std::arch::x86_64::__m256i::from_bits(i16x16::splat(i16::from(symbol))))\r\n    };\r\n    let output = data + (increment_v & i16x16::from_bits(mask_v));\r\n    let mut xfinal = [0i16; 16];\r\n    output.store_unaligned(&mut xfinal);\r\n    assert_eq!(xfinal, [4, 8, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65]);\r\n}\r\n}\r\n```\r\nusing: \r\n```rustc 1.27.0-nightly (ac3c2288f 2018-04-18)\r\nbinary: rustc\r\ncommit-hash: ac3c2288f9f9d977acb46406ba60033d65165a7b\r\ncommit-date: 2018-04-18\r\nhost: x86_64-apple-darwin\r\nrelease: 1.27.0-nightly\r\nLLVM version: 6.0\r\n```\r\non OSX 10.12.6 (16G1314)\r\n\r\nand also on linux\r\n```\r\nrustc --verbose --version\r\nrustc 1.27.0-nightly (ac3c2288f 2018-04-18)\r\nbinary: rustc\r\ncommit-hash: ac3c2288f9f9d977acb46406ba60033d65165a7b\r\ncommit-date: 2018-04-18\r\nhost: x86_64-unknown-linux-gnu\r\nrelease: 1.27.0-nightly\r\nLLVM version: 6.0\r\n```\r\n\r\nI was unable to reproduce the above problem by making a simple main with the above function, so it could be something to do with the build options.\r\n\r\nOne more note: the same exact test and code have been working for months with stdsimd 0.0.3 and 0.0.4 crate. I couldn't get that crate to build with nightly 1.27.0, so I couldn't see if it still worked.\r\n\r\n\r\n"},"comment":{"url":"https://api.github.com/repos/rust-lang/rust/issues/comments/383403252","html_url":"https://github.com/rust-lang/rust/issues/50154#issuecomment-383403252","issue_url":"https://api.github.com/repos/rust-lang/rust/issues/50154","id":383403252,"user":{"login":"danielrh","id":47249,"avatar_url":"https://avatars1.githubusercontent.com/u/47249?v=4","gravatar_id":"","url":"https://api.github.com/users/danielrh","html_url":"https://github.com/danielrh","followers_url":"https://api.github.com/users/danielrh/followers","following_url":"https://api.github.com/users/danielrh/following{/other_user}","gists_url":"https://api.github.com/users/danielrh/gists{/gist_id}","starred_url":"https://api.github.com/users/danielrh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/danielrh/subscriptions","organizations_url":"https://api.github.com/users/danielrh/orgs","repos_url":"https://api.github.com/users/danielrh/repos","events_url":"https://api.github.com/users/danielrh/events{/privacy}","received_events_url":"https://api.github.com/users/danielrh/received_events","type":"User","site_admin":false},"created_at":"2018-04-22T18:45:45Z","updated_at":"2018-04-22T18:45:45Z","author_association":"NONE","body":"Great question: I can avoid the bug by specifying `RUSTFLAGS=\"-C target-cpu=core-avx-i\" cargo test --release` as the build command line\r\n\r\nBut in the past, llvm has been able to polyfill the instructions down to SSE2 with stdsimd-0.0.4 and therefore I didn't have to specify any flag at all.\r\n\r\nI've noticed that asking LLVM to polyfill the instructions from avx2 down to core-avx-i actually improves performance on most available AVX2 hardware unless your instructions are sufficiently dense. This is because the AVX2 instructions downclock the chip for some time, and so it's much better to keep the full clock speed, but then keep the AVX2 code around for newer chips like skylake.\r\n\r\nI really loved writing AVX2 intrinsics and having the compiler match them to my desired architecture...having 4 code paths (avx2, avx and SSE4.2 and SSE2) to match my desired targets is a significant support burden, so from my perspective, the old behavior with the SSE2 polyfill was ideal.\r\n"}}
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