{"push_id":3096585181,"size":2,"distinct_size":2,"ref":"refs/heads/tegra_dev","head":"ca988352f38ef6379d4edbe3df42420f6b813733","before":"9d573dd937bc41794a6315a9f0a9fbb95974eae9","commits":[{"sha":"0d779c6c06805ff9b5da69b837c4ddedb72f3012","author":{"name":"Stephen Warren","email":"5ef2a23ba3aff51d1cfc8c113c1ec34b608b3b13@nvidia.com"},"message":"PCI: dwc: Don't hard-code DBI/ATU offset\n\nThe DWC PCIe core contains various separate register spaces: DBI, DBI2,\nATU, DMA, etc. The relationship between the addresses of these register\nspaces is entirely determined by the implementation of the IP block, not\nby the IP block design itself. Hence, the DWC driver must not make\nassumptions that one register space can be accessed at a fixed offset from\nany other register space. To avoid such assumptions, introduce an\nexplicit/separate register pointer for the ATU register space. In\nparticular, the current assumption is not valid for NVIDIA's T194 SoC.\n\nThe ATU register space is only used on systems that require unrolled ATU\naccess. This property is detected at run-time for host controllers, and\nwhen this is detected, this patch provides a default value for atu_base\nthat matches the previous assumption re: register layout. An alternative\nwould be to update all drivers for HW that requires unrolled access to\nexplicitly set atu_base. However, it's hard to tell which drivers would\nrequire atu_base to be set. The unrolled property is not detected for\nendpoint systems, and so any endpoint driver that requires unrolled access\nmust explicitly set the iatu_unroll_enabled flag (none do at present), and\nso a check is added to require the driver to also set atu_base while at\nit.\n\nSigned-off-by: Stephen Warren <swarren@nvidia.com>\nAcked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>\nAcked-by: Vidya Sagar <vidyas@nvidia.com>\n---\nv3:\n* Added DEFAULT_DBI_ATU_OFFSET define and associated comment.\nv2:\n* Modified patch subject\n* Added missing outer brackets to PCIE_GET_ATU_INB_UNR_REG_OFFSET macro","distinct":true,"url":"https://api.github.com/repos/swarren/linux-tegra/commits/0d779c6c06805ff9b5da69b837c4ddedb72f3012"},{"sha":"ca988352f38ef6379d4edbe3df42420f6b813733","author":{"name":"Stephen Warren","email":"5ef2a23ba3aff51d1cfc8c113c1ec34b608b3b13@nvidia.com"},"message":"PCI: dwc ep: cache config until DBI regs available\n\nSome implementations of the DWC PCIe endpoint controller do not allow\naccess to DBI registers until the attached host has started REFCLK,\nreleased PERST, and the endpoint driver has initialized clocking of the\nDBI registers based on that. One such system is NVIDIA's T194 SoC. The\nPCIe endpoint subsystem and DWC driver currently don't work on such\nhardware, since they assume that all endpoint configuration can happen\nat any arbitrary time.\n\nEnhance the DWC endpoint driver to support such systems by caching all\nendpoint configuration in software, and only writing the configuration\nto hardware once it's been initialized. This is implemented by splitting\nall endpoint controller ops into two functions; the first which simply\nrecords/caches the desired configuration whenever called by the\nassociated function driver and optionally calls the second, and the\nsecond which actually programs the configuration into hardware, which\nmay be called either by the first function, or later when it's known\nthat the DBI registers are available.\n\nSigned-off-by: Stephen Warren <swarren@nvidia.com>\n---\nv2:\nReplace hw_regs_available with hw_regs_not_available. A 0 value in this\nfield is now equivalent to the existing behaviour, so that drivers that\nallocate struct dw_pcie_ep with kzalloc or equivalent do not need to\nexplicitly set this new field in order to maintain existing behaviour.\n\nNote: I have only compiled-tested this patch in the context of the\nmainline kernel since NVIDIA Tegra PCIe EP support is not yet present.\nHowever, I've built and tested an equivalent patch in our downstream\nkernel. I did have to manually port it to mainline due to conflicts\nthough.\n\nThis patch was developed on top of \"PCI: designware: don't hard-code\nDBI/ATU offset\" which I sent a little while back, so may rely on that\nfor patch context.","distinct":true,"url":"https://api.github.com/repos/swarren/linux-tegra/commits/ca988352f38ef6379d4edbe3df42420f6b813733"}]}
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