{"action":"closed","issue":{"url":"https://api.github.com/repos/ghdl/ghdl/issues/530","repository_url":"https://api.github.com/repos/ghdl/ghdl","labels_url":"https://api.github.com/repos/ghdl/ghdl/issues/530/labels{/name}","comments_url":"https://api.github.com/repos/ghdl/ghdl/issues/530/comments","events_url":"https://api.github.com/repos/ghdl/ghdl/issues/530/events","html_url":"https://github.com/ghdl/ghdl/issues/530","id":298024265,"number":530,"title":"casting of sliced port in a module instantiation fails","user":{"login":"putsplut","id":26128264,"avatar_url":"https://avatars1.githubusercontent.com/u/26128264?v=4","gravatar_id":"","url":"https://api.github.com/users/putsplut","html_url":"https://github.com/putsplut","followers_url":"https://api.github.com/users/putsplut/followers","following_url":"https://api.github.com/users/putsplut/following{/other_user}","gists_url":"https://api.github.com/users/putsplut/gists{/gist_id}","starred_url":"https://api.github.com/users/putsplut/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/putsplut/subscriptions","organizations_url":"https://api.github.com/users/putsplut/orgs","repos_url":"https://api.github.com/users/putsplut/repos","events_url":"https://api.github.com/users/putsplut/events{/privacy}","received_events_url":"https://api.github.com/users/putsplut/received_events","type":"User","site_admin":false},"labels":[{"id":288528269,"url":"https://api.github.com/repos/ghdl/ghdl/labels/Bug","name":"Bug","color":"fc2929","default":false}],"state":"closed","locked":false,"assignee":{"login":"tgingold","id":13433645,"avatar_url":"https://avatars2.githubusercontent.com/u/13433645?v=4","gravatar_id":"","url":"https://api.github.com/users/tgingold","html_url":"https://github.com/tgingold","followers_url":"https://api.github.com/users/tgingold/followers","following_url":"https://api.github.com/users/tgingold/following{/other_user}","gists_url":"https://api.github.com/users/tgingold/gists{/gist_id}","starred_url":"https://api.github.com/users/tgingold/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tgingold/subscriptions","organizations_url":"https://api.github.com/users/tgingold/orgs","repos_url":"https://api.github.com/users/tgingold/repos","events_url":"https://api.github.com/users/tgingold/events{/privacy}","received_events_url":"https://api.github.com/users/tgingold/received_events","type":"User","site_admin":false},"assignees":[{"login":"tgingold","id":13433645,"avatar_url":"https://avatars2.githubusercontent.com/u/13433645?v=4","gravatar_id":"","url":"https://api.github.com/users/tgingold","html_url":"https://github.com/tgingold","followers_url":"https://api.github.com/users/tgingold/followers","following_url":"https://api.github.com/users/tgingold/following{/other_user}","gists_url":"https://api.github.com/users/tgingold/gists{/gist_id}","starred_url":"https://api.github.com/users/tgingold/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tgingold/subscriptions","organizations_url":"https://api.github.com/users/tgingold/orgs","repos_url":"https://api.github.com/users/tgingold/repos","events_url":"https://api.github.com/users/tgingold/events{/privacy}","received_events_url":"https://api.github.com/users/tgingold/received_events","type":"User","site_admin":false}],"milestone":null,"comments":4,"created_at":"2018-02-17T18:10:14Z","updated_at":"2018-02-18T17:25:19Z","closed_at":"2018-02-18T17:25:19Z","author_association":"NONE","body":"When instantiating a module, it is sometimes convenient to cast portions of an input or output port.  In the example, I cast both directions. The cast on the output raises an exception `TYPES.INTERNAL_ERROR : trans.adb:619`. The input port cast works fine, and a cast on an entire port works fine.\r\n\r\nNote: support for casting or slices of ports has spotty results across commercial tools.  The example would work in Riviera-PRO and Modelsim.  Riviera has had issues with a function call being assigned to a sliced input (even when the function is just a shorthand cast). Vivado has had issues with (I think) the sliced output casts, but Quartus accepts it.\r\n\r\n```vhdl\r\nlibrary ieee;\r\n   use ieee.std_logic_1164.all;\r\n   use ieee.numeric_std.all;\r\n\r\nentity submodule is\r\nport (\r\n   clk : in  std_logic;\r\n   arg : in  std_logic_vector(15 downto 0);\r\n   res : out std_logic_vector(15 downto 0)\r\n);\r\nend submodule;\r\n\r\nlibrary ieee;\r\n   use ieee.std_logic_1164.all;\r\n   use ieee.numeric_std.all;\r\n\r\nentity sliced_ex is\r\nport (\r\n   clk   : in  std_logic;\r\n   arg_a : in  signed(7 downto 0);\r\n   arg_b : in  signed(7 downto 0);\r\n   res_a : out signed(7 downto 0);\r\n   res_b : out signed(7 downto 0)\r\n);\r\nend sliced_ex;\r\n\r\narchitecture rtl of sliced_ex is\r\n\r\n   signal tmp : signed(15 downto 0);\r\n\r\nbegin\r\n\r\n   SUB_MODULE : entity work.submodule\r\n   port map (\r\n      clk => clk,\r\n      arg( 7 downto 0) => std_logic_vector(arg_a),\r\n      arg(15 downto 8) => std_logic_vector(arg_b),\r\n      -- The casting of a sliced output causes an exception.\r\n      -- Casting of the entire output bus does work\r\n      -- signed(res) => tmp -- (this would work)\r\n      signed(res( 7 downto 0)) => res_a,\r\n      signed(res(15 downto 8)) => res_b\r\n   );\r\n\r\nend rtl;\r\n```\r\n\r\n[sample_slice_ports.vhd.txt](https://github.com/ghdl/ghdl/files/1733960/sample_slice_ports.vhd.txt)\r\n"}}
{"actor":{"display_login":"tgingold"}}