{"push_id":3080803106,"size":264,"distinct_size":1,"ref":"refs/heads/power-gpr0-exclude","head":"6119568ae2fdada44f6d593a6ed2dd5d953b3b8f","before":"d9010a1758a97d7bbdb99c22e44309af165d4790","commits":[{"sha":"f55e0f1cead484559fb7f89e63fffcf70404607c","author":{"name":"Henry Zongaro","email":"100255d9dced3045c921ee08f370d6bd7239070d@ca.ibm.com"},"message":"Add support for inlining new atomic methods on Power\n\nAdded support for inlining of the new atomic methods\natomic{AddAndFetch|FetchAndAdd|Swap}{32|64}BitSymbol on Power.  This is\nlargely a copy of similar support in OpenJ9 for inlining methods of\nAtomicInteger and AtomicLong.\n\nSigned-off-by:  Henry Zongaro <zongaro@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/f55e0f1cead484559fb7f89e63fffcf70404607c"},{"sha":"30fb9c6471e960891b905b342f9b126e2c36524c","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Implement iconstEvaluator() and some others\n\nThis commit implements some evaluators in UnaryEvaluator.cpp,\nsuch as iconstEvaluator() and lconstEvaluator(), for aarch64.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/30fb9c6471e960891b905b342f9b126e2c36524c"},{"sha":"0351d176e8d75a80f3ba010b76a1e93b12c5ec7e","author":{"name":"Victor Ding","email":"702c5efe41471368ec946f49f1a994144025b9bd@ca.ibm.com"},"message":"Properly set array related feature flags on X86\n\nGuard following feature flags with \"canGenerateArraylets\":\n1. SupportsArrayCmp\n2. SupportsPrimitiveArrayCopy\n3. SupportsArraySet\n4. SupportsArrayTranslateTRTO\n5. SupportsArrayTranslateTROT\n6. SupportsArrayTranslateTROTNoBreak\n\nRemove SupportsReferenceArrayCopy as OMR doesn't actually\nfully support reference arraycopy.\n\nSigned-off-by: Victor Ding <dvictor@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/0351d176e8d75a80f3ba010b76a1e93b12c5ec7e"},{"sha":"1ebf7cc8f938811b55bc4fc9dfd2a6715ec31137","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Implement BBStart/BBEnd evaluators\n\nThis commit implements BBStart/BBEnd evaluators for aarch64.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/1ebf7cc8f938811b55bc4fc9dfd2a6715ec31137"},{"sha":"1106bb4b2fe9943f43c43b5f0d00f4c177f89aa3","author":{"name":"Henry Zongaro","email":"100255d9dced3045c921ee08f370d6bd7239070d@ca.ibm.com"},"message":"Avoid inlining TR_ScratchBufferInfo::writeToBuffer\n\nIf TR_ScratchBufferInfo::writeToBuffer is inlined, it appears to expose\na bug in code generated by the IBM xlC compiler on z-Series.  The same\n(or a similar) problem was previously seen on p-Series compiling with\nxlC, and the work-around was to avoid inlining when compiling with xlC\non POWER.  This extends the same work-around to z compiling with xlC\n\nSigned-off-by:  Henry Zongaro <zongaro@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/1106bb4b2fe9943f43c43b5f0d00f4c177f89aa3"},{"sha":"42f72e85c25fa8cfd9d5c282835b72b8c419be69","author":{"name":"Henry Zongaro","email":"100255d9dced3045c921ee08f370d6bd7239070d@ca.ibm.com"},"message":"Update comment for TR_ScratchBufferInfo::writeToBuffer\n\nUpdated comments for TR_ScratchBufferInfo::writeToBuffer to indicate\nxlC compiler versions that have shown problems on z and POWER that\nnecessitated prevention of inlining, along with the symptoms seen.\n\nSigned-of-by:  Henry Zongaro <zongaro@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/42f72e85c25fa8cfd9d5c282835b72b8c419be69"},{"sha":"85d8c0ef0c2ab327a040b00f40993f132308cf1c","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Implement iaddEvaluator() and some others\n\nThis commit implements some evaluators in BinaryEvaluator.cpp,\nsuch as iaddEvaluator() and imulEvaluator(), for aarch64.\nThis depends on #2963, and #2964.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/85d8c0ef0c2ab327a040b00f40993f132308cf1c"},{"sha":"880c6897fb8715322fae6d67b38c0435a0d3cebb","author":{"name":"Henry Zongaro","email":"100255d9dced3045c921ee08f370d6bd7239070d@ca.ibm.com"},"message":"Add support for inlining new atomic methods on Power\n\nAdded support for inlining of the new atomic methods\natomic{AddAndFetch|FetchAndAdd|Swap}{32|64}BitSymbol on Power.  This is\nlargely a copy of similar support in OpenJ9 for inlining methods of\nAtomicInteger and AtomicLong.\n\nSigned-off-by:  Henry Zongaro <zongaro@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/880c6897fb8715322fae6d67b38c0435a0d3cebb"},{"sha":"6dbec8898ac4f97e7a8ad4bd12ee1b6393e31fc8","author":{"name":"Henry Zongaro","email":"100255d9dced3045c921ee08f370d6bd7239070d@ca.ibm.com"},"message":"Merge branch 'atomic-power-alt' of https://github.com/hzongaro/omr into atomic-power-alt","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/6dbec8898ac4f97e7a8ad4bd12ee1b6393e31fc8"},{"sha":"c53a0aa42cd78c89ce0339be3d0c52d84e967e30","author":{"name":"Victor Ding","email":"702c5efe41471368ec946f49f1a994144025b9bd@ca.ibm.com"},"message":"Avoid OOL instruction generation during OOM on X86\n\nOutlinedInstructionsGenerator to not generate instructions\nwhen there is a uncaught exception.\n\nSigned-off-by: Victor Ding <dvictor@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/c53a0aa42cd78c89ce0339be3d0c52d84e967e30"},{"sha":"f0599cdf87b2c47c6ebdea98853ba2a7d6afc911","author":{"name":"Pavel Samolysov","email":"6f1fcf954d441b01751b39f5c198405aaa04dae3@gmail.com"},"message":"Fix MSVC error C2398 requires narrowing conversion\n\nThe 'SimpifierFoldAbsNegTest' unit test from 'compilertriltest' contains\nan initialization block for a vector of floats:\n\nstd::vector<  float> fTestData =\n    { 0, 1, 2, -1, -2, 3.14, -3.14,\n      std::numeric_limits<float>::min(), std::numeric_limits<float>::min() };\n\nDuring a compilation with MSVC the following errors appears:\n\n.\\..\\fvtest\\compilertriltest\\SimplifierFoldAbsNegTest.cpp(45): error\nC2398: Element '6': conversion from 'double' to 'float' requires a\nnarrowing conversion\n..\\..\\fvtest\\compilertriltest\\SimplifierFoldAbsNegTest.cpp(45): error\nC2398: Element '7': conversion from 'double' to 'float' requires a\nnarrowing conversion\n\nLiterals '3.14' and '-3.14' can be represented as well 'double' as\n'float', the 'f' suffix after the literal must be present to fix the\ncompilation error.\n\nSigned-off-by: Pavel Samolysov <samolisov@gmail.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/f0599cdf87b2c47c6ebdea98853ba2a7d6afc911"},{"sha":"e8f65c40c0037a1be4f3db68ac54b3a2434852ca","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Merge pull request #3086 from 0dvictor/unwind\n\nAvoid OOL instruction generation during OOM on X86\r\n\r\nFixes #3083","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/e8f65c40c0037a1be4f3db68ac54b3a2434852ca"},{"sha":"b86e576fadee9413f0da79f8dc527a00be95680e","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Remove code related to MemoryDataRegister from OMRMemoryReference\n\nOMRMemoryReference::generateBinaryEncoding() had wrong code for\nembedding MemoryDataRegister in instruction binary encoding.\nThis commit removes those lines.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/b86e576fadee9413f0da79f8dc527a00be95680e"},{"sha":"36e7e26e011d87c106ec13c5ffd428e8b110370c","author":{"name":"Aleksandar Micic","email":"298dda9593d6eb8fc6f51007550c14e933a91a98@ca.ibm.com"},"message":"Flush GC caches for concurrent marker thread\n\nGC threads at startup act briefly as mutators since they allocate from\nheap (various thread specific objects). Before transitioning the thread\ntype to its specific GC role, they need to flush any GC specific caches,\nas any mutators do.\n\nSpecifically, in Concurrent Scavenger, if a GC thread is created during\na very early cycle, it may trigger a read barrier and create a copy\ncache. This cache has to by flushed (to scan queue for further scanning\nin final STW GC phase).\n\nThis problem has already been addressed for Master and Slave GC threads\n(https://github.com/eclipse/omr/pull/2696). Here Concurrent Marking\nBackground threads are treated with the identical fix. \n\nSigned-off-by: Aleksandar Micic <amicic@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/36e7e26e011d87c106ec13c5ffd428e8b110370c"},{"sha":"e45d8b15fb12d94da667f6bad336a26ec7520e64","author":{"name":"Aleksandar Micic","email":"298dda9593d6eb8fc6f51007550c14e933a91a98@ca.ibm.com"},"message":"State explicitly CS witout H/W assistance\n\nSlighly modify the verbose GC stanza where we state if Concurrent\nScavenger is enabled:\n\n1) on H/W capable platforms we will state one of two:\n\nenabled, with H/W assistance\nenabled, without H/W assistance\n\n2) on plaforms with no H/W assistance we will just state:\n\nenabled\n\n3) if CS is not enabled, regardless of platform, the stanza is not\nissued\n\nSince there is an overlap, also piggybacking to this change removal of\nunused softwareEvacuateReadBarrier flag and retirment of jitLoaded field\nin Initialized hook.\n\nSigned-off-by: Aleksandar Micic <amicic@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/e45d8b15fb12d94da667f6bad336a26ec7520e64"},{"sha":"f1a7d77c2c963095b585bc3e2fd820585bfbf308","author":{"name":"Keith W. Campbell","email":"95f8b4a83822d17dd9d3a4fe1dcf2f0c5c806590@ca.ibm.com"},"message":"Add support for CUDA 10.0\n\nAccording to [1], CUDA Toolkit version 10.0\nwas released in September 2018.\n\n[1] https://developer.nvidia.com/cuda-toolkit-archive\n\nSigned-off-by: Keith W. Campbell <keithc@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/f1a7d77c2c963095b585bc3e2fd820585bfbf308"},{"sha":"b97b1f25d016890b4ef13a92d2a1131d21be26a4","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Merge pull request #3090 from samolisov/fix-triltest-compilation\n\nFix MSVC error C2398 requires narrowing conversion","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/b97b1f25d016890b4ef13a92d2a1131d21be26a4"},{"sha":"b2c40107f76e9f4309cc9dd1efd86e7e1d836a95","author":{"name":"Daryl Maier","email":"04babc56297ff17e6845dac082142a3f971b0934@ca.ibm.com"},"message":"Merge pull request #2985 from knn-k/aarch64eval6\n\nAArch64: Implement iaddEvaluator() and some others","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/b2c40107f76e9f4309cc9dd1efd86e7e1d836a95"},{"sha":"685af8173bd363abfa77552dff3354bcc4129a3c","author":{"name":"Aleksandar Micic","email":"298dda9593d6eb8fc6f51007550c14e933a91a98@ca.ibm.com"},"message":"Explicit thread count for parallel GC task\n\nFixing 2 problems, when overriding thread count for a task (via run()\nAPI), which may occur in a scenario when initial heap size is so small\nto cause an early GC before even all GC threads are up and running: \n\n1) major: the overriding value should be no bigger than\n_threadCount/_adjustedThreadCount, since there might not be\nmore slave threads available, yet. Otherwise, the task would hang\nwaiting for non-existant threads to complete.\n2) minor: do not record the overriding value into Dispatcher's\n_threadCount, since early at startup _threadCount might still be\nconstructed. Just pass the value to the task. Otherwise, the final\nconstructed value could be lost and subsequent GCs may run with reduced\nGC counts.\n\nTemporarily, keeping both old and new variant of prepareThreadsForTask()\nAPI until downstream OMR projects start using the new API.\n\nSigned-off-by: Aleksandar Micic <amicic@ca.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/685af8173bd363abfa77552dff3354bcc4129a3c"},{"sha":"068615b0704017d26ed352f1a3d43afa02d28ab4","author":{"name":"knn-k","email":"dcce18c1bceade117d2b062b1463e1670d375091@jp.ibm.com"},"message":"AArch64: Add incRegisterTotalUseCounts() to RegisterDependencyConditions\n\nThe totalUseCounts of registers in RegisterDependencyConditions were\nnot counted properly.  This commit adds a new function to\nRegisterDependencyConditions, and calls to the function.\n\nSigned-off-by: knn-k <konno@jp.ibm.com>","distinct":false,"url":"https://api.github.com/repos/aviansie-ben/omr/commits/068615b0704017d26ed352f1a3d43afa02d28ab4"}]}
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