{"push_id":2857154483,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"70e99b3383a4c7760d077cb7e6c8443cbeb2bcd8","before":"1c0d3f0a7bd218f53928aaa24c1e29cafc863170","commits":[{"sha":"68e835e9f0298f240716bcb6df0ea8c24e1497d3","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel.\n\nThe ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341605 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/68e835e9f0298f240716bcb6df0ea8c24e1497d3"},{"sha":"70e99b3383a4c7760d077cb7e6c8443cbeb2bcd8","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Add RMW ADC patterns with load in operand 1.\n\nADC is commutable and the load could be in either operand, but we were only checking operand 0.\n\nIdeally we'd mark X86adc_flag as commutable and tablegen would automatically do this, but the EFLAGS register mention is preventing it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341606 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/70e99b3383a4c7760d077cb7e6c8443cbeb2bcd8"}]}
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