{"action":"closed","issue":{"url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/9534","repository_url":"https://api.github.com/repos/RIOT-OS/RIOT","labels_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/9534/labels{/name}","comments_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/9534/comments","events_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/9534/events","html_url":"https://github.com/RIOT-OS/RIOT/issues/9534","id":339910282,"node_id":"MDU6SXNzdWUzMzk5MTAyODI=","number":9534,"title":"linkerscripts for stm32 incorrect for MCUs with non-contiguous SRAM1 & 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common linker script for stm32 based platforms doesn't take into account that on some platforms the available RAM is split up in different RAM sections e.g. SRAM1 & SRAM2. \r\nOn some MCUs there is a hardware feature to remap the address space of SRAM2 consecutively after SRAM1, there it doesn't actually impose a problem. This feature is not available on all MCUs though.\r\nOn stm32l476rg for example SRAM1 is at 0x20000000 while SRAM2 resides at 0x10000000. After SRAM1 unmapped address space is located (see [RM0351 reference manual page 73](https://www.st.com/content/ccc/resource/technical/document/reference_manual/02/35/09/0c/4f/f7/40/03/DM00083560.pdf/files/DM00083560.pdf/jcr:content/translations/en.DM00083560.pdf#page=73)).\r\n\r\nI stumbled across this when testing low power RAM retention which is only available on SRAM2 on the named MCU. \r\n\r\nAs a minimum fix the RAM_LEN value in [stm32_mem_lengths.mk](https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32_common/stm32_mem_lengths.mk) for affected platforms should be reduced to the minimum consecutively addressable amount (96K in the above case).\r\n\r\nA better fix would need to add another ram section to [cortexm.ld](https://github.com/RIOT-OS/RIOT/blob/master/cpu/cortexm_common/ldscripts/cortexm.ld) and [cortexm_base.ld](https://github.com/RIOT-OS/RIOT/blob/master/cpu/cortexm_common/ldscripts/cortexm_base.ld) and respectively additional parameters to [stm32_mem_lengths.mk](https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32_common/stm32_mem_lengths.mk). \r\n\r\nI'd like to use this Issue to collect which other MCUs are affected by this (if any) and discussion on how to properly integrate the split RAM to the linker scripts before opening up a PR. Feel free to help, of course ;)\r\n\r\n_edit_\r\nJust checked the RIOT-supported L4 MCUs.\r\n\r\nno automatic remap (problem exists):\r\nstm32l475vg (b-l475e-iot01a)\r\nstm32l476rg (nucleo-l476rg)\r\nstm32l476vg (stm32l476g-disco)\r\n\r\nautomatic remap (no problem):\r\nstm32l432kc\r\nstm32l433rc\r\nstm32l452re\r\nstm32l496zg\r\n"}}
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