{"push_id":2338657953,"size":302,"distinct_size":302,"ref":"refs/heads/master","head":"3907ea1a3b75c8e7d0a1061a47cdd6298001c362","before":"16fc83f0934d392baf98f35e7ec8d52fcb3d12d0","commits":[{"sha":"4c204e6f3f335826c6418aaada2ca8651332e46b","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"arm: helper: Factor out CP regs common to [pv]msa\n\nV6+ PMSA and VMSA share some common registers that are currently\nin the VMSA definition block. Split them out into a new def that can\nbe shared to PMSA.\n\nBackports commit 8e5d75c950a1241f6e1243c37f28cd58f68fedc9 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/4c204e6f3f335826c6418aaada2ca8651332e46b"},{"sha":"e8499a8f9b14f97babd2f68a3c2ddd8c955ee997","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"arm: Refactor get_phys_addr FSR return mechanism\n\nCurrently, the return code for get_phys_addr is overloaded for both\nsuccess/fail and FSR value return. This doesn't handle the case where\nthere is an error with a 0 FSR. This case exists in PMSAv7.\n\nSo rework get_phys_addr and friends to return a success/failure boolean\nreturn code and populate the FSR via a caller provided uint32_t\npointer.\n\nBackports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/e8499a8f9b14f97babd2f68a3c2ddd8c955ee997"},{"sha":"6f843a548408b283f60e4207e29daedd2d788110","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"arm: Implement uniprocessor with MP config\n\nAdd a boolean for indicating uniprocessors with MP extensions. This\ndrives the U bit in MPIDR. Prepares support for Cortex-R5.\n\nBackports commit a8e81b319d1ae1224cc7059877dcdf04a5aad59d from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/6f843a548408b283f60e4207e29daedd2d788110"},{"sha":"0299851aa06d4046cb95ceb992f268c4c6381443","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"arm: Add has-mpu property\n\nFor processors that support MPUs, add a property to de-feature it. This\nis similar to the implementation of the EL3 feature.\n\nThe processor definition in init sets ARM_FEATURE_MPU if it can support\nan MPU. post_init exposes the property, defaulting to true. If cleared\nby the instantiator, ARM_FEATURE_MPU is then removed at realize time.\n\nThis is to support R profile processors that may or may-not have an MPU\nconfigured.\n\nBackports commit 8f325f568fbd0158cd413e7d637573ba90b3eaab from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/0299851aa06d4046cb95ceb992f268c4c6381443"},{"sha":"c1554dbd06098906ec583c5e770e67b6ef545e40","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"arm: helper: rename get_phys_addr_mpu\n\nThis get_phys_addr is really for pmsav5. Rename it accordingly.\n\nBackports commit 13689d43646482f7305282de1bdd662c0d2b8b77 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/c1554dbd06098906ec583c5e770e67b6ef545e40"},{"sha":"13db1967927f50806ad3263c64073431c7ad67d7","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"target-arm: Correct \"preferred return address\" for cpreg access exceptions\n\nThe architecture defines that when taking an exception trying to\naccess a coprocessor register, the \"preferred return address\" for\nthe exception is the address of the instruction that caused the\nexception. Correct an off-by-4 error which meant we were returning\nthe address after the instruction for traps which happened because\nof a failure of a runtime access-check function on an AArch32\nregister. (Traps caused by translate-time checkable permissions\nfailures had the correct address, as did traps on AArch64 registers.)\n\nThis fixes https://bugs.launchpad.net/qemu/+bug/1463338\n\nBackports commit 3977ee5d7a9f2e3664dd8b233f3224694e23b62b from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/13db1967927f50806ad3263c64073431c7ad67d7"},{"sha":"93df793d4d482018888a7cb484b406bbcda8e5f5","author":{"name":"Aurelien Jarno","email":"cd2cad3dc514db80899a4324dff884235ca6b264@aurel32.net"},"message":"softmmu: provide tlb_vaddr_to_host function for user mode\n\nTo avoid to many #ifdef in target code, provide a tlb_vaddr_to_host for\nboth user and softmmu modes. In the first case the function always\nsucceed and just call the g2h function.\n\nBackports commit 2e83c496261c799b0fe6b8e18ac80cdc0a5c97ce from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/93df793d4d482018888a7cb484b406bbcda8e5f5"},{"sha":"20c2ed80a2ac294bad15b5df5749b27aea3dd527","author":{"name":"Aurelien Jarno","email":"cd2cad3dc514db80899a4324dff884235ca6b264@aurel32.net"},"message":"translate-all: fix watchpoints if retranslation not possible\n\nThe tb_check_watchpoint function currently assumes that all memory\naccess is done either directly through the TCG code or through an\nhelper which knows its return address. This is obviously wrong as the\nhelpers use cpu_ldxx/stxx_data functions to access the memory.\n\nInstead of aborting in that case, don't try to retranslate the code, but\nassume that the CPU state (and especially the program counter) has been\nsaved before calling the helper. Then invalidate the TB based on this\naddress.\n\nBackports commit 8d302e76755b8157373073d7107e31b0b13f80c1 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/20c2ed80a2ac294bad15b5df5749b27aea3dd527"},{"sha":"7ca21d4ab4e640e11d34b4056279ff611f1a152e","author":{"name":"Aurelio C. Remonda","email":"41b4179095fab6dc2aee0d19bbee83bd17f44cc8@gmail.com"},"message":"target-arm: Add the Cortex-M4 CPU\n\nThis patch adds the Cortex-M4 CPU. The M4 is basically the same as\nthe M3, the main differences being the DSP instructions and an\noptional FPU. Only no-FPU cortex-M4 is implemented here, cortex-M4F\nis not because the core target-arm code doesn't support the M-profile\nFPU model yet.\n\nBackports commit ba890a9b2509a0087bb7eafddae02ea5ecbb7bb4 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/7ca21d4ab4e640e11d34b4056279ff611f1a152e"},{"sha":"07ead14756a1428170555420db53bfa0375525e5","author":{"name":"Sergey Fedorov","email":"2617c199f233264cfa2e118da040233ad6cd74de@gmail.com"},"message":"target-arm: Do not reset sysregs marked as ALIAS\n\ncp_reg_reset() is called from g_hash_table_foreach() which does not\ndefine a specific ordering of the hash table iteration. Thus doing reset\nfor registers marked as ALIAS would give an ambiguous result when\nresetvalue is different for original and alias registers. Exit\ncp_reg_reset() early when passed an alias register. Then clean up alias\nregister definitions from needless resetvalue and resetfn.\n\nIn particular, this fixes a bug in the handling of the PMCR register,\nwhich had different resetvalues for its 32 and 64-bit views.\n\nBackports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/07ead14756a1428170555420db53bfa0375525e5"},{"sha":"7d933a6ba951246966a9b722aa8ec7c6396b0ac1","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"target-arm/helper.c: define MPUIR register\n\nDefine the MPUIR register for MPU supporting ARMv6 and onwards.\nCurrently we only support unified MPU.\n\nThe size of the unified MPU is defined via the number of \"dregions\".\nSo just a single config is added to specify this size. (When split MPU\nis implemented we will add an extra iregions config).\n\nBackports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/7d933a6ba951246966a9b722aa8ec7c6396b0ac1"},{"sha":"65f70d7a08fbc39ed88a0743f0e3638c81324f31","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"target-arm: Add registers for PMSAv7\n\nDefine the arm CP registers for PMSAv7 and their accessor functions.\nRGNR serves as a shared index that indexes into arrays storing the\nDRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd\nseparately from the CP interface using a new PMSA specific VMSD\nsubsection.\n\nBackports commit 6cb0b013a1fa421cdfb83257cd33f855cc90649a from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/65f70d7a08fbc39ed88a0743f0e3638c81324f31"},{"sha":"500d37e9b36c5dbe8a7d7770547bc19f4e8d9429","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"target-arm: Implement PMSAv7 MPU\n\nUnified MPU only. Uses ARM architecture major revision to switch\nbetween PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains\nunsupported and is asserted against.\n\nBackports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/500d37e9b36c5dbe8a7d7770547bc19f4e8d9429"},{"sha":"63e5f57bb2cbe348a7e8f22721483ee54c9ff3db","author":{"name":"Peter Crosthwaite","email":"5936add4956896b4a5091aa53ad556ae23055d30@xilinx.com"},"message":"target-arm: Add support for Cortex-R5\n\nIntroduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,\nand both thumb and ARM div instructions.\n\nAlso implement dummy ATCM and BTCM. These CPs are defined for R5 but\ndon't have a lot of meaning in QEMU yet. Raz them so the guest can\nproceed if they are read. The TCM registers will return a size of 0,\nindicating no TCM.\n\nBackports commit d6a6b13ea1dfeb25c43a648e94cfe4395906f1da from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/63e5f57bb2cbe348a7e8f22721483ee54c9ff3db"},{"sha":"0a0383e2b58be315682bd9149c6818efb52a3506","author":{"name":"Greg Ungerer","email":"0b10ca03a5cbf520aba931fb02ddaa9fa28f3f76@uclinux.org"},"message":"m68k: implement move to/from usp register instruction\n\nFill out the code support for the move to/from usp instructions. They are\nbeing decoded, but there is no code to support there actions. So add it.\n\nCurrent versions of Linux running on the ColdFire 5208 use these instructions.\n\nBackports commit 2a8327e8a8288e301a2f01bc3ca2d465a3a4ca78 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/0a0383e2b58be315682bd9149c6818efb52a3506"},{"sha":"1f6f6b2863a05d81aca16e7c616b8bdd1cb82789","author":{"name":"Greg Ungerer","email":"0b10ca03a5cbf520aba931fb02ddaa9fa28f3f76@uclinux.org"},"message":"m68k: fix usp processing on interrupt entry and exception exit\n\nThe action to potentially switch sp register is not occurring at the correct\npoint in the interrupt entry or exception exit sequences.\n\nFor the interrupt entry case the sp on entry is used to create the stack\nexception frame - but this may well be the user stack pointer, since we\nhaven't done the switch yet. Re-order the flow to switch the sp regs then\nuse the current sp to create the exception frame.\n\nFor the return from exception case the code is unwinding the sp after\nswitching sp registers. But it should always unwind the supervisor sp\nfirst, then carry out any required sp switch.\n\nNote that these problems don't effect operation unless the user sp bit is\nset in the CACR register. Only a single sp is used in the default power up\nstate. Previously Linux only used this single sp mode. But modern versions\nof Linux use the user sp mode now, so we need correct behavior for Linux\nto work.\n\nBackports commit 0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/1f6f6b2863a05d81aca16e7c616b8bdd1cb82789"},{"sha":"d544d8334814cc6d1bfd5788c42e09c0fbdeff4c","author":{"name":"Eric Blake","email":"e61e790737d449e266fd6afd4f899153a9c1e9e9@redhat.com"},"message":"qobject: Use 'bool' for qbool\n\nWe require a C99 compiler, so let's use 'bool' instead of 'int'\nwhen dealing with boolean values. There are few enough clients\nto fix them all in one pass.\n\nBackports commit fc48ffc39ed1060856475e4320d5896f26c945e8 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/d544d8334814cc6d1bfd5788c42e09c0fbdeff4c"},{"sha":"c749554a75c05c1ddc65cfb69d492c636122c108","author":{"name":"Eric Blake","email":"e61e790737d449e266fd6afd4f899153a9c1e9e9@redhat.com"},"message":"qobject: Use 'bool' inside qdict\n\nNow that qbool is fixed, let's fix getting and setting a bool\nvalue to a qdict member to also use C99 bool rather than int.\n\nI audited all callers to ensure that the changed return type\nwill not cause any changed semantics.\n\nBackports commit 34acbc95229f9f841bde83691a5af949c15e105b from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/c749554a75c05c1ddc65cfb69d492c636122c108"},{"sha":"349447b32468e9ff70c14d25766f6ce35e33aebb","author":{"name":"Markus Armbruster","email":"17e8d303f47f86a8ecdbc2cf426c9ffa4d071a8d@redhat.com"},"message":"qerror: Eliminate QERR_DEVICE_NOT_FOUND\n\nError classes other than ERROR_CLASS_GENERIC_ERROR should not be used\nin new code. Hiding them in QERR_ macros makes new uses hard to spot.\nFortunately, there's just one such macro left. Eliminate it with this\ncoccinelle semantic patch:\n\n@@\nexpression EP, E;\n@@\n-error_set(EP, QERR_DEVICE_NOT_FOUND, E)\n+error_set(EP, ERROR_CLASS_DEVICE_NOT_FOUND, \"Device '%s' not found\", E)\n\nBackports commit 75158ebbe259f0bd8bf435e8f4827a43ec89c877 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/349447b32468e9ff70c14d25766f6ce35e33aebb"},{"sha":"76c16a46c7d914842f06b38e7338615f2e0b6555","author":{"name":"Markus Armbruster","email":"17e8d303f47f86a8ecdbc2cf426c9ffa4d071a8d@redhat.com"},"message":"qerror: Clean up QERR_ macros to expand into a single string\n\nThese macros expand into error class enumeration constant, comma,\nstring. Unclean. Has been that way since commit 13f59ae.\n\nThe error class is always ERROR_CLASS_GENERIC_ERROR since the previous\ncommit.\n\n* Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and\ndelete it from the QERR_ macro. No change after preprocessing.\n\n* Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into\nerror_setg(...). Again, no change after preprocessing.\n\nBackports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu","distinct":true,"url":"https://api.github.com/repos/yuzu-emu/unicorn/commits/76c16a46c7d914842f06b38e7338615f2e0b6555"}]}
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