{"push_id":3097229196,"size":5,"distinct_size":5,"ref":"refs/heads/master","head":"e3924b1c15606bb5bf98392e0c20e731b4965311","before":"83bcdb16b4435875938f127596528b2ae36fcd18","commits":[{"sha":"3ccf8b50bf551124f5f96747d8c9278a02b52fad","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Split skylake-avx512 run lines in SLP vectorizer tests to cover -mprefer=vector-width=256 and -mprefer-vector-width=512.\n\nThis will make these tests immune if we ever change the default behavior of -march=skylake-avx512 to prefer 256 bit vectors.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348046 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/3ccf8b50bf551124f5f96747d8c9278a02b52fad"},{"sha":"b8f365e6e8b956ae1e457df754a1fcdaa1b4ca36","author":{"name":"Sanjay Patel","email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com"},"message":"[x86] add tests for undef + partial undef constant folding; NFC\n\nKeep this file sync'd with the instsimplify version (rL348045).\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348047 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/b8f365e6e8b956ae1e457df754a1fcdaa1b4ca36"},{"sha":"39a2bbdea0f8b4e9390bd418f75c56700592fdcb","author":{"name":"Nicolai Haehnle","email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com"},"message":"[DA] GPUDivergenceAnalysis for unstructured GPU kernels\n\nSummary:\nThis is patch #3 of the new DivergenceAnalysis\n\n  <https://lists.llvm.org/pipermail/llvm-dev/2018-May/123606.html>\n\nThe GPUDivergenceAnalysis is intended to eventually supersede the existing\nLegacyDivergenceAnalysis. The existing LegacyDivergenceAnalysis produces\nincorrect results on unstructured Control-Flow Graphs:\n\n  <https://bugs.llvm.org/show_bug.cgi?id=37185>\n\nThis patch adds the option -use-gpu-divergence-analysis to the\nLegacyDivergenceAnalysis to turn it into a transparent wrapper for the\nGPUDivergenceAnalysis.\n\nReviewers: nhaehnle\n\nReviewed By: nhaehnle\n\nSubscribers: jholewinski, jvesely, jfb, llvm-commits, alex-t, sameerds, arsenm, nhaehnle\n\nDifferential Revision: https://reviews.llvm.org/D53493\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348048 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/39a2bbdea0f8b4e9390bd418f75c56700592fdcb"},{"sha":"37b386de2131627f2fcb4efd062cc7a09a9ebc1a","author":{"name":"Nicolai Haehnle","email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com"},"message":"AMDGPU: Fix various issues around the VirtReg2Value mapping\n\nSummary:\nThe VirtReg2Value mapping is crucial for getting consistently\nreliable divergence information into the SelectionDAG. This\npatch fixes a bunch of issues that lead to incorrect divergence\ninfo and introduces tight assertions to ensure we don't regress:\n\n1. VirtReg2Value is generated lazily; there were some cases where\n   a lookup was performed before all relevant virtual registers were\n   created, leading to an out-of-sync mapping. Those cases were:\n\n  - Complex code to lower formal arguments that generated CopyFromReg\n    nodes from live-in registers (fixed by never querying the mapping\n    for live-in registers).\n\n  - Code that generates CopyToReg for formal arguments that are used\n    outside the entry basic block (fixed by never querying the\n    mapping for Register nodes, which don't need the divergence info\n    anyway).\n\n2. For complex values that are lowered to a sequence of registers,\n   all registers must be reflected in the VirtReg2Value mapping.\n\nI am not adding any new tests, since I'm not actually aware of any\nbugs that these problems are causing with trunk as-is. However,\nI recently added a test case (in r346423) which fails when D53283 is\napplied without this change. Also, the new assertions should provide\nmost of the effective test coverage.\n\nThere is one test change in sdwa-peephole.ll. The underlying issue\nis that since the divergence info is now correct, the DAGISel will\nselect V_OR_B32 directly instead of S_OR_B32. This leads to an extra\nCOPY which affects the behavior of MachineLICM in a way that ends up\nwith the S_MOV_B32 with the constant in a different basic block than\nthe V_OR_B32, which is presumably what defeats the peephole.\n\nReviewers: alex-t, arsenm, rampitec\n\nSubscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D54340\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348049 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/37b386de2131627f2fcb4efd062cc7a09a9ebc1a"},{"sha":"e3924b1c15606bb5bf98392e0c20e731b4965311","author":{"name":"Nicolai Haehnle","email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com"},"message":"AMDGPU: Divergence-driven selection of scalar buffer load intrinsics\n\nSummary:\nMoving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if\nthe load is really uniform. So select the scalar load intrinsics directly\nto either VMEM or SMRD buffer loads based on divergence analysis.\n\nIf an offset happens to end up in a VGPR -- either because a floating\npoint calculation was involved, or due to other remaining deficiencies\nin SIFixSGPRCopies -- we use v_readfirstlane.\n\nThere is some unrelated churn in tests since we now select MUBUF offsets\nin a unified way with non-scalar buffer loads.\n\nChange-Id: I170e6816323beb1348677b358c9d380865cd1a19\n\nReviewers: arsenm, alex-t, rampitec, tpr\n\nSubscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D53283\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348050 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/e3924b1c15606bb5bf98392e0c20e731b4965311"}]}
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