{"action":"created","issue":{"url":"https://api.github.com/repos/riscv/riscv-tools/issues/77","repository_url":"https://api.github.com/repos/riscv/riscv-tools","labels_url":"https://api.github.com/repos/riscv/riscv-tools/issues/77/labels{/name}","comments_url":"https://api.github.com/repos/riscv/riscv-tools/issues/77/comments","events_url":"https://api.github.com/repos/riscv/riscv-tools/issues/77/events","html_url":"https://github.com/riscv/riscv-tools/issues/77","id":230229600,"number":77,"title":"Error while building the tools","user":{"login":"kllbrd","id":26334457,"avatar_url":"https://avatars0.githubusercontent.com/u/26334457?v=4","gravatar_id":"","url":"https://api.github.com/users/kllbrd","html_url":"https://github.com/kllbrd","followers_url":"https://api.github.com/users/kllbrd/followers","following_url":"https://api.github.com/users/kllbrd/following{/other_user}","gists_url":"https://api.github.com/users/kllbrd/gists{/gist_id}","starred_url":"https://api.github.com/users/kllbrd/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/kllbrd/subscriptions","organizations_url":"https://api.github.com/users/kllbrd/orgs","repos_url":"https://api.github.com/users/kllbrd/repos","events_url":"https://api.github.com/users/kllbrd/events{/privacy}","received_events_url":"https://api.github.com/users/kllbrd/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2017-05-21T15:51:26Z","updated_at":"2018-02-03T01:07:23Z","closed_at":"2018-02-03T01:07:23Z","author_association":"NONE","body":"[root@localhost riscv-tools]# ./build.sh\r\nStarting RISC-V Toolchain build process\r\n\r\nRemoving existing riscv-openocd/build directory\r\nConfiguring project riscv-openocd\r\nlibtoolize:   error: 'build-aux/config.guess' is newer: use '--force' to overwrite\r\nlibtoolize:   error: 'build-aux/config.sub' is newer: use '--force' to overwrite\r\nBuilding project riscv-openocd\r\n../../../src/target/riscv/riscv-013.c: In function ‘assert_reset’:\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1158:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1158:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1161:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1161:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c: In function ‘deassert_reset’:\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1186:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1186:15: note: in expansion of macro ‘set_field’\r\n     control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n               ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c: In function ‘riscv013_halt_current_hart’:\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1700:14: note: in expansion of macro ‘set_field’\r\n  dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);\r\n              ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1700:14: note: in expansion of macro ‘set_field’\r\n  dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);\r\n              ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1716:14: note: in expansion of macro ‘set_field’\r\n  dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);\r\n              ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1716:14: note: in expansion of macro ‘set_field’\r\n  dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);\r\n              ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c: In function ‘riscv013_reset_current_hart’:\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1856:13: note: in expansion of macro ‘set_field’\r\n   control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n             ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1856:13: note: in expansion of macro ‘set_field’\r\n   control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);\r\n             ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1864:13: note: in expansion of macro ‘set_field’\r\n   control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);\r\n             ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1864:13: note: in expansion of macro ‘set_field’\r\n   control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);\r\n             ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c: In function ‘riscv013_set_autoexec’:\r\n../../../src/target/riscv/riscv-013.c:71:69: error: left shift of negative value [-Werror=shift-negative-value]\r\n #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))\r\n                                                                     ^\r\n../../../src/target/riscv/riscv-013.c:1982:21: note: in expansion of macro ‘get_field’\r\n   uint32_t aa_aed = get_field(aa, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);\r\n                     ^~~~~~~~~\r\n../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]\r\n t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))\r\n                                                                           ^\r\n../../../src/target/riscv/riscv-013.c:1985:8: note: in expansion of macro ‘set_field’\r\n   aa = set_field(aa, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, aa_aed);\r\n        ^~~~~~~~~\r\ncc1: all warnings being treated as errors\r\ngmake[6]: *** [riscv/riscv-013.lo] Error 1\r\ngmake[5]: *** [all-recursive] Error 1\r\ngmake[4]: *** [all] Error 2\r\ngmake[3]: *** [all-recursive] Error 1\r\ngmake[2]: *** [all] Error 2\r\ngmake[1]: *** [all-recursive] Error 1\r\ngmake: *** [all] Error 2\r\n\r\nany help would be appreciated, \r\nthanks"},"comment":{"url":"https://api.github.com/repos/riscv/riscv-tools/issues/comments/362757360","html_url":"https://github.com/riscv/riscv-tools/issues/77#issuecomment-362757360","issue_url":"https://api.github.com/repos/riscv/riscv-tools/issues/77","id":362757360,"user":{"login":"jim-wilson","id":11654017,"avatar_url":"https://avatars0.githubusercontent.com/u/11654017?v=4","gravatar_id":"","url":"https://api.github.com/users/jim-wilson","html_url":"https://github.com/jim-wilson","followers_url":"https://api.github.com/users/jim-wilson/followers","following_url":"https://api.github.com/users/jim-wilson/following{/other_user}","gists_url":"https://api.github.com/users/jim-wilson/gists{/gist_id}","starred_url":"https://api.github.com/users/jim-wilson/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jim-wilson/subscriptions","organizations_url":"https://api.github.com/users/jim-wilson/orgs","repos_url":"https://api.github.com/users/jim-wilson/repos","events_url":"https://api.github.com/users/jim-wilson/events{/privacy}","received_events_url":"https://api.github.com/users/jim-wilson/received_events","type":"User","site_admin":false},"created_at":"2018-02-03T01:07:22Z","updated_at":"2018-02-03T01:07:22Z","author_association":"COLLABORATOR","body":"This was apparently fixed by the change Palmer merged in."}}
{"actor":{"display_login":"jim-wilson"}}