{"action":"created","issue":{"url":"https://api.github.com/repos/potentialventures/cocotb/issues/611","repository_url":"https://api.github.com/repos/potentialventures/cocotb","labels_url":"https://api.github.com/repos/potentialventures/cocotb/issues/611/labels{/name}","comments_url":"https://api.github.com/repos/potentialventures/cocotb/issues/611/comments","events_url":"https://api.github.com/repos/potentialventures/cocotb/issues/611/events","html_url":"https://github.com/potentialventures/cocotb/issues/611","id":320084274,"number":611,"title":"cocotb and RTL that uses altsyncram","user":{"login":"Fatsie","id":11200448,"avatar_url":"https://avatars2.githubusercontent.com/u/11200448?v=4","gravatar_id":"","url":"https://api.github.com/users/Fatsie","html_url":"https://github.com/Fatsie","followers_url":"https://api.github.com/users/Fatsie/followers","following_url":"https://api.github.com/users/Fatsie/following{/other_user}","gists_url":"https://api.github.com/users/Fatsie/gists{/gist_id}","starred_url":"https://api.github.com/users/Fatsie/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Fatsie/subscriptions","organizations_url":"https://api.github.com/users/Fatsie/orgs","repos_url":"https://api.github.com/users/Fatsie/repos","events_url":"https://api.github.com/users/Fatsie/events{/privacy}","received_events_url":"https://api.github.com/users/Fatsie/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":5,"created_at":"2018-05-03T21:21:15Z","updated_at":"2018-05-09T22:45:12Z","closed_at":null,"author_association":"NONE","body":"I am trying to get a testbench going with RTL that uses altsyncram block RAM. But it does not seem to work.\r\nThe makefile: [Makefile_altera](https://github.com/potentialventures/cocotb/files/1972667/Makefile_altera.txt)\r\nThe output: [output.log](https://github.com/potentialventures/cocotb/files/1972687/output.log)\r\n\r\nI am using modelsim that is delivered with Quartus Prime Lite 17.1; cocotb is installed from pypi with pip.\r\nAnybody ideas to get it working ?\r\n\r\n(I am actually porting the RTL to use of generic RAM but would like test that the two implementation behave the same)."},"comment":{"url":"https://api.github.com/repos/potentialventures/cocotb/issues/comments/387897539","html_url":"https://github.com/potentialventures/cocotb/issues/611#issuecomment-387897539","issue_url":"https://api.github.com/repos/potentialventures/cocotb/issues/611","id":387897539,"user":{"login":"elgorwi","id":8214162,"avatar_url":"https://avatars3.githubusercontent.com/u/8214162?v=4","gravatar_id":"","url":"https://api.github.com/users/elgorwi","html_url":"https://github.com/elgorwi","followers_url":"https://api.github.com/users/elgorwi/followers","following_url":"https://api.github.com/users/elgorwi/following{/other_user}","gists_url":"https://api.github.com/users/elgorwi/gists{/gist_id}","starred_url":"https://api.github.com/users/elgorwi/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/elgorwi/subscriptions","organizations_url":"https://api.github.com/users/elgorwi/orgs","repos_url":"https://api.github.com/users/elgorwi/repos","events_url":"https://api.github.com/users/elgorwi/events{/privacy}","received_events_url":"https://api.github.com/users/elgorwi/received_events","type":"User","site_admin":false},"created_at":"2018-05-09T22:45:12Z","updated_at":"2018-05-09T22:45:12Z","author_association":"CONTRIBUTOR","body":"Looking at the log file, it seems modelsim has found some unconnected ports in memory_registers_altera.v. You probably want to check the instantiation of altsyncram and set any unused input ports to an appropriate value (eg. '0).\r\n\r\nI have also checked my local modelsim.ini and it looks like altera_mf_ver is mapped to the verilog version of the libs and altera_mf is mapped to the vhdl version of the libs. You can try changing your makefile to:\r\nVSIM_ARGS := -L altera_mf_ver\r\n"}}
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