{"push_id":2474255970,"size":1,"distinct_size":1,"ref":"refs/heads/wip-local-interrupts","head":"58559f97538aa6f2dcf93e697e1b6fa010ce203f","before":"0882030b703366f187e96e5113ef4be6e9a493d8","commits":[{"sha":"58559f97538aa6f2dcf93e697e1b6fa010ce203f","author":{"name":"Michael Clark","email":"835e254f7e4e78ce79054bd4f71f95af7f9c99e2@sifive.com"},"message":"RISC-V: Implement atomic CSR access to mstatus.mip\n\nUse the new CSR read/modify/write interface to implement\natomic access to mstatus.mip and mstatus.sip. This change\nallows mip writes to atomically update the SEIP bit so the\nhelpers are changed to use the delegable_ints constant.\n\nSigned-off-by: Michael Clark <mjc@sifive.com>","distinct":true,"url":"https://api.github.com/repos/michaeljclark/riscv-qemu/commits/58559f97538aa6f2dcf93e697e1b6fa010ce203f"}]}
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