{"push_id":3033971137,"size":2,"distinct_size":2,"ref":"refs/heads/nexell","head":"d5488d047012af7a84cae5f176f5ac36e76cdef0","before":"a516720fd5571a6eb295bcadafc2baf6495a6a08","commits":[{"sha":"bb32a2496506963a292aee48368d2402bae0bd10","author":{"name":"suker","email":"90e83096000af0dbfa1406f47324a6bb2e31ea4d@nexell.co.kr"},"message":"risc-v: bl1: boot complete\n\nThis patch is about riscv-bl1 boot complete codes update.\nThis patch include a scheme which DRAM clock down from 200Mhz to 100Mhz.\n\nChange-Id: Iec04d3cc6d975834c1e927651f948cf118c0c763\nSigned-off-by: suker <suker@nexell.co.kr>\nReviewed-on: https://review.gerrithub.io/432370\nReviewed-by: Sungwoo Park <psw0523@gmail.com>\nTested-by: Sungwoo Park <psw0523@gmail.com>","distinct":true,"url":"https://api.github.com/repos/swallow-riscv/nexell_swallow_riscv-bl1/commits/bb32a2496506963a292aee48368d2402bae0bd10"},{"sha":"d5488d047012af7a84cae5f176f5ac36e76cdef0","author":{"name":"Hyunseok Jung","email":"fcd56dc1a0b4916cf7872284bd3a63b0f010b0eb@nexell.co.kr"},"message":"risc-v: bl1: clear csr and enable uart rx\n\nThis patch clear csr and enable uart rx.\n\nChange-Id: I499b1e02ff9205571c5527e99c6d1ec5c34c3571\nSigned-off-by: Hyunseok Jung <hsjung@nexell.co.kr>\nReviewed-on: https://review.gerrithub.io/432520\nReviewed-by: Sungwoo Park <psw0523@gmail.com>\nTested-by: Sungwoo Park <psw0523@gmail.com>","distinct":true,"url":"https://api.github.com/repos/swallow-riscv/nexell_swallow_riscv-bl1/commits/d5488d047012af7a84cae5f176f5ac36e76cdef0"}]}
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