{"push_id":2784857054,"size":6,"distinct_size":6,"ref":"refs/heads/master","head":"e840ab91add5b1eee4125e07a943715b23acb311","before":"e423010b5ba3538e5d82990ad291696de0b37487","commits":[{"sha":"b67aa23318ccfb2f007418f0079452983ccbc75c","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"DRIVERS: rtc: Make PL031 driver Xvisor specific\n\nWe have lot of our changes in PL031 driver hence no point in\nkeeping in Linux-like driver. This patch makes PL031 driver\ntotally Xvisor specific.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/b67aa23318ccfb2f007418f0079452983ccbc75c"},{"sha":"3f4b1e93c84681ec902b4f9ce8b76642bb8023b7","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"ARM: Fix MPIDR of boot CPU in arch_smp_init_cpus()\n\nWe cannot simply assume that MPIDR of boot CPU will be\nreg property of first child DT node under /cpus DT node\nbecause any CPU can be the boot CPU.\n\nThis patch fixes arch_smp_init_cpus() to lookup correct\nDT node for boot CPU based of MPIDR register of boot CPU.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/3f4b1e93c84681ec902b4f9ce8b76642bb8023b7"},{"sha":"041b36906acf58f598afbaea797b79630a085bd3","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"CORE: vmm_host_irq: Initialize default affinity before desc init\n\nThe __vmm_host_irq_init_desc() uses default affinity\nhence we should initialize default affinity before\nusing __vmm_host_irq_init_desc().\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/041b36906acf58f598afbaea797b79630a085bd3"},{"sha":"4a47b1df1e6528590162d326232023ccf8605647","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"DRIVERS: irqchip: Track target HART and mode for each PLIC context\n\nA PLIC context is connected to targe HART and mode hence we should\ntrack both HART ID and mode for each PLIC context.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/4a47b1df1e6528590162d326232023ccf8605647"},{"sha":"f336f48481485adb72b3cf7a8939f489fe9bfc1f","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"RISCV: Use RISCV_PTR macro instead of .dword in assembly\n\nWe should use RISCV_PTR macro instead of .dword in RISC-V\nassembly code.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/f336f48481485adb72b3cf7a8939f489fe9bfc1f"},{"sha":"e840ab91add5b1eee4125e07a943715b23acb311","author":{"name":"Anup Patel","email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org"},"message":"RISCV: Fix HARTID of boot CPU in arch_smp_init_cpus()\n\nWe cannot simply assume that HART ID of boot CPU will be\nreg property of first child DT node under /cpus DT node\nbecause any CPU can win the boot-time lottery and become\nboot CPU.\n\nThis patch fixes arch_smp_init_cpus() to lookup correct\nDT node for boot CPU based of HART ID passed by bootloader\nin \"a0\" register.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":true,"url":"https://api.github.com/repos/avpatel/xvisor-next/commits/e840ab91add5b1eee4125e07a943715b23acb311"}]}
{"actor":{"display_login":"avpatel"}}