{"push_id":2852529991,"size":26,"distinct_size":1,"ref":"refs/heads/terms","head":"6bbc78068210dd450b6201cdbf60810f76eb8fe6","before":"33fb913e94e127637c07835050599b0334026e0a","commits":[{"sha":"2d7d3d0c1e933f863f78b2d07934c12d7081d171","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Fix typo in data0 definition.\n\nFixes #312.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/2d7d3d0c1e933f863f78b2d07934c12d7081d171"},{"sha":"f4bd15fe51afce5d1c4baafe90fadaaacbe847f0","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Define cmderr for non-existent register access. (#325)\n\nFixes #317.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/f4bd15fe51afce5d1c4baafe90fadaaacbe847f0"},{"sha":"6d60ad996d4b3ab125964529cfc53b5d99687c26","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Rebuild PDF","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/6d60ad996d4b3ab125964529cfc53b5d99687c26"},{"sha":"a14d8686dfdafa12e2855d96a8a0c39734c8b4a7","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Allow extra harts to be reset. (#330)\n\n* Allow extra harts to be reset.\r\n\r\nBased on feedback by Allen that resetting just one hart in a multi-hart\r\ncore can be complex/poorly defined, depending on implementation.\r\n\r\n* Remove halt-on-reset requirement for extra harts.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/a14d8686dfdafa12e2855d96a8a0c39734c8b4a7"},{"sha":"b51c6dbeaf56f6c17f9acce302b985820a87adba","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Clarify ebreak behavior when ebreak* are 0. (#311)","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/b51c6dbeaf56f6c17f9acce302b985820a87adba"},{"sha":"81df032860364c76be2a8384353212034dcecbab","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Explain what we mean by Preset. (#323)","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/81df032860364c76be2a8384353212034dcecbab"},{"sha":"57df3f3b0a1a374f262198740565a27ee7d2e75e","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"\\Rcommand is not readable. (#328)\n\nFixes #313.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/57df3f3b0a1a374f262198740565a27ee7d2e75e"},{"sha":"2ca20aa33f72c6023e865cf4931de747529abf35","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"clrresethaltreq trumps setresethaltreq (#332)\n\nFixes #319.\r\n\r\nAlso explain why there are separate bits in the first place, and make\r\nthem both W1.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/2ca20aa33f72c6023e865cf4931de747529abf35"},{"sha":"45b7636b8e674bb0a9ae3daa7391fc3891304ad3","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Clearing hasel does not clear the ha mask reg. (#327)","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/45b7636b8e674bb0a9ae3daa7391fc3891304ad3"},{"sha":"762d30875db7f0d1031bf31d5f16212ab9b2e48c","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Add aarpostincrement to abstract register access. (#333)\n\nThis enables batch reading/writing of consecutively numbered registers.\r\n\r\nImplements #250.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/762d30875db7f0d1031bf31d5f16212ab9b2e48c"},{"sha":"fd5cf6225f10f2e54bf101b4ce2e4fa6a5d24e64","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Triggers do not fire in Debug Mode. (#335)","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/fd5cf6225f10f2e54bf101b4ce2e4fa6a5d24e64"},{"sha":"497352c202ffc7943984cdcc60118f00d078fa0c","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Side effects happen for abstract register accesses (#334)\n\nClarifies #318.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/497352c202ffc7943984cdcc60118f00d078fa0c"},{"sha":"19058ef9e6f178a9abf267216c5affcf06047c34","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Clarify that resumereq is not level-sensitive. (#321)\n\n* Clarify that resumereq is edge-sensitive.\r\n\r\n* Make haltreq/resumereq more consistent.\r\n\r\nAlso clarify ackhavereset.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/19058ef9e6f178a9abf267216c5affcf06047c34"},{"sha":"b52d9fe76c28c504d9b11ff99b5f705080094167","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Allow control xfers in progbuf to act as illegal. (#331)\n\nThis is an alternate proposal to #329, which fixing #314 in a different\r\nway.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/b52d9fe76c28c504d9b11ff99b5f705080094167"},{"sha":"13d5c08e84b42c95e48adba03507af636e9936ec","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Thank John Hauser.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/13d5c08e84b42c95e48adba03507af636e9936ec"},{"sha":"0f120c069189733078532d6629daf4ef5168eb55","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Solution to native triggers in M mode only systems (#309)\n\n* Solution to native triggers in M mode only systems\r\n\r\nThis came out of today's debug call.\r\n\r\n* Incorporate feedback.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/0f120c069189733078532d6629daf4ef5168eb55"},{"sha":"e967b3b68f1faf1935ce7d06de9fd7acd094b35b","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"mprven may be tied high or low. (#339)\n\n* mprven may be tied high or low.\r\n\r\n* Make mprven WARL.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/e967b3b68f1faf1935ce7d06de9fd7acd094b35b"},{"sha":"6bd15ac7646bf2e950184303972fb715c1077afe","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Be more clear about running signal. (#338)\n\nHelps with #336.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/6bd15ac7646bf2e950184303972fb715c1077afe"},{"sha":"ff0941857f357b691d876f6fe60ae97b3548159f","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Rebuild PDF.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/ff0941857f357b691d876f6fe60ae97b3548159f"},{"sha":"0fb41b973bacf9885774a5a58ac3019fff9bac20","author":{"name":"Tim Newsome","email":"5ee0edb9e2229c0838f1959779f1949031de0123@sifive.com"},"message":"Don't change step/stepie while running. (#340)\n\nThis is an alternate to #326.","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-debug-spec/commits/0fb41b973bacf9885774a5a58ac3019fff9bac20"}]}
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