{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/10","repository_url":"https://api.github.com/repos/ucb-bar/chisel-testers2","labels_url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/10/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/10/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/10/events","html_url":"https://github.com/ucb-bar/chisel-testers2/issues/10","id":394520529,"node_id":"MDU6SXNzdWUzOTQ1MjA1Mjk=","number":10,"title":"[Proposal] Add optional timeout to (en|de)queue","user":{"login":"nhynes","id":2353785,"node_id":"MDQ6VXNlcjIzNTM3ODU=","avatar_url":"https://avatars2.githubusercontent.com/u/2353785?v=4","gravatar_id":"","url":"https://api.github.com/users/nhynes","html_url":"https://github.com/nhynes","followers_url":"https://api.github.com/users/nhynes/followers","following_url":"https://api.github.com/users/nhynes/following{/other_user}","gists_url":"https://api.github.com/users/nhynes/gists{/gist_id}","starred_url":"https://api.github.com/users/nhynes/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/nhynes/subscriptions","organizations_url":"https://api.github.com/users/nhynes/orgs","repos_url":"https://api.github.com/users/nhynes/repos","events_url":"https://api.github.com/users/nhynes/events{/privacy}","received_events_url":"https://api.github.com/users/nhynes/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2018-12-28T01:01:58Z","updated_at":"2018-12-30T21:39:49Z","closed_at":null,"author_association":"CONTRIBUTOR","body":"Setting a maximum number of cycles would prevent infinite loops when testing buggy circuits."},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/comments/450588410","html_url":"https://github.com/ucb-bar/chisel-testers2/issues/10#issuecomment-450588410","issue_url":"https://api.github.com/repos/ucb-bar/chisel-testers2/issues/10","id":450588410,"node_id":"MDEyOklzc3VlQ29tbWVudDQ1MDU4ODQxMA==","user":{"login":"nhynes","id":2353785,"node_id":"MDQ6VXNlcjIzNTM3ODU=","avatar_url":"https://avatars2.githubusercontent.com/u/2353785?v=4","gravatar_id":"","url":"https://api.github.com/users/nhynes","html_url":"https://github.com/nhynes","followers_url":"https://api.github.com/users/nhynes/followers","following_url":"https://api.github.com/users/nhynes/following{/other_user}","gists_url":"https://api.github.com/users/nhynes/gists{/gist_id}","starred_url":"https://api.github.com/users/nhynes/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/nhynes/subscriptions","organizations_url":"https://api.github.com/users/nhynes/orgs","repos_url":"https://api.github.com/users/nhynes/repos","events_url":"https://api.github.com/users/nhynes/events{/privacy}","received_events_url":"https://api.github.com/users/nhynes/received_events","type":"User","site_admin":false},"created_at":"2018-12-30T21:39:49Z","updated_at":"2018-12-30T21:39:49Z","author_association":"CONTRIBUTOR","body":"> timeout by idle cycles\r\n\r\nI like that better actually. I'm not quite seeing anything in treadle that would expose whether the circuit state changed, but I also didn't look too deeply.\r\n\r\n> real-time constraints\r\n\r\nLike if I have a specification that states that `output.valid` is asserted `x` cycles after `input.valid`. The [Xilinx DMA IP Spec Table 2-2](https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf#G5.425382) is an example.\r\n\r\nhttps://github.com/ucb-bar/chisel-testers2/pull/11 shows an example of how a simple global per-clock limit would work."}}
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