{"action":"created","issue":{"url":"https://api.github.com/repos/dgschwend/zynqnet/issues/43","repository_url":"https://api.github.com/repos/dgschwend/zynqnet","labels_url":"https://api.github.com/repos/dgschwend/zynqnet/issues/43/labels{/name}","comments_url":"https://api.github.com/repos/dgschwend/zynqnet/issues/43/comments","events_url":"https://api.github.com/repos/dgschwend/zynqnet/issues/43/events","html_url":"https://github.com/dgschwend/zynqnet/issues/43","id":312892949,"number":43,"title":"Questions about the results of output on FPGA","user":{"login":"lishen565","id":1812302,"avatar_url":"https://avatars0.githubusercontent.com/u/1812302?v=4","gravatar_id":"","url":"https://api.github.com/users/lishen565","html_url":"https://github.com/lishen565","followers_url":"https://api.github.com/users/lishen565/followers","following_url":"https://api.github.com/users/lishen565/following{/other_user}","gists_url":"https://api.github.com/users/lishen565/gists{/gist_id}","starred_url":"https://api.github.com/users/lishen565/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/lishen565/subscriptions","organizations_url":"https://api.github.com/users/lishen565/orgs","repos_url":"https://api.github.com/users/lishen565/repos","events_url":"https://api.github.com/users/lishen565/events{/privacy}","received_events_url":"https://api.github.com/users/lishen565/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":17,"created_at":"2018-04-10T12:05:17Z","updated_at":"2018-04-19T13:55:32Z","closed_at":null,"author_association":"NONE","body":"Hi, I've run the zynqnet on Xilinx ZC706 successfully.  The result of top-5 is puzzling me though\r\n I've set the AXI HP port to 32 bits. Did you meet this situation before ? Thanks a lot.\r\n![4](https://user-images.githubusercontent.com/1812302/38555913-7a98a49a-3cfa-11e8-8a22-0792639f195f.PNG)\r\n"},"comment":{"url":"https://api.github.com/repos/dgschwend/zynqnet/issues/comments/382745148","html_url":"https://github.com/dgschwend/zynqnet/issues/43#issuecomment-382745148","issue_url":"https://api.github.com/repos/dgschwend/zynqnet/issues/43","id":382745148,"user":{"login":"wangj346","id":28952216,"avatar_url":"https://avatars2.githubusercontent.com/u/28952216?v=4","gravatar_id":"","url":"https://api.github.com/users/wangj346","html_url":"https://github.com/wangj346","followers_url":"https://api.github.com/users/wangj346/followers","following_url":"https://api.github.com/users/wangj346/following{/other_user}","gists_url":"https://api.github.com/users/wangj346/gists{/gist_id}","starred_url":"https://api.github.com/users/wangj346/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/wangj346/subscriptions","organizations_url":"https://api.github.com/users/wangj346/orgs","repos_url":"https://api.github.com/users/wangj346/repos","events_url":"https://api.github.com/users/wangj346/events{/privacy}","received_events_url":"https://api.github.com/users/wangj346/received_events","type":"User","site_admin":false},"created_at":"2018-04-19T13:55:32Z","updated_at":"2018-04-19T13:55:32Z","author_association":"NONE","body":"@lishen565 hello lishen, I am having the same try with the zc706 board in our student project, but I ran the './test FPGA indata.ini' in the _FIRMWARE folder after 'sudo make' and the FPGA sacked after ran the command. Have you met the same problems before? (I used the auto assign address tool of vivado when create the IP core)\r\nWould you like to share your successful project? I'd really appreciate it if you would contact me or give any suggestions.\r\nmy email:w280400191@hotmail.com\r\nbest wishes"}}
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