{"push_id":2995354611,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"d537a8485f5ff7676e5a03cc33ea2d700372bb95","before":"fc13e795f2aeb39ea0ee268483c51a3bfd1d0826","commits":[{"sha":"d537a8485f5ff7676e5a03cc33ea2d700372bb95","author":{"name":"Lei Huang","email":"a56ad06d45d77b573aa90c400a44067fdaceabf8@ca.ibm.com"},"message":"[PowerPC] Improve BUILD_VECTOR of 4 i32s\n\nCurrently, for this node:\n  vector int test(int a, int b, int c, int d) {\n    return (vector int) { a, b, c, d };\n  }\n\nwe get this on Power9:\n  mtvsrdd 34, 5, 3\n  mtvsrdd 35, 6, 4\n  vmrgow 2, 3, 2\n\nand this on Power8:\n  mtvsrwz 0, 3\n  mtvsrwz 1, 5\n  mtvsrwz 2, 4\n  mtvsrwz 3, 6\n  xxmrghd 34, 1, 0\n  xxmrghd 35, 3, 2\n  vmrgow 2, 3, 2\n\nThis can be improved to this on LE Power9:\n  rldimi 3, 4, 32, 0\n  rldimi 5, 6, 32, 0\n  mtvsrdd 34, 5, 3\n\nand this on LE Power8\n  rldimi 3, 4, 32, 0\n  rldimi 5, 6, 32, 0\n  mtvsrd 34, 3\n  mtvsrd 35, 5\n  xxpermdi 34, 35, 34, 0\n\nThis patch updates the TD pattern to generate the optimized sequence for both\nPower8 and Power9 on LE and BE.\n\nDifferential Revision: https://reviews.llvm.org/D53494\n\nllvm-svn=345414","distinct":true,"url":"https://api.github.com/repos/llvm-git-prototype/llvm/commits/d537a8485f5ff7676e5a03cc33ea2d700372bb95"}]}
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