{"push_id":2550031479,"size":71,"distinct_size":0,"ref":"refs/heads/master","head":"e5cd695266c5709308aa95b1baae499e4b5d4544","before":"c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9","commits":[{"sha":"6d9c1b8dbb3527258bbc473aa3a9b02c6a86c506","author":{"name":"Jan Kiszka","email":"a5b45c9af271d077f30d36aa7d9b988eed9d56eb@siemens.com"},"message":"hw/arm/virt: Add linux,pci-domain property\n\nThis allows to pin the host controller in the Linux PCI domain space.\nLinux requires that property to be available consistently or not at all,\nin which case the domain number becomes unstable on additions/removals.\nAdding it here won't make a difference in practice for most setups as we\nonly expose one controller.\n\nHowever, enabling Jailhouse on top may introduce another controller, and\nthat one would like to have stable address as well. So the property is\nneeded for the first controller as well.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>\nMessage-id: 3301c5bc-7b47-1b0e-8ce4-30435057a276@web.de\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/6d9c1b8dbb3527258bbc473aa3a9b02c6a86c506"},{"sha":"100061121c1f69a672ce7bb3e9e3781f8018f9f6","author":{"name":"Mathew Maidment","email":"f9791342c5930d053862397861a8fffa7bc4f6aa@gmail.com"},"message":"target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() conditional case\n\nThe duplication of id_tlbtr_reginfo was unintentionally added within\n3281af8114c6b8ead02f08b58e3c36895c1ea047 which should have been\nid_mpuir_reginfo.\n\nThe effect was that for OMAP and StrongARM CPUs we would\nincorrectly UNDEF writes to MPUIR rather than NOPing them.\n\nSigned-off-by: Mathew Maidment <mathew1800@gmail.com>\nMessage-id: 20180501184933.37609-2-mathew1800@gmail.com\n[PMM: tweak commit message]\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/100061121c1f69a672ce7bb3e9e3781f8018f9f6"},{"sha":"0c6a108ec1efd8498b281086d44604204196a9d5","author":{"name":"Patrick Oppenlander","email":"c891d7b774adbbd583b1c0d37c08327fa8b0f587@gmail.com"},"message":"hw/char/cmsdk-apb-uart.c: Accept more input after character read\n\nThe character frontend needs to be notified that the uart receive buffer\nis empty and ready to handle another character.\n\nPreviously, the uart only worked correctly when receiving one character\nat a time.\n\nSigned-off-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>\nMessage-id: CAEg67GkRTw=cXei3o9hvpxG_L4zSrNzR0bFyAgny+sSEUb_kPw@mail.gmail.com\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0c6a108ec1efd8498b281086d44604204196a9d5"},{"sha":"a22cadbefd2b2ff57f5c06688f7ed06c52d6929a","author":{"name":"Peter Maydell","email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org"},"message":"hw/usb/tusb6010: Convert away from old_mmio\n\nConvert the tusb6010 device away from using the old_mmio field\nof MemoryRegionOps. This device is used only in the n800 and n810\nboards.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 20180427173611.10281-2-peter.maydell@linaro.org","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/a22cadbefd2b2ff57f5c06688f7ed06c52d6929a"},{"sha":"50a22d0de84955692a5f31134d88c1e8fea80247","author":{"name":"Peter Maydell","email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org"},"message":"hw/net/smc91c111: Convert away from old_mmio\n\nConvert the smc91c111 device away from using the old_mmio field of\nMemoryRegionOps. This device is used by several Arm board models.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 20180427173611.10281-3-peter.maydell@linaro.org","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/50a22d0de84955692a5f31134d88c1e8fea80247"},{"sha":"0c9492765a56c1547dc7edf56971c97685354fe4","author":{"name":"Igor Mammedov","email":"376726f239c919d31d97c9332191663ab16d47b5@redhat.com"},"message":"arm: boot: set boot_info starting from first_cpu\n\nEven though nothing is currently broken (since all boards\nuse first_cpu as boot cpu), make sure that boot_info is set\non all CPUs.\nIf some board would like support heterogenuos setup (i.e.\ninit boot_info on subset of CPUs) in future, it should add\na reasonable API to do it, instead of starting assigning\nboot_info from some CPU and till the end of present CPUs\nlist.\n\nRef:\n\"Message-ID: <CAFEAcA_NMWuA8WSs3cNeY6xX1kerO_uAcN_3=fK02BEhHJW86g@mail.gmail.com>\"\n\nSigned-off-by: Igor Mammedov <imammedo@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1525176522-200354-5-git-send-email-imammedo@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0c9492765a56c1547dc7edf56971c97685354fe4"},{"sha":"8dae46970532afcf93470b00e83ca9921980efc3","author":{"name":"Richard Henderson","email":"641039872457cf7d26c8010228bc48b428501525@linaro.org"},"message":"target/arm: Tidy conditions in handle_vec_simd_shri\n\nThe (size > 3 && !is_q) condition is identical to the preceeding test\nof bit 3 in immh; eliminate it.  For the benefit of Coverity, assert\nthat size is within the bounds we expect.\n\nFixes: Coverity CID1385846\nFixes: Coverity CID1385849\nFixes: Coverity CID1385852\nFixes: Coverity CID1385857\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-id: 20180501180455.11214-2-richard.henderson@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/8dae46970532afcf93470b00e83ca9921980efc3"},{"sha":"a8766e3172c1671cab297c1ef4566a3c5d094822","author":{"name":"Richard Henderson","email":"641039872457cf7d26c8010228bc48b428501525@linaro.org"},"message":"target/arm: Tidy condition in disas_simd_two_reg_misc\n\nPath analysis shows that size == 3 && !is_q has been eliminated.\n\nFixes: Coverity CID1385853\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-id: 20180501180455.11214-3-richard.henderson@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/a8766e3172c1671cab297c1ef4566a3c5d094822"},{"sha":"a82929a251481af1467569810ec309b57558f7fe","author":{"name":"Thomas Huth","email":"9e65be74847981e55b2564b6266c57d86d3bac05@redhat.com"},"message":"hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode\n\nWhen running omap1/2 or pxa2xx based ARM machines with -nodefaults,\nthey bail out immediately complaining about a \"missing SecureDigital\ndevice\". That's not how the \"default\" devices in vl.c are meant to\nwork - it should be possible for a board to also start up without\ndefault devices. So let's turn the error message and exit() into\na warning instead.\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nMessage-id: 1525326811-3233-1-git-send-email-thuth@redhat.com\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/a82929a251481af1467569810ec309b57558f7fe"},{"sha":"b1e5336a9899016c53d59eba53ebf6abcc21995c","author":{"name":"Peter Maydell","email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org"},"message":"target/arm: Implement v8M VLLDM and VLSTM\n\nFor v8M the instructions VLLDM and VLSTM support lazy saving\nand restoring of the secure floating-point registers. Even\nif the floating point extension is not implemented, these\ninstructions must act as NOPs in Secure state, so they can\nbe used as part of the secure-to-nonsecure call sequence.\n\nFixes: https://bugs.launchpad.net/qemu/+bug/1768295\nCc: qemu-stable@nongnu.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 20180503105730.5958-1-peter.maydell@linaro.org","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/b1e5336a9899016c53d59eba53ebf6abcc21995c"},{"sha":"527773eeef9f2225370f9c17c35074b2ed0ced92","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmu-common: smmu base device and datatypes\n\nThe patch introduces the smmu base device and class for the ARM\nsmmu. Devices for specific versions will be derived from this\nbase device.\n\nWe also introduce some important datatypes.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-2-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/527773eeef9f2225370f9c17c35074b2ed0ced92"},{"sha":"cac994ef43b128c80c56b4cd4dd9d8af0f95da3f","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmu-common: IOMMU memory region and address space setup\n\nWe set up the infrastructure to enumerate all the PCI devices\nattached to the SMMU and create an associated IOMMU memory\nregion and address space.\n\nThose info are stored in SMMUDevice objects. The devices are\ngrouped according to the PCIBus they belong to. A hash table\nindexed by the PCIBus pointer is used. Also an array indexed by\nthe bus number allows to find the list of SMMUDevices.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-3-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/cac994ef43b128c80c56b4cd4dd9d8af0f95da3f"},{"sha":"93641948d4c85f261be1f25a0bdc2ded3476e7d9","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmu-common: VMSAv8-64 page table walk\n\nThis patch implements the page table walk for VMSAv8-64.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nMessage-id: 1524665762-31355-4-git-send-email-eric.auger@redhat.com\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/93641948d4c85f261be1f25a0bdc2ded3476e7d9"},{"sha":"10a83cb9887eddb1b504ecf3b189159db949178e","author":{"name":"Prem Mallappa","email":"b795c93dfe51d1dc638607667a13e3a742d8a48a@broadcom.com"},"message":"hw/arm/smmuv3: Skeleton\n\nThis patch implements a skeleton for the smmuv3 device.\nDatatypes and register definitions are introduced. The MMIO\nregion, the interrupts and the queue are initialized.\n\nOnly the MMIO read operation is implemented here.\n\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-5-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/10a83cb9887eddb1b504ecf3b189159db949178e"},{"sha":"6a736033d343e0e5774849fa0eef88f2582c364a","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Wired IRQ and GERROR helpers\n\nWe introduce some helpers to handle wired IRQs and especially\nGERROR interrupt. SMMU writes GERROR register on GERROR event\nand SW acks GERROR interrupts by setting GERRORn.\n\nThe Wired interrupts are edge sensitive hence the pulse usage.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-6-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/6a736033d343e0e5774849fa0eef88f2582c364a"},{"sha":"dadd1a0809b1aff8c4d5364f3714b3e0e039dcb0","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Queue helpers\n\nWe introduce helpers to read/write into the command and event\ncircular queues.\n\nsmmuv3_write_eventq and smmuv3_cmq_consume will become static\nin subsequent patches.\n\nInvalidation commands are not yet dealt with. We do not cache\ndata that need to be invalidated. This will change with vhost\nintegration.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-7-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/dadd1a0809b1aff8c4d5364f3714b3e0e039dcb0"},{"sha":"fae4be38b35dcfae48494c023454e8988c15b69a","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Implement MMIO write operations\n\nNow we have relevant helpers for queue and irq\nmanagement, let's implement MMIO write operations.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-8-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/fae4be38b35dcfae48494c023454e8988c15b69a"},{"sha":"bb981004eaf4bab2c8ae4feaaf6ead8be7275044","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Event queue recording helper\n\nLet's introduce a helper function aiming at recording an\nevent in the event queue.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-9-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/bb981004eaf4bab2c8ae4feaaf6ead8be7275044"},{"sha":"9bde7f0674fe0354ab58ccf25fdfd9f2f68f2b5c","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Implement translate callback\n\nThis patch implements the IOMMU Memory Region translate()\ncallback. Most of the code relates to the translation\nconfiguration decoding and check (STE, CD).\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Prem Mallappa <prem.mallappa@broadcom.com>\nMessage-id: 1524665762-31355-10-git-send-email-eric.auger@redhat.com\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/9bde7f0674fe0354ab58ccf25fdfd9f2f68f2b5c"},{"sha":"0d1ac82eced6bb641a98cd5d7f3b829635f95fac","author":{"name":"Eric Auger","email":"f60a3d4b180725ab11fd137ffa53f5ae9a69db9a@redhat.com"},"message":"hw/arm/smmuv3: Abort on vfio or vhost case\n\nAt the moment, the SMMUv3 does not support notification on\nTLB invalidation. So let's log an error as soon as such notifier\ngets enabled.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1524665762-31355-11-git-send-email-eric.auger@redhat.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":false,"url":"https://api.github.com/repos/hisilicon/qemu/commits/0d1ac82eced6bb641a98cd5d7f3b829635f95fac"}]}
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