{"action":"created","comment":{"url":"https://api.github.com/repos/linux4sam/at91bootstrap/pulls/comments/186369485","pull_request_review_id":117931874,"id":186369485,"diff_hunk":"@@ -0,0 +1,189 @@\n+/* ----------------------------------------------------------------------------\n+ *          Support for pico-SAM9G45 Board   http://arm.mini-box.com/\n+ * ----------------------------------------------------------------------------\n+ * Copyright (c) 2018, Jochen Friedrich <jochen@scram.de>\n+ *\n+ * Based on at91sam9m10g45ek.c \n+ * Copyright (c) 2008, Atmel Corporation\n+ *\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * - Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the disclaimer below.\n+ *\n+ * Atmel's name may not be used to endorse or promote products derived from\n+ * this software without specific prior written permission.\n+ *\n+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"common.h\"\n+#include \"hardware.h\"\n+#include \"arch/at91_ccfg.h\"\n+#include \"arch/at91_rstc.h\"\n+#include \"arch/at91_pmc.h\"\n+#include \"arch/at91_smc.h\"\n+#include \"arch/at91_pio.h\"\n+#include \"arch/at91_ddrsdrc.h\"\n+#include \"gpio.h\"\n+#include \"pmc.h\"\n+#include \"usart.h\"\n+#include \"debug.h\"\n+#include \"ddramc.h\"\n+#include \"timer.h\"\n+#include \"watchdog.h\"\n+#include \"string.h\"\n+#include \"pico_sam9g45.h\"\n+\n+static void at91_dbgu_hw_init(void)\n+{\n+\t/* Configure DBGU pin */\n+\tconst struct pio_desc dbgu_pins[] = {\n+\t\t{\"RXD\", AT91C_PIN_PB(12), 0, PIO_DEFAULT, PIO_PERIPH_A},\n+\t\t{\"TXD\", AT91C_PIN_PB(13), 0, PIO_DEFAULT, PIO_PERIPH_A},\n+\t\t{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},\n+\t};\n+\n+\t/* Configure the dbgu pins */\n+\tpmc_enable_periph_clock(AT91C_ID_PIOB);\n+\tpio_configure(dbgu_pins);\n+}\n+\n+static void initialize_dbgu(void)\n+{\n+\tat91_dbgu_hw_init();\n+\tusart_init(BAUDRATE(MASTER_CLOCK, 115200));\n+}\n+\n+#ifdef CONFIG_DDR2\n+static void ddramc_reg_config(struct ddramc_register *ddramc_config)\n+{\n+\tddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS\n+\t\t\t| AT91C_DDRC2_MD_DDR2_SDRAM);\n+\n+\tddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9\t/* 10 column bits */\n+\t\t\t| AT91C_DDRC2_NR_14\t\t/* 14 row bits(8K)*/\n+\t\t\t| AT91C_DDRC2_CAS_3\t\t/* CAS Latency 3 */\n+\t\t\t| AT91C_DDRC2_DISABLE_RESET_DLL);\n+\n+\tddramc_config->rtr = 0x24B;\n+\n+\tddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)\t/* 6 * 7.5 = 45 ns */\n+\t\t\t| AT91C_DDRC2_TRCD_(2)\t\t/* 2 * 7.5 = 22.5 ns */\n+\t\t\t| AT91C_DDRC2_TWR_(2)\t\t/* 2 * 7.5 = 15 ns */\n+\t\t\t| AT91C_DDRC2_TRC_(8)\t\t/* 8 * 7.5 = 75 ns */\n+\t\t\t| AT91C_DDRC2_TRP_(2)\t\t/* 2 * 7.5 = 22.5 ns */\n+\t\t\t| AT91C_DDRC2_TRRD_(1)\t\t/* 1 * 7.5 = 7.5 ns */\n+\t\t\t| AT91C_DDRC2_TWTR_(1)\t\t/* 1 clock cycle */\n+\t\t\t| AT91C_DDRC2_TMRD_(2));\t/* 2 clock cycles */\n+\n+\tddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)\t/* 2 * 7.5 = 15 ns */\n+\t\t\t| AT91C_DDRC2_TXSRD_(200)\t/* 200 clock cycles */\n+\t\t\t| AT91C_DDRC2_TXSNR_(16)\t/* 16 * 7.5 = 120 ns */\n+\t\t\t| AT91C_DDRC2_TRFC_(14));\t/* 14 * 7.5 = 142 ns */\n+\n+\tddramc_config->t2pr = (AT91C_DDRC2_TRTP_(1)\t/* 1 * 7.5 = 7.5 ns */\n+\t\t\t| AT91C_DDRC2_TRPA_(0)\t\t/* 0 * 7.5 = 0 ns */\n+\t\t\t| AT91C_DDRC2_TXARDS_(7)\t/* 7 clock cycles */\n+\t\t\t| AT91C_DDRC2_TXARD_(2));\t/* 2 clock cycles */\n+}\n+\n+static void ddramc_init(void)\n+{\n+\tunsigned long csa;\n+\tstruct ddramc_register  ddramc_reg;\n+\n+\tddramc_reg_config(&ddramc_reg);\n+\n+\t/* ENABLE DDR2 clock */ \n+\tpmc_enable_system_clock(AT91C_PMC_DDR);\n+\n+\t/* Chip select 1 is for DDR2/SDRAM */\n+\tcsa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);\n+\tcsa |= AT91C_EBI_CS1A_SDRAMC;\n+\tcsa &= ~AT91C_VDDIOM_SEL_33V;\n+\twritel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);\n+\n+\t/* DDRAM2 Controller initialize */\n+\tddram_initialize(AT91C_BASE_DDRSDRC0, AT91C_BASE_CS6, &ddramc_reg);\n+\tddram_initialize(AT91C_BASE_DDRSDRC1, AT91C_BASE_CS1, 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