{"action":"created","comment":{"url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/pulls/comments/168098251","pull_request_review_id":96408494,"id":168098251,"diff_hunk":"@@ -113,6 +113,16 @@\n \t\t\tstatus = \"disabled\";\n \t\t\tlabel = \"SPI_1\";\n \t\t};\n+\n+\t\tspi2: spi@40003800 {","path":"dts/arm/st/stm32f0.dtsi","position":5,"original_position":5,"commit_id":"7874721f3b649795cb7aacb1f32aad845cca74d9","original_commit_id":"7874721f3b649795cb7aacb1f32aad845cca74d9","user":{"login":"DWagenk","id":32838899,"avatar_url":"https://avatars3.githubusercontent.com/u/32838899?v=4","gravatar_id":"","url":"https://api.github.com/users/DWagenk","html_url":"https://github.com/DWagenk","followers_url":"https://api.github.com/users/DWagenk/followers","following_url":"https://api.github.com/users/DWagenk/following{/other_user}","gists_url":"https://api.github.com/users/DWagenk/gists{/gist_id}","starred_url":"https://api.github.com/users/DWagenk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/DWagenk/subscriptions","organizations_url":"https://api.github.com/users/DWagenk/orgs","repos_url":"https://api.github.com/users/DWagenk/repos","events_url":"https://api.github.com/users/DWagenk/events{/privacy}","received_events_url":"https://api.github.com/users/DWagenk/received_events","type":"User","site_admin":false},"body":"spi2 is not present on all f0 SoCs so it shouldn't be in this place. \r\nI'd propse adding an stm32f030Xc.dtsi and a stm32f030X8.dtsi file and adding the node there.","created_at":"2018-02-14T07:57:32Z","updated_at":"2018-02-14T08:01:31Z","html_url":"https://github.com/zephyrproject-rtos/zephyr/pull/6172#discussion_r168098251","pull_request_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/pulls/6172","author_association":"CONTRIBUTOR","_links":{"self":{"href":"https://api.github.com/repos/zephyrproject-rtos/zephyr/pulls/comments/168098251"},"html":{"href":"https://github.com/zephyrproject-rtos/zephyr/pull/6172#discussion_r168098251"},"pull_request":{"href":"https://api.github.com/repos/zephyrproject-rtos/zephyr/pulls/6172"}}},"pull_request":{"url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/pulls/6172","id":168833639,"html_url":"https://github.com/zephyrproject-rtos/zephyr/pull/6172","diff_url":"https://github.com/zephyrproject-rtos/zephyr/pull/6172.diff","patch_url":"https://github.com/zephyrproject-rtos/zephyr/pull/6172.patch","issue_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/6172","number":6172,"state":"open","locked":false,"title":"Enabling SPI ports on some nucleos","user":{"login":"tbursztyka","id":1608406,"avatar_url":"https://avatars2.githubusercontent.com/u/1608406?v=4","gravatar_id":"","url":"https://api.github.com/users/tbursztyka","html_url":"https://github.com/tbursztyka","followers_url":"https://api.github.com/users/tbursztyka/followers","following_url":"https://api.github.com/users/tbursztyka/following{/other_user}","gists_url":"https://api.github.com/users/tbursztyka/gists{/gist_id}","starred_url":"https://api.github.com/users/tbursztyka/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tbursztyka/subscriptions","organizations_url":"https://api.github.com/users/tbursztyka/orgs","repos_url":"https://api.github.com/users/tbursztyka/repos","events_url":"https://api.github.com/users/tbursztyka/events{/privacy}","received_events_url":"https://api.github.com/users/tbursztyka/received_events","type":"User","site_admin":false},"body":"Hello,\r\n\r\nWhile testing something on SPI that required to use stm32's, and since I had these nucleos, I enabled the SPI ports relevantly there.\r\nI could successfully test nucleo_f103rb and nucleo_f334r8\r\n\r\n@erwango My nucleo_f030r8 st-link acting weirdly as you know I could not test yet (I'll do you trick of using an external st-link). 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