{"action":"created","issue":{"url":"https://api.github.com/repos/sinara-hw/Kasli/issues/5","repository_url":"https://api.github.com/repos/sinara-hw/Kasli","labels_url":"https://api.github.com/repos/sinara-hw/Kasli/issues/5/labels{/name}","comments_url":"https://api.github.com/repos/sinara-hw/Kasli/issues/5/comments","events_url":"https://api.github.com/repos/sinara-hw/Kasli/issues/5/events","html_url":"https://github.com/sinara-hw/Kasli/issues/5","id":331992368,"node_id":"MDU6SXNzdWUzMzE5OTIzNjg=","number":5,"title":"Kasli v1.2 wishlist","user":{"login":"marmeladapk","id":24512604,"node_id":"MDQ6VXNlcjI0NTEyNjA0","avatar_url":"https://avatars1.githubusercontent.com/u/24512604?v=4","gravatar_id":"","url":"https://api.github.com/users/marmeladapk","html_url":"https://github.com/marmeladapk","followers_url":"https://api.github.com/users/marmeladapk/followers","following_url":"https://api.github.com/users/marmeladapk/following{/other_user}","gists_url":"https://api.github.com/users/marmeladapk/gists{/gist_id}","starred_url":"https://api.github.com/users/marmeladapk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/marmeladapk/subscriptions","organizations_url":"https://api.github.com/users/marmeladapk/orgs","repos_url":"https://api.github.com/users/marmeladapk/repos","events_url":"https://api.github.com/users/marmeladapk/events{/privacy}","received_events_url":"https://api.github.com/users/marmeladapk/received_events","type":"User","site_admin":false},"labels":[{"id":963441539,"node_id":"MDU6TGFiZWw5NjM0NDE1Mzk=","url":"https://api.github.com/repos/sinara-hw/Kasli/labels/area:kasli","name":"area:kasli","color":"ededed","default":false}],"state":"closed","locked":false,"assignee":{"login":"marmeladapk","id":24512604,"node_id":"MDQ6VXNlcjI0NTEyNjA0","avatar_url":"https://avatars1.githubusercontent.com/u/24512604?v=4","gravatar_id":"","url":"https://api.github.com/users/marmeladapk","html_url":"https://github.com/marmeladapk","followers_url":"https://api.github.com/users/marmeladapk/followers","following_url":"https://api.github.com/users/marmeladapk/following{/other_user}","gists_url":"https://api.github.com/users/marmeladapk/gists{/gist_id}","starred_url":"https://api.github.com/users/marmeladapk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/marmeladapk/subscriptions","organizations_url":"https://api.github.com/users/marmeladapk/orgs","repos_url":"https://api.github.com/users/marmeladapk/repos","events_url":"https://api.github.com/users/marmeladapk/events{/privacy}","received_events_url":"https://api.github.com/users/marmeladapk/received_events","type":"User","site_admin":false},"assignees":[{"login":"marmeladapk","id":24512604,"node_id":"MDQ6VXNlcjI0NTEyNjA0","avatar_url":"https://avatars1.githubusercontent.com/u/24512604?v=4","gravatar_id":"","url":"https://api.github.com/users/marmeladapk","html_url":"https://github.com/marmeladapk","followers_url":"https://api.github.com/users/marmeladapk/followers","following_url":"https://api.github.com/users/marmeladapk/following{/other_user}","gists_url":"https://api.github.com/users/marmeladapk/gists{/gist_id}","starred_url":"https://api.github.com/users/marmeladapk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/marmeladapk/subscriptions","organizations_url":"https://api.github.com/users/marmeladapk/orgs","repos_url":"https://api.github.com/users/marmeladapk/repos","events_url":"https://api.github.com/users/marmeladapk/events{/privacy}","received_events_url":"https://api.github.com/users/marmeladapk/received_events","type":"User","site_admin":false}],"milestone":null,"comments":29,"created_at":"2018-06-13T13:22:05Z","updated_at":"2018-06-13T13:23:04Z","closed_at":"2018-06-13T13:22:06Z","author_association":"MEMBER","body":"_From @marmeladapk on [2018-01-31 09:53](https://github.com/sinara-hw/sinara/issues/499)_\n\n\n- Rotate SATA connector\r\n- Have I2C and UART signals in the same bank (each of them)\r\n- Switch all components to our standard library\r\n- Switch U1 to nonBGA version\r\n- Maybe [Bigger heat sink](https://www.digikey.de/products/en/fans-thermal-management/thermal-heat-sinks/219?k=&pkeyword=heat+sink+bga&pv623=19&FV=1341800%2C5940104%2Cffe000db&mnonly=0&ColumnSort=625&page=1&stock=1&quantity=0&ptm=0&fid=0&pageSize=25) with clamps pending measurements with big artiq setup\r\n- Move the clock input SMA further towards the panel. Leave just enough gap for the insulating washer. Otherwise (with a gap, the two insulating washers, the panel, and the nut, even without the springy/claw washer) there is not enough thread to fully tighten an SMA connector.\r\n- Si5369 instead of Si5324+ADCLK944 (power, board space, components, cost). Or even Si5346\r\n- Move UART RxD away from bank 13\r\n- Replace 100k resistors with 0R on the SMA clock input and MMCX clock outputs to tie all grounds together.\r\n- Add note on schematic by the connectors saying something like \"To float connector grounds, replace 0R with 100k. NB Kasli must be connected to mains ground for to avoid damage to it or other equipment connected to it!\"\r\n - Add TVS on JTAG\r\n - Make board 2-3 mm shorter, so that technosystem doesn't need to grind each board to mount backplane connector... (they told me about it after five months!)"},"comment":{"url":"https://api.github.com/repos/sinara-hw/Kasli/issues/comments/396935213","html_url":"https://github.com/sinara-hw/Kasli/issues/5#issuecomment-396935213","issue_url":"https://api.github.com/repos/sinara-hw/Kasli/issues/5","id":396935213,"node_id":"MDEyOklzc3VlQ29tbWVudDM5NjkzNTIxMw==","user":{"login":"marmeladapk","id":24512604,"node_id":"MDQ6VXNlcjI0NTEyNjA0","avatar_url":"https://avatars1.githubusercontent.com/u/24512604?v=4","gravatar_id":"","url":"https://api.github.com/users/marmeladapk","html_url":"https://github.com/marmeladapk","followers_url":"https://api.github.com/users/marmeladapk/followers","following_url":"https://api.github.com/users/marmeladapk/following{/other_user}","gists_url":"https://api.github.com/users/marmeladapk/gists{/gist_id}","starred_url":"https://api.github.com/users/marmeladapk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/marmeladapk/subscriptions","organizations_url":"https://api.github.com/users/marmeladapk/orgs","repos_url":"https://api.github.com/users/marmeladapk/repos","events_url":"https://api.github.com/users/marmeladapk/events{/privacy}","received_events_url":"https://api.github.com/users/marmeladapk/received_events","type":"User","site_admin":false},"created_at":"2018-06-13T13:23:04Z","updated_at":"2018-06-13T13:23:04Z","author_association":"MEMBER","body":"_From @hartytp on [2018-04-01 17:34](https://github.com/sinara-hw/sinara/issues/499#issuecomment-377802981)_\n\n\n> Part of the reason it's a surprise is because uniprocessor systems (e.g. the DRTIO satellite, and other MiSoC ports to Artix-7 boards) meet timing; the problems appear with the ARTIQ dual-CPU design for some reason.\r\n\r\nYes, that is a bit concerning. And, again, it doesn't give me much confidence that issues to do with Artix FPGAs being slow won't be a recurring theme as we develop ARTIQ further, e.g. by adding hard FP."}}
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