{"action":"created","issue":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/365","repository_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing","labels_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/365/labels{/name}","comments_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/365/comments","events_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/365/events","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365","id":332327596,"node_id":"MDExOlB1bGxSZXF1ZXN0MTk0ODM1MjIy","number":365,"title":"Support packing when modes provide different routing","user":{"login":"mithro","id":21212,"node_id":"MDQ6VXNlcjIxMjEy","avatar_url":"https://avatars2.githubusercontent.com/u/21212?v=4","gravatar_id":"","url":"https://api.github.com/users/mithro","html_url":"https://github.com/mithro","followers_url":"https://api.github.com/users/mithro/followers","following_url":"https://api.github.com/users/mithro/following{/other_user}","gists_url":"https://api.github.com/users/mithro/gists{/gist_id}","starred_url":"https://api.github.com/users/mithro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mithro/subscriptions","organizations_url":"https://api.github.com/users/mithro/orgs","repos_url":"https://api.github.com/users/mithro/repos","events_url":"https://api.github.com/users/mithro/events{/privacy}","received_events_url":"https://api.github.com/users/mithro/received_events","type":"User","site_admin":false},"labels":[{"id":411294564,"node_id":"MDU6TGFiZWw0MTEyOTQ1NjQ=","url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/labels/VPR","name":"VPR","color":"d4c5f9","default":false},{"id":877556871,"node_id":"MDU6TGFiZWw4Nzc1NTY4NzE=","url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/labels/build","name":"build","color":"42a6af","default":false},{"id":865751016,"node_id":"MDU6TGFiZWw4NjU3NTEwMTY=","url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/labels/lang-cpp","name":"lang-cpp","color":"f9d0c4","default":false},{"id":877556875,"node_id":"MDU6TGFiZWw4Nzc1NTY4NzU=","url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/labels/lang-make","name":"lang-make","color":"f9d0c4","default":false}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2018-06-14T09:43:46Z","updated_at":"2018-06-15T01:01:51Z","closed_at":null,"author_association":"COLLABORATOR","pull_request":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/pulls/365","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365","diff_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365.diff","patch_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365.patch"},"body":"This is a work in progress. I'm sending it to get feedback on the change.\r\n\r\nThis makes the packer work when there are multiple modes which change the routing pattern through a cluster.\r\n\r\nThe packer will try and pack everything together, then it will fail routing causing it to fall back to checking routing atom-by-atom.\r\n\r\nThis will then cause the packer to not add the conflicting modes into one cluster.\r\n"},"comment":{"url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/comments/397482799","html_url":"https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365#issuecomment-397482799","issue_url":"https://api.github.com/repos/verilog-to-routing/vtr-verilog-to-routing/issues/365","id":397482799,"node_id":"MDEyOklzc3VlQ29tbWVudDM5NzQ4Mjc5OQ==","user":{"login":"mithro","id":21212,"node_id":"MDQ6VXNlcjIxMjEy","avatar_url":"https://avatars2.githubusercontent.com/u/21212?v=4","gravatar_id":"","url":"https://api.github.com/users/mithro","html_url":"https://github.com/mithro","followers_url":"https://api.github.com/users/mithro/followers","following_url":"https://api.github.com/users/mithro/following{/other_user}","gists_url":"https://api.github.com/users/mithro/gists{/gist_id}","starred_url":"https://api.github.com/users/mithro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mithro/subscriptions","organizations_url":"https://api.github.com/users/mithro/orgs","repos_url":"https://api.github.com/users/mithro/repos","events_url":"https://api.github.com/users/mithro/events{/privacy}","received_events_url":"https://api.github.com/users/mithro/received_events","type":"User","site_admin":false},"created_at":"2018-06-15T01:01:51Z","updated_at":"2018-06-15T01:01:51Z","author_association":"COLLABORATOR","body":"This seems to cause failures at the moment;\r\n```\r\nTest 'vtr_reg_strong' had 30 qor test failures\r\nTest 'vtr_reg_strong' had 1 run failures\r\nTest complete\r\nError: 31 tests failed!\r\n```\r\n\r\n```\r\nregression_tests/vtr_reg_strong/strong_fracturable_luts...\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_post_packed_nets: golden = 249 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common device_width: golden = 11 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common device_height: golden = 11 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width: golden = 36 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common routed_wirelength: golden = 1599 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common logic_block_area_total: golden = 0 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common logic_block_area_used: golden = 0 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width_routing_area_total: golden = 316062. result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width_routing_area_per_tile: golden = 2612.08 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_clb: golden = 14 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_io: golden = 99 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_outputs: golden = 130 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_memories: golden = 1 result = -1\r\n[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_mult: golden = 0 result = -1\r\nregression_tests/vtr_reg_strong/strong_mcnc...[Pass]\r\nregression_tests/vtr_reg_strong/strong_no_timing...\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_post_packed_nets: golden = 250 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common device_width: golden = 10 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common device_height: golden = 10 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width: golden = 34 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common routed_wirelength: golden = 2330 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common logic_block_area_total: golden = 3.92691e+06 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common logic_block_area_used: golden = 1.08694e+06 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width_routing_area_total: golden = 218071. result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width_routing_area_per_tile: golden = 2180.71 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_clb: golden = 10 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_io: golden = 99 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_outputs: golden = 130 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_memories: golden = 1 result = -1\r\n[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_mult: golden = 0 result = -1\r\n```"}}
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