{"action":"created","issue":{"url":"https://api.github.com/repos/WebAssembly/simd/issues/28","repository_url":"https://api.github.com/repos/WebAssembly/simd","labels_url":"https://api.github.com/repos/WebAssembly/simd/issues/28/labels{/name}","comments_url":"https://api.github.com/repos/WebAssembly/simd/issues/28/comments","events_url":"https://api.github.com/repos/WebAssembly/simd/issues/28/events","html_url":"https://github.com/WebAssembly/simd/issues/28","id":310126151,"number":28,"title":"Adding new SIMD instructions to load sign and zero extend 8, 16 and 32 byte integers","user":{"login":"rrwinterton","id":12848208,"avatar_url":"https://avatars3.githubusercontent.com/u/12848208?v=4","gravatar_id":"","url":"https://api.github.com/users/rrwinterton","html_url":"https://github.com/rrwinterton","followers_url":"https://api.github.com/users/rrwinterton/followers","following_url":"https://api.github.com/users/rrwinterton/following{/other_user}","gists_url":"https://api.github.com/users/rrwinterton/gists{/gist_id}","starred_url":"https://api.github.com/users/rrwinterton/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/rrwinterton/subscriptions","organizations_url":"https://api.github.com/users/rrwinterton/orgs","repos_url":"https://api.github.com/users/rrwinterton/repos","events_url":"https://api.github.com/users/rrwinterton/events{/privacy}","received_events_url":"https://api.github.com/users/rrwinterton/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2018-03-30T17:45:19Z","updated_at":"2018-03-30T18:06:43Z","closed_at":null,"author_association":"NONE","body":"[proposal-webAssembly-SIMD-modification.pdf](https://github.com/WebAssembly/simd/files/1864317/proposal-webAssembly-SIMD-modification.pdf)\r\n"},"comment":{"url":"https://api.github.com/repos/WebAssembly/simd/issues/comments/377585364","html_url":"https://github.com/WebAssembly/simd/issues/28#issuecomment-377585364","issue_url":"https://api.github.com/repos/WebAssembly/simd/issues/28","id":377585364,"user":{"login":"kenchris","id":1101339,"avatar_url":"https://avatars1.githubusercontent.com/u/1101339?v=4","gravatar_id":"","url":"https://api.github.com/users/kenchris","html_url":"https://github.com/kenchris","followers_url":"https://api.github.com/users/kenchris/followers","following_url":"https://api.github.com/users/kenchris/following{/other_user}","gists_url":"https://api.github.com/users/kenchris/gists{/gist_id}","starred_url":"https://api.github.com/users/kenchris/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/kenchris/subscriptions","organizations_url":"https://api.github.com/users/kenchris/orgs","repos_url":"https://api.github.com/users/kenchris/repos","events_url":"https://api.github.com/users/kenchris/events{/privacy}","received_events_url":"https://api.github.com/users/kenchris/received_events","type":"User","site_admin":false},"created_at":"2018-03-30T18:06:43Z","updated_at":"2018-03-30T18:06:43Z","author_association":"NONE","body":"Proposal WebAssembly SIMD Modification\r\n===\r\n\r\nCurrently as proposed there is an instruction defined in the WASM SIMD ISA as follows.\r\nInstruction – i8x16.mul which is a register to register operation that takes 16 8 bit integers and\r\nmultiplies them together resulting in an 8 bit value. If the distribution of the integers it flat this\r\nwould result in approximately 50 percent of the instructions with overflow. This instruction is\r\nnot too useful in real life applications that is known. This instruction could be left in the ISA mix\r\nbut for IA would require a significant amount of instructions and would have to require\r\noverflow handling and specifications to achieve cross platform compatibility. This really is\r\nmessy for no known applications. This overflow handling is currently not defined in the WASM\r\nSIMD specification.\r\n\r\nProposal is to remove this instruction as known applications don’t use i8x16.mul functionality\r\nand add the widening load integer instructions. This was previously proposed as a candidate in\r\nbullet two back in November last year.\r\n\r\n![image](https://user-images.githubusercontent.com/1101339/38148184-ae56ccce-3455-11e8-9a01-47dd62ac545c.png)\r\n\r\nProposed new instructions:\r\n===\r\nIn conjunction with the potential change of the i8x16.mul removal it is proposed to create an\r\ninstruction that would have six new load instructions to make integer multiplies easier. The\r\nfirst is i8x16. This would make i8, i16, i32 multiplies useful and more practical for applications\r\nsuch as machine learning, image compression and video and rendering data processing.\r\nThe new instructions would take consecutive integers of the corresponding size and zero sign\r\nextend and sign extend the consecutive bytes, words or dword to\r\n\r\n![image](https://user-images.githubusercontent.com/1101339/38148202-bfb1334c-3455-11e8-9cb2-3fb7b2d8e11c.png)\r\n\r\nIntel and ARM both have this capability by doing the following:\r\n\r\nmovzxbw,\r\nmovzxwd\r\nmovzxdq\r\nmovsxbw\r\nmovsxwd\r\nmovsxdq\r\n\r\nARM:\r\n\r\n![image](https://user-images.githubusercontent.com/1101339/38148228-d1d0c772-3455-11e8-97d5-0edd957b0604.png)\r\n\r\nSo the new instructions for WASM would be defined as follows:\r\n\r\ni8x8.zxload, i16x4.zxload, i32x2.zxload, i8x8.sxload, i16x4.sxload, i32x2.sxload\r\nAs a result of these new instructions a multiply can now be done without worrying about signed\r\nand unsigned overflow on 50 percent of the data it operates on.\r\n"}}
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