{"action":"created","issue":{"url":"https://api.github.com/repos/m-labs/artiq/issues/1055","repository_url":"https://api.github.com/repos/m-labs/artiq","labels_url":"https://api.github.com/repos/m-labs/artiq/issues/1055/labels{/name}","comments_url":"https://api.github.com/repos/m-labs/artiq/issues/1055/comments","events_url":"https://api.github.com/repos/m-labs/artiq/issues/1055/events","html_url":"https://github.com/m-labs/artiq/issues/1055","id":329503630,"node_id":"MDU6SXNzdWUzMjk1MDM2MzA=","number":1055,"title":"Sayma: check HMC7043 output phases status on init","user":{"login":"hartytp","id":21218399,"node_id":"MDQ6VXNlcjIxMjE4Mzk5","avatar_url":"https://avatars0.githubusercontent.com/u/21218399?v=4","gravatar_id":"","url":"https://api.github.com/users/hartytp","html_url":"https://github.com/hartytp","followers_url":"https://api.github.com/users/hartytp/followers","following_url":"https://api.github.com/users/hartytp/following{/other_user}","gists_url":"https://api.github.com/users/hartytp/gists{/gist_id}","starred_url":"https://api.github.com/users/hartytp/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/hartytp/subscriptions","organizations_url":"https://api.github.com/users/hartytp/orgs","repos_url":"https://api.github.com/users/hartytp/repos","events_url":"https://api.github.com/users/hartytp/events{/privacy}","received_events_url":"https://api.github.com/users/hartytp/received_events","type":"User","site_admin":false},"labels":[{"id":449842836,"node_id":"MDU6TGFiZWw0NDk4NDI4MzY=","url":"https://api.github.com/repos/m-labs/artiq/labels/area:sayma","name":"area:sayma","color":"d4c5f9","default":false}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2018-06-05T15:14:40Z","updated_at":"2018-07-04T18:21:43Z","closed_at":null,"author_association":"COLLABORATOR","body":"We should probably read back the \"outputs phases status\" bit from the HMC7043 before we return from init (see the typical programming sequence section, point 10). This verifies that the phases are stable before we unmute the outputs (i.e. no glitches).\r\n\r\nI interpret that as meaning that we should read back register 0x7D, potentially after setting an appropriate mask in register 0x71, although maybe I've misunderstood that. Anyway, currently 0x7d  always seems to be 0x00, indicating that the phases aren't stable or that I'm doing something wrong.\r\n\r\nAs a low priority, would you mind looking into this @sbourdeauducq or @enjoy-digital "},"comment":{"url":"https://api.github.com/repos/m-labs/artiq/issues/comments/402538450","html_url":"https://github.com/m-labs/artiq/issues/1055#issuecomment-402538450","issue_url":"https://api.github.com/repos/m-labs/artiq/issues/1055","id":402538450,"node_id":"MDEyOklzc3VlQ29tbWVudDQwMjUzODQ1MA==","user":{"login":"hartytp","id":21218399,"node_id":"MDQ6VXNlcjIxMjE4Mzk5","avatar_url":"https://avatars0.githubusercontent.com/u/21218399?v=4","gravatar_id":"","url":"https://api.github.com/users/hartytp","html_url":"https://github.com/hartytp","followers_url":"https://api.github.com/users/hartytp/followers","following_url":"https://api.github.com/users/hartytp/following{/other_user}","gists_url":"https://api.github.com/users/hartytp/gists{/gist_id}","starred_url":"https://api.github.com/users/hartytp/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/hartytp/subscriptions","organizations_url":"https://api.github.com/users/hartytp/orgs","repos_url":"https://api.github.com/users/hartytp/repos","events_url":"https://api.github.com/users/hartytp/events{/privacy}","received_events_url":"https://api.github.com/users/hartytp/received_events","type":"User","site_admin":false},"created_at":"2018-07-04T18:21:43Z","updated_at":"2018-07-04T18:21:43Z","author_association":"COLLABORATOR","body":"Thanks for checking that.\r\n\r\nSo, either we're not using this bit correctly or the phases aren't settling properly."}}
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