{"push_id":2981215002,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"dc6587ba0d7998a98387d7d936e9a9593e26d53c","before":"38ccfecd5eb66bd10669ec3a8726b8d18bb1b89f","commits":[{"sha":"dc6587ba0d7998a98387d7d936e9a9593e26d53c","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"Recommit r344877 \"[X86] Stop promoting integer loads to vXi64\"\n\nI've included a fix to DAGCombiner::ForwardStoreValueToDirectLoad that I believe will prevent the previous miscompile.\n\nOriginal commit message:\n\nTheoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to rem\n\nI had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping.\n\nI still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the lo\n\nI'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion.\n\nReviewers: RKSimon, spatel\n\nReviewed By: RKSimon\n\nSubscribers: llvm-commits, RKSimon\n\nDifferential Revision: https://reviews.llvm.org/D53306","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/dc6587ba0d7998a98387d7d936e9a9593e26d53c"}]}
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