{"push_id":2761618628,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"87fa367dfe4d05171711ab0857db0597ce221340","before":"151c617964a6c1f3eaff31d8ad70b7214d8cb6f7","commits":[{"sha":"87fa367dfe4d05171711ab0857db0597ce221340","author":{"name":"Francis Visoiu Mistrih","email":"7a95e7be7df2469ab0a6511684ac541d5b50df28@yahoo.com"},"message":"[X86] Preserve more liveness information in emitStackProbeInline\n\nThis commit fixes two issues with the liveness information after the\ncall:\n\n1) The code always spills RCX and RDX if InProlog == true, which results\nin an use of undefined phys reg.\n2) FinalReg, JoinReg, RoundedReg, SizeReg are not added as live-ins to\nthe basic blocks that use them, therefore they are seen undefined.\n\nhttps://llvm.org/PR38376\n\nDifferential Revision: https://reviews.llvm.org/D50020","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-20170507/commits/87fa367dfe4d05171711ab0857db0597ce221340"}]}
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