{"action":"created","comment":{"url":"https://api.github.com/repos/dotnet/coreclr/pulls/comments/192836052","pull_request_review_id":125686754,"id":192836052,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDE5MjgzNjA1Mg==","diff_hunk":"@@ -5359,192 +5386,276 @@ void emitter::emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNu\n }\n \n #ifdef FEATURE_HW_INTRINSICS\n-void emitter::emitIns_SIMD_R_R_A(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, GenTreeIndir* indir)\n+void emitter::emitIns_SIMD_R_R_I(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, int ival)\n+{\n+    if (UseVEXEncoding() || IsDstSrcImmAvxInstruction(ins))\n+    {\n+        emitIns_R_R_I(ins, attr, targetReg, op1Reg, ival);\n+    }\n+    else\n+    {\n+        if (op1Reg != targetReg)\n+        {\n+            emitIns_R_R(INS_movaps, attr, targetReg, op1Reg);\n+        }\n+        emitIns_R_I(ins, attr, targetReg, ival);\n+    }\n+}\n+\n+void emitter::emitIns_SIMD_R_R_A(\n+    instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, GenTreeIndir* indir)\n {\n     if (UseVEXEncoding())\n     {\n-        emitIns_R_R_A(ins, attr, reg, reg1, indir, IF_RWR_RRD_ARD);\n+        emitIns_R_R_A(ins, attr, targetReg, op1Reg, indir);\n     }\n     else\n     {\n-        if (reg1 != reg)\n+        if (op1Reg != targetReg)\n         {\n-            emitIns_R_R(INS_movaps, attr, reg, reg1);\n+            emitIns_R_R(INS_movaps, attr, targetReg, op1Reg);\n         }\n-        emitIns_R_A(ins, attr, reg, indir, IF_RRW_ARD);\n+        emitIns_R_A(ins, attr, targetReg, indir);\n     }\n }\n \n-void emitter::emitIns_SIMD_R_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber base)\n+void emitter::emitIns_SIMD_R_R_AR(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber base)\n {\n     if (UseVEXEncoding())\n     {\n-        emitIns_R_R_AR(ins, attr, reg, reg1, base, 0);\n+        emitIns_R_R_AR(ins, attr, targetReg, op1Reg, base, 0);\n     }\n     else\n     {\n-        if (reg1 != reg)\n+        if (op1Reg != targetReg)\n         {\n-            emitIns_R_R(INS_movaps, attr, reg, reg1);\n+            emitIns_R_R(INS_movaps, attr, targetReg, op1Reg);\n         }\n-        emitIns_R_AR(ins, attr, reg, base, 0);\n+        emitIns_R_AR(ins, attr, targetReg, base, 0);\n     }\n }\n \n void emitter::emitIns_SIMD_R_R_C(\n-    instruction ins, emitAttr attr, regNumber reg, regNumber reg1, CORINFO_FIELD_HANDLE fldHnd, int offs)\n+    instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, CORINFO_FIELD_HANDLE fldHnd, int offs)\n {\n     if (UseVEXEncoding())\n     {\n-        emitIns_R_R_C(ins, attr, reg, reg1, fldHnd, offs);\n+        emitIns_R_R_C(ins, attr, targetReg, op1Reg, fldHnd, offs);\n     }\n     else\n     {\n-        if (reg1 != reg)\n+        if (op1Reg != targetReg)\n         {\n-            emitIns_R_R(INS_movaps, attr, reg, reg1);\n+            emitIns_R_R(INS_movaps, attr, targetReg, op1Reg);\n         }\n-        emitIns_R_C(ins, attr, reg, fldHnd, offs);\n+        emitIns_R_C(ins, attr, targetReg, fldHnd, offs);\n     }\n }\n \n-void emitter::emitIns_SIMD_R_R_R(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber reg2)\n+void emitter::emitIns_SIMD_R_R_R(\n+    instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg)\n {\n     if (UseVEXEncoding())\n     {\n-        emitIns_R_R_R(ins, attr, reg, reg1, reg2);\n+        emitIns_R_R_R(ins, attr, targetReg, op1Reg, op2Reg);\n     }\n     else\n     {\n-        if (reg1 != reg)\n+        if (op1Reg != targetReg)\n         {\n             // Ensure we aren't overwriting op2\n-            assert(reg2 != reg);\n+            assert(op2Reg != targetReg);\n \n-            emitIns_R_R(INS_movaps, attr, reg, reg1);\n+            emitIns_R_R(INS_movaps, attr, targetReg, op1Reg);\n         }\n-        emitIns_R_R(ins, attr, reg, reg2);\n+        emitIns_R_R(ins, attr, targetReg, op2Reg);\n     }\n }\n \n-//------------------------------------------------------------------------\n-// IsDstSrcImmAvxInstruction: check if instruction has \"R(M) R(M) I\" format\n-// for EVEX, VEX and legacy SSE encodings and has no (E)VEX.NDS\n-//\n-// Arguments:\n-//    instruction -- processor instruction to check\n-//\n-// Return Value:\n-//    true if instruction has \"R(M) R(M) I\" format and has no (E)VEX.NDS\n-//\n-static bool IsDstSrcImmAvxInstruction(instruction ins)\n+void emitter::emitIns_SIMD_R_R_S(","path":"src/jit/emitxarch.cpp","position":194,"original_position":194,"commit_id":"513d9309bb5c7c41c0132a2f4389e446d33ae8a9","original_commit_id":"513d9309bb5c7c41c0132a2f4389e446d33ae8a9","user":{"login":"CarolEidt","id":2973870,"node_id":"MDQ6VXNlcjI5NzM4NzA=","avatar_url":"https://avatars1.githubusercontent.com/u/2973870?v=4","gravatar_id":"","url":"https://api.github.com/users/CarolEidt","html_url":"https://github.com/CarolEidt","followers_url":"https://api.github.com/users/CarolEidt/followers","following_url":"https://api.github.com/users/CarolEidt/following{/other_user}","gists_url":"https://api.github.com/users/CarolEidt/gists{/gist_id}","starred_url":"https://api.github.com/users/CarolEidt/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/CarolEidt/subscriptions","organizations_url":"https://api.github.com/users/CarolEidt/orgs","repos_url":"https://api.github.com/users/CarolEidt/repos","events_url":"https://api.github.com/users/CarolEidt/events{/privacy}","received_events_url":"https://api.github.com/users/CarolEidt/received_events","type":"User","site_admin":false},"body":"This also need a function header.","created_at":"2018-06-04T18:22:59Z","updated_at":"2018-06-04T18:32:38Z","html_url":"https://github.com/dotnet/coreclr/pull/18262#discussion_r192836052","pull_request_url":"https://api.github.com/repos/dotnet/coreclr/pulls/18262","author_association":"MEMBER","_links":{"self":{"href":"https://api.github.com/repos/dotnet/coreclr/pulls/comments/192836052"},"html":{"href":"https://github.com/dotnet/coreclr/pull/18262#discussion_r192836052"},"pull_request":{"href":"https://api.github.com/repos/dotnet/coreclr/pulls/18262"}}},"pull_request":{"url":"https://api.github.com/repos/dotnet/coreclr/pulls/18262","id":192228656,"node_id":"MDExOlB1bGxSZXF1ZXN0MTkyMjI4NjU2","html_url":"https://github.com/dotnet/coreclr/pull/18262","diff_url":"https://github.com/dotnet/coreclr/pull/18262.diff","patch_url":"https://github.com/dotnet/coreclr/pull/18262.patch","issue_url":"https://api.github.com/repos/dotnet/coreclr/issues/18262","number":18262,"state":"open","locked":false,"title":"Support containment for most one-operand x86 HWIntrinsics","user":{"login":"tannergooding","id":10487869,"node_id":"MDQ6VXNlcjEwNDg3ODY5","avatar_url":"https://avatars3.githubusercontent.com/u/10487869?v=4","gravatar_id":"","url":"https://api.github.com/users/tannergooding","html_url":"https://github.com/tannergooding","followers_url":"https://api.github.com/users/tannergooding/followers","following_url":"https://api.github.com/users/tannergooding/following{/other_user}","gists_url":"https://api.github.com/users/tannergooding/gists{/gist_id}","starred_url":"https://api.github.com/users/tannergooding/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tannergooding/subscriptions","organizations_url":"https://api.github.com/users/tannergooding/orgs","repos_url":"https://api.github.com/users/tannergooding/repos","events_url":"https://api.github.com/users/tannergooding/events{/privacy}","received_events_url":"https://api.github.com/users/tannergooding/received_events","type":"User","site_admin":false},"body":"FYI. @CarolEidt, @fiigii, @eerhardt \r\n\r\nThis adds containment support for most of the one-operand HWIntrinsics.\r\n\r\nThis also cleans up the names of the `emitIns_SIMD_*` parameters (which was a request from @CarolEidt  on a previous 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