{"push_id":2610287716,"size":119,"distinct_size":8,"ref":"refs/heads/intel_ci","head":"7149dc9e3148fc0fbd15164a3ca183785495cb58","before":"08dd52f20ad84c8fd79b763512a1ccaa4fae9afe","commits":[{"sha":"6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba","author":{"name":"Jose Dapena Paz","email":"b5088db3fada4757e1f7efee9638369134c6a04c@lge.com"},"message":"mesa: do not leak ctx->Shader.ReferencedProgram references\n\nWhen glUseProgram is used, references to the included shaders are\nadded in ctx->Shader.ReferencedProgram. But those references are not\ndecreased when the shader data is deallocated. Thus, those shaders\nare leaked.\n\nExplicitely remove the pending references to these shaders.\n\nFixes: e6506b3cd23 (\"mesa: retain gl_shader_programs after glDeleteProgram if they are in use\")\nReviewed-by: Timothy Arceri <tarceri@itsqueeze.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba"},{"sha":"8c406f0b4d904867058deb4e19acd69fd2c38c91","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: remove unused parameter in radv_dump_annotated_shader()\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/8c406f0b4d904867058deb4e19acd69fd2c38c91"},{"sha":"6f0530ecfe9cfe4349dab197397df92dd967c50c","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: rework how shaders are dumped when generating a hang report\n\nUse a flag for the active stages instead.\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/6f0530ecfe9cfe4349dab197397df92dd967c50c"},{"sha":"de06dfa9ea05ab5d06efb20223a858eb42d02683","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: add radv_dump_pipeline_state() helper\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/de06dfa9ea05ab5d06efb20223a858eb42d02683"},{"sha":"66e38654c9fef548b9f5a77f0d376aea57b89b50","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: fix dumping compute shader on the graphics queue\n\nThe graphics pipeline can be NULL.\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/66e38654c9fef548b9f5a77f0d376aea57b89b50"},{"sha":"45eb24fedf5b790237263d79d72cd1e433931b87","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv: run the EarlyCSEMemSSA LLVM pass\n\nIt's recommended by the instruction combining pass, and\nRadeonSI also runs it.\n\nThis pass used to segfault with one shader of F12017 in the\npast, but it no longer crashes. Maybe the LLVM IR generated\nby RADV has changed.\n\nPolaris10:\nTotals from affected shaders:\nSGPRS: 441352 -> 441648 (0.07 %)\nVGPRS: 310888 -> 300784 (-3.25 %)\nSpilled SGPRs: 13576 -> 12983 (-4.37 %)\nCode Size: 22560328 -> 22420544 (-0.62 %) bytes\nMax Waves: 40755 -> 41366 (1.50 %)\n\nVega10:\nTotals from affected shaders:\nSGPRS: 442848 -> 442000 (-0.19 %)\nVGPRS: 310396 -> 300460 (-3.20 %)\nSpilled SGPRs: 13708 -> 12906 (-5.85 %)\nCode Size: 22479428 -> 22336216 (-0.64 %) bytes\nMax Waves: 45783 -> 46506 (1.58 %)\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/45eb24fedf5b790237263d79d72cd1e433931b87"},{"sha":"cfe75cc7b5acbf0692baff07a516ff4efe7fa968","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Added in-place building to SCATTERPS\n\nSCATTERPS previously assumed it was being used with an existing basic\nblock\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/cfe75cc7b5acbf0692baff07a516ff4efe7fa968"},{"sha":"f09636e2e1311b24cbcd2a2d49e97f8a69702cfd","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Check gCoreBuckets/CORE_BUCKETS equal length at compile time\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/f09636e2e1311b24cbcd2a2d49e97f8a69702cfd"},{"sha":"14b5cac0be15b2a1f6624431ae1b694f3a4487dd","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Use metadata to communicate between passes\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/14b5cac0be15b2a1f6624431ae1b694f3a4487dd"},{"sha":"98d0201577ba21223e6d9a54b1240fe49524d486","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Renamed MetaData calls\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/98d0201577ba21223e6d9a54b1240fe49524d486"},{"sha":"b6b114c1aeaa996a4bf8c1fd409e8141d18b120c","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Removed superfluous JitManager argument from passes\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/b6b114c1aeaa996a4bf8c1fd409e8141d18b120c"},{"sha":"b3360f5c8b74906187a8801d83f2c4f73f3c025e","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Moved memory init out of core swr init\n\nAdded two new files for a wrapper function for initialization\n\nv2: added missing include for single architecture builds\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/b3360f5c8b74906187a8801d83f2c4f73f3c025e"},{"sha":"fb20ae0374425ae3aff2a50a498c7e2b428632a4","author":{"name":"Alok Hota","email":"da626974068c7010767aeff29c36740aa9b5a3d1@intel.com"},"message":"swr/rast: Adjusted avx512 primitive assembly for msvc codegen\n\nOptimize AVX-512 PA Assemble (PA_STATE_OPT). Reduced generated code by\nabout 4x, MSVC compiler was going crazy making temporaries and\nsplit-loading inputs onto the stack unless explicit AVX-512 load ops\nwere added\n\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/fb20ae0374425ae3aff2a50a498c7e2b428632a4"},{"sha":"d21c086d819d78fb3f6abcbb14aa492970f442aa","author":{"name":"Scott D Phillips","email":"869de412a74df48368498a2fabd4c27e6a0922a9@intel.com"},"message":"i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear\n\nThe reference for MOVNTDQA says:\n\n    For WC memory type, the nontemporal hint may be implemented by\n    loading a temporary internal buffer with the equivalent of an\n    aligned cache line without filling this data to the cache.\n    [...] Subsequent MOVNTDQA reads to unread portions of the WC\n    cache line will receive data from the temporary internal\n    buffer if data is available.\n\nThis hidden cache line sized temporary buffer can improve the\nread performance from wc maps.\n\nv2: Add mfence at start of tiled_to_linear for streaming loads (Chris)\n\nReviewed-by: Chris Wilson <chris@chris-wilson.co.uk>\nReviewed-by: Matt Turner <mattst88@gmail.com>\nAcked-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/d21c086d819d78fb3f6abcbb14aa492970f442aa"},{"sha":"a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"st/mesa: simplify lastLevel determination in st_finalize_texture\n\nThis fixes shader images where we always bind stObj->pt and not individual\ngl_texture_images.\n\nRoughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308\nwhich does a similar thing but for a different reason.\n\nThis fixes GL CTS assertion failures introduced by Ilia.\n\nCc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1"},{"sha":"92ea9329e5eacf9a44ed30b3d72038a411eb771a","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"radeonsi: fix incorrect parentheses around VS-PS varying elimination\n\nI don't know if it caused issues.\n\nCc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/92ea9329e5eacf9a44ed30b3d72038a411eb771a"},{"sha":"a7d61c075366ebdc0b77267f5bf0dbd6102d6920","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"radeonsi: fix color inputs/outputs for GS and tess\n\nGS is tested, tessellation is untested.\n\nHave outputs_written_before_ps for HW VS and outputs_written for other\nstages. The reason is that COLOR and BCOLOR alias for HW VS, which\ndrives elimination of VS outputs based on PS inputs.\n\nReviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/a7d61c075366ebdc0b77267f5bf0dbd6102d6920"},{"sha":"2f65c67043529f8f7fca8514f88251f935e61c2c","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"radeonsi: fix passing gl_ClipVertex for GS and tess\n\nAlso add the fprintf call.\n\nReviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/2f65c67043529f8f7fca8514f88251f935e61c2c"},{"sha":"ae514ca695a599cdd0b7c22f48fd4d721671b0cb","author":{"name":"Jason Ekstrand","email":"b186559eaedf698788888c8a2559b4efb4db10d6@intel.com"},"message":"intel/blorp: Support blits and clears on surfaces with offsets\n\nFor certain EGLImage cases, we represent a single slice or LOD of an\nimage with a byte offset to a tile and X/Y intratile offsets to the\ngiven slice.  Most of i965 is fine with this but it breaks blorp.  This\nis a terrible way to represent slices of a surface in EGL and we should\nstop some day but that's a very scary and thorny path.  This gets blorp\nto start working with those surfaces and fixes some dEQP EGL test bugs.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629\nCc: mesa-stable@lists.freedesktop.org\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/ae514ca695a599cdd0b7c22f48fd4d721671b0cb"},{"sha":"18c50498db078f8bfbf1f8135b4e72ed479e32d9","author":{"name":"Marek Olšák","email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com"},"message":"radeonsi: remove unused variable addr_vec\n\ntrivial","distinct":false,"url":"https://api.github.com/repos/tarceri/Mesa/commits/18c50498db078f8bfbf1f8135b4e72ed479e32d9"}]}
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