{"action":"created","issue":{"url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/36","repository_url":"https://api.github.com/repos/riscv/riscv-v-spec","labels_url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/36/labels{/name}","comments_url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/36/comments","events_url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/36/events","html_url":"https://github.com/riscv/riscv-v-spec/issues/36","id":372333748,"node_id":"MDU6SXNzdWUzNzIzMzM3NDg=","number":36,"title":"unclear on how vemaxw interacts with s/d/q registers (vregd, vregq)","user":{"login":"vbx-glemieux","id":5769177,"node_id":"MDQ6VXNlcjU3NjkxNzc=","avatar_url":"https://avatars1.githubusercontent.com/u/5769177?v=4","gravatar_id":"","url":"https://api.github.com/users/vbx-glemieux","html_url":"https://github.com/vbx-glemieux","followers_url":"https://api.github.com/users/vbx-glemieux/followers","following_url":"https://api.github.com/users/vbx-glemieux/following{/other_user}","gists_url":"https://api.github.com/users/vbx-glemieux/gists{/gist_id}","starred_url":"https://api.github.com/users/vbx-glemieux/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/vbx-glemieux/subscriptions","organizations_url":"https://api.github.com/users/vbx-glemieux/orgs","repos_url":"https://api.github.com/users/vbx-glemieux/repos","events_url":"https://api.github.com/users/vbx-glemieux/events{/privacy}","received_events_url":"https://api.github.com/users/vbx-glemieux/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2018-10-21T16:46:08Z","updated_at":"2018-10-27T05:29:53Z","closed_at":null,"author_association":"NONE","body":"I don't understand how vemaxw interacts with vregd and vregq specifications.\r\n\r\nUsing vregd and vregq, some vectors can be made twice as wide (double or quad words). The base registers are words.\r\n\r\nIf I change vemaxw to be 16b, does it mean the s registers remain 32b in width, but all data operations are 16b in width (leaving upper 16 bits of each element untouched)?  Or does mean the s registers are now 16b in size, stored in a packed format, and the allowed vector length is twice as long? I believe it means the latter, but this is not clear to me in the spec.\r\n\r\nHow, then, should the 'd' and 'q' registers be treated? Do they remain 64b/128b in size, but all data operations remain at 16b (so upper 48 or 112 bits of each element are untouched)? Or are they now 32b and 64b in size, but also twice as long? Again, I'd assume it would have to mirror the s case, so they should now be 32b and 64b in size but twice as long. \r\n\r\nIs it valid to have operations between differently sized registers (s, d, q)? It must be, since masking must always be done with v0 and that should be combined with a d or q register (making all the registers the same length means masks from v0 apply to d or q registers on an element-by-element basis). IF different sized register operations can be mixed, this implies there is some size conversion being done (when sources are mismatched, or destination mismatches) ==> this implies significant data shuffling between lanes is required to match the element locations of the larger size vectors. Also, should I assume this conversion is done in the same way as vcvt when downsizing, and when upsizing should sign or zero extension is being done (eg, on a vadd)?\r\n"},"comment":{"url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/comments/433592656","html_url":"https://github.com/riscv/riscv-v-spec/issues/36#issuecomment-433592656","issue_url":"https://api.github.com/repos/riscv/riscv-v-spec/issues/36","id":433592656,"node_id":"MDEyOklzc3VlQ29tbWVudDQzMzU5MjY1Ng==","user":{"login":"vbx-glemieux","id":5769177,"node_id":"MDQ6VXNlcjU3NjkxNzc=","avatar_url":"https://avatars1.githubusercontent.com/u/5769177?v=4","gravatar_id":"","url":"https://api.github.com/users/vbx-glemieux","html_url":"https://github.com/vbx-glemieux","followers_url":"https://api.github.com/users/vbx-glemieux/followers","following_url":"https://api.github.com/users/vbx-glemieux/following{/other_user}","gists_url":"https://api.github.com/users/vbx-glemieux/gists{/gist_id}","starred_url":"https://api.github.com/users/vbx-glemieux/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/vbx-glemieux/subscriptions","organizations_url":"https://api.github.com/users/vbx-glemieux/orgs","repos_url":"https://api.github.com/users/vbx-glemieux/repos","events_url":"https://api.github.com/users/vbx-glemieux/events{/privacy}","received_events_url":"https://api.github.com/users/vbx-glemieux/received_events","type":"User","site_admin":false},"created_at":"2018-10-27T05:29:53Z","updated_at":"2018-10-27T05:29:53Z","author_association":"NONE","body":"@chenwei-tw It is different for every instruction -- see https://github.com/riscv/riscv-v-spec/blob/master/vector-op-types.csv under column heading \"Dst Type (dst_width = src_width / 2)\""}}
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