{"push_id":2916367936,"size":4,"distinct_size":4,"ref":"refs/heads/_4_4__powerpc_64s_hash_add_more_barriers_for_slb_preloading_mbox_next","head":"ef7d7205335b445b365d23cc974efe300d146076","before":"b1d38629601b53ea06b69970550b1425e0c4b25d","commits":[{"sha":"969d69a549e03b7b86bdd5a52f48add57f666d60","author":{"name":"Nicholas Piggin","email":"24829078df5003d9dd1dd871ca2aeb0b1cf95ef4@gmail.com"},"message":"powerpc/64: add struct int_regs to save additional registers on stack\n\nstruct pt_regs is part of the user ABI and also the fundametal\nstructure for saving registers at interrupt.\n\nThe generic kernel code makes it difficult to completely decouple\nthese, but it's easy enough to add additional space required to save\nmore registers. Create a struct int_stack with struct pt_regs at\noffset 0.\n\nThis is required for a following fix to save the PPR SPR on stack.\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/969d69a549e03b7b86bdd5a52f48add57f666d60"},{"sha":"9ed287f1b5e3c236826b29cf2e41c072cd3208f1","author":{"name":"Nicholas Piggin","email":"24829078df5003d9dd1dd871ca2aeb0b1cf95ef4@gmail.com"},"message":"powerpc/64: interrupts save PPR on stack rather than thread_struct\n\nPPR is the odd register out when it comes to interrupt handling,\nit is saved in current->thread.ppr while all others are saved on\nthe stack.\n\nThe difficulty with this is that accessing thread.ppr can cause a\nSLB fault, but the SLB fault handler implementation in C change had\nassumed the normal exception entry handlers would not cause an SLB\nfault.\n\nFix this by allocating room in the interrupt stack to save PPR.\n\nFixes: 5e46e29e6a97 (\"powerpc/64s/hash: convert SLB miss handlers to C\")\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/9ed287f1b5e3c236826b29cf2e41c072cd3208f1"},{"sha":"71f7f85d5e366466a93a97f6b213a4bc2b9e5abf","author":{"name":"Nicholas Piggin","email":"24829078df5003d9dd1dd871ca2aeb0b1cf95ef4@gmail.com"},"message":"powerpc/64s/hash: Fix preloading of SLB entries\n\nslb_setup_new_exec and preload_new_slb_context assumed if an address\nmissed the preload cache, then it would not be in the SLB and could\nbe added. This is wrong if the preload cache has started to overflow.\nThis can cause SLB multi-hits on user addresses.\n\nThat assumption came from an earlier version of the patch which\ncleared the preload cache when copying the task, but even that was\ntechnically wrong because some user accesses occur before these\npreloads, and the preloads themselves could overflow the cache\ndepending on the size.\n\nFixes: 89ca4e126a3f (\"powerpc/64s/hash: Add a SLB preload cache\")\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/71f7f85d5e366466a93a97f6b213a4bc2b9e5abf"},{"sha":"ef7d7205335b445b365d23cc974efe300d146076","author":{"name":"Nicholas Piggin","email":"24829078df5003d9dd1dd871ca2aeb0b1cf95ef4@gmail.com"},"message":"powerpc/64s/hash: add more barriers for slb preloading\n\nIn several places, more care has to be taken to prevent compiler or\nCPU re-ordering of memory accesses into critical sections that must\nnot take SLB faults.\n\nFixes: 5e46e29e6a97 (\"powerpc/64s/hash: convert SLB miss handlers to C\")\nFixes: 89ca4e126a3f (\"powerpc/64s/hash: Add a SLB preload cache\")\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ruscur/linux/commits/ef7d7205335b445b365d23cc974efe300d146076"}]}
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