{"action":"created","issue":{"url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/11917","repository_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr","labels_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/11917/labels{/name}","comments_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/11917/comments","events_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/11917/events","html_url":"https://github.com/zephyrproject-rtos/zephyr/issues/11917","id":388340347,"node_id":"MDU6SXNzdWUzODgzNDAzNDc=","number":11917,"title":"GPIO: need generic API for optimized pin read/write operations","user":{"login":"pabigot","id":964298,"node_id":"MDQ6VXNlcjk2NDI5OA==","avatar_url":"https://avatars1.githubusercontent.com/u/964298?v=4","gravatar_id":"","url":"https://api.github.com/users/pabigot","html_url":"https://github.com/pabigot","followers_url":"https://api.github.com/users/pabigot/followers","following_url":"https://api.github.com/users/pabigot/following{/other_user}","gists_url":"https://api.github.com/users/pabigot/gists{/gist_id}","starred_url":"https://api.github.com/users/pabigot/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/pabigot/subscriptions","organizations_url":"https://api.github.com/users/pabigot/orgs","repos_url":"https://api.github.com/users/pabigot/repos","events_url":"https://api.github.com/users/pabigot/events{/privacy}","received_events_url":"https://api.github.com/users/pabigot/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2018-12-06T18:27:49Z","updated_at":"2018-12-06T18:50:31Z","closed_at":null,"author_association":"COLLABORATOR","body":"I think we need macro-based APIs to avoid function call overhead to set and clear bits, which allow SoC-specific code to provide small and fast assembly implementations. This would be needed for time-sensitive bit banging protocol implementations.\r\n\r\n_Originally posted by @mbolivar in https://github.com/zephyrproject-rtos/zephyr/issues/2288#issuecomment-433343055_"},"comment":{"url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/comments/444985019","html_url":"https://github.com/zephyrproject-rtos/zephyr/issues/11917#issuecomment-444985019","issue_url":"https://api.github.com/repos/zephyrproject-rtos/zephyr/issues/11917","id":444985019,"node_id":"MDEyOklzc3VlQ29tbWVudDQ0NDk4NTAxOQ==","user":{"login":"pfalcon","id":500451,"node_id":"MDQ6VXNlcjUwMDQ1MQ==","avatar_url":"https://avatars3.githubusercontent.com/u/500451?v=4","gravatar_id":"","url":"https://api.github.com/users/pfalcon","html_url":"https://github.com/pfalcon","followers_url":"https://api.github.com/users/pfalcon/followers","following_url":"https://api.github.com/users/pfalcon/following{/other_user}","gists_url":"https://api.github.com/users/pfalcon/gists{/gist_id}","starred_url":"https://api.github.com/users/pfalcon/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/pfalcon/subscriptions","organizations_url":"https://api.github.com/users/pfalcon/orgs","repos_url":"https://api.github.com/users/pfalcon/repos","events_url":"https://api.github.com/users/pfalcon/events{/privacy}","received_events_url":"https://api.github.com/users/pfalcon/received_events","type":"User","site_admin":false},"created_at":"2018-12-06T18:50:31Z","updated_at":"2018-12-06T18:50:31Z","author_association":"MEMBER","body":"> I think we need macro-based APIs to avoid function call overhead to set and clear bits, which allow SoC-specific code to provide small and fast assembly implementations.\r\n\r\nNeed for what? Setting/clearing bits in Zephyr works as follows:\r\n\r\n1. A system call is issued, a relatively expensive operation (CPU exception, saving of all/many registers).\r\n2. MMU context is replaced.\r\n3. A driver is called via indirect call.\r\n4. A driver for example performs pin operation over GPIO extender connected over I2C.\r\n\r\nIt's unclear how to reconcile this view of Zephyr with a fact that specific SoCs has a way to toggle a limited subset of pins (builtin into SoC) using a couple of instructions.\r\n"}}
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