{"push_id":2644050513,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"75f4cd0c543171fb46b797898be06c2af080cf26","before":"bb5d08a4d089ce90085a86d25c531e58eeb456ab","commits":[{"sha":"2cdc5636762a18da6b89ce42a44b62359bf42d47","author":{"name":"manu","email":"158873d90a7ef40f3637a222b7329c09d0222554@FreeBSD.org"},"message":"rk_pll: Add support for mode\n\nRockChip PLL have two modes controlled by a register, a \"slow mode\" (the\ndefault one) where the frequency is derived from the 24Mhz oscillator on the\nboard, and a \"normal\" one when the pll take it's input from the real PLL output.\n\nDefault the mode to normal for all the PLLs.","distinct":true,"url":"https://api.github.com/repos/evadot/freebsd/commits/2cdc5636762a18da6b89ce42a44b62359bf42d47"},{"sha":"75f4cd0c543171fb46b797898be06c2af080cf26","author":{"name":"manu","email":"158873d90a7ef40f3637a222b7329c09d0222554@FreeBSD.org"},"message":"rk_armclk: Add the write mask to the register mux value\n\nThis was omitted in r334112 and r334996 which cause the PLL to not correctly\nreparent, leaving the armclk to be derived from the APLL instead of the NPLL.\nThe arm core clock is now correctly set to 600Mhz via the assigned-clock present\nin the DTB.","distinct":true,"url":"https://api.github.com/repos/evadot/freebsd/commits/75f4cd0c543171fb46b797898be06c2af080cf26"}]}
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