{"action":"created","comment":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/comments/78450233","id":78450233,"diff_hunk":"@@ -24,88 +26,74 @@ case object BankIdLSB extends Field[Int]\n case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]\n /** Function for building some kind of tile connected to a reset signal */\n case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]\n-/** A string describing on-chip devices, readable by target software */\n-case object ConfigString extends Field[Array[Byte]]\n-/** Number of external interrupt sources */\n-case object NExtInterrupts extends Field[Int]\n-/** Interrupt controller configuration */\n-case object PLICKey extends Field[PLICConfig]\n /** The file to read the BootROM contents from */\n case object BootROMFile extends Field[String]\n-/** Export an external MMIO slave port */\n-case object ExportMMIOPort extends Field[Boolean]\n-/** Expose additional TileLink client ports */\n-case object NExternalClients extends Field[Int]\n-/** Extra top-level ports exported from the coreplex */\n-case object ExtraCoreplexPorts extends Field[Parameters => Bundle]\n \n trait HasCoreplexParameters {\n   implicit val p: Parameters\n-  lazy val nTiles = p(NTiles)\n   lazy val nMemChannels = p(NMemoryChannels)\n   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)\n   lazy val nBanks = nMemChannels*nBanksPerMemChannel\n   lazy val lsb = p(BankIdLSB)\n   lazy val innerParams = p.alterPartial({ case TLId => \"L1toL2\" })\n   lazy val outermostParams = p.alterPartial({ case TLId => \"Outermost\" })\n   lazy val outermostMMIOParams = p.alterPartial({ case TLId => \"MMIO_Outermost\" })\n-  lazy val nExtClients = p(NExternalClients)\n-  lazy val exportMMIO = p(ExportMMIOPort)\n+  lazy val configString = p(rocketchip.ConfigString).get\n+  lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get\n }\n \n-abstract class Coreplex(implicit val p: Parameters) extends Module\n+case class CoreplexConfig(\n+    nTiles: Int,\n+    nExtInterrupts: Int,\n+    nSlaves: Int,\n+    hasSupervisor: Boolean,\n+    hasExtMMIOPort: Boolean)\n+{\n+  val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)\n+}\n+\n+abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Module\n     with HasCoreplexParameters {\n-  class CoreplexIO(implicit val p: Parameters) extends Bundle {\n-    val mem  = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))\n-    val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip\n-    val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))\n-    val interrupts = Vec(p(NExtInterrupts), Bool()).asInput\n+  class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {\n+    val master = new Bundle {\n+      val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))","path":"src/main/scala/coreplex/Coreplex.scala","position":64,"original_position":64,"commit_id":"d985cdfc6622df6575acad6b6fe6f3c1fcb72299","original_commit_id":"d985cdfc6622df6575acad6b6fe6f3c1fcb72299","user":{"login":"zhemao","id":433799,"avatar_url":"https://avatars.githubusercontent.com/u/433799?v=3","gravatar_id":"","url":"https://api.github.com/users/zhemao","html_url":"https://github.com/zhemao","followers_url":"https://api.github.com/users/zhemao/followers","following_url":"https://api.github.com/users/zhemao/following{/other_user}","gists_url":"https://api.github.com/users/zhemao/gists{/gist_id}","starred_url":"https://api.github.com/users/zhemao/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/zhemao/subscriptions","organizations_url":"https://api.github.com/users/zhemao/orgs","repos_url":"https://api.github.com/users/zhemao/repos","events_url":"https://api.github.com/users/zhemao/events{/privacy}","received_events_url":"https://api.github.com/users/zhemao/received_events","type":"User","site_admin":false},"body":"The only things that depended on it are in the Coreplex itself and thus have access to CoreplexConfig. I've done the refactor in a separate PR #276. Could you take a look.","created_at":"2016-09-12T20:40:27Z","updated_at":"2016-09-12T20:40:27Z","html_url":"https://github.com/ucb-bar/rocket-chip/pull/259#discussion_r78450233","pull_request_url":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/259","_links":{"self":{"href":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/comments/78450233"},"html":{"href":"https://github.com/ucb-bar/rocket-chip/pull/259#discussion_r78450233"},"pull_request":{"href":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/259"}}},"pull_request":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/259","id":84441790,"html_url":"https://github.com/ucb-bar/rocket-chip/pull/259","diff_url":"https://github.com/ucb-bar/rocket-chip/pull/259.diff","patch_url":"https://github.com/ucb-bar/rocket-chip/pull/259.patch","issue_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/259","number":259,"state":"closed","locked":false,"title":"Refactor Periphery","user":{"login":"yunsup","id":703957,"avatar_url":"https://avatars.githubusercontent.com/u/703957?v=3","gravatar_id":"","url":"https://api.github.com/users/yunsup","html_url":"https://github.com/yunsup","followers_url":"https://api.github.com/users/yunsup/followers","following_url":"https://api.github.com/users/yunsup/following{/other_user}","gists_url":"https://api.github.com/users/yunsup/gists{/gist_id}","starred_url":"https://api.github.com/users/yunsup/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/yunsup/subscriptions","organizations_url":"https://api.github.com/users/yunsup/orgs","repos_url":"https://api.github.com/users/yunsup/repos","events_url":"https://api.github.com/users/yunsup/events{/privacy}","received_events_url":"https://api.github.com/users/yunsup/received_events","type":"User","site_admin":false},"body":"This commit changes the Periphery to use tilelink2 LazyModules, and splits Peripheries into traits, which can later be chained together using \"with\"s on top of the BaseTop.  This makes rocket-chip to be used more as a library, therefore I changed the top-level module name to \"ExampleTop\" to clearly denote it's an example.  Users of rocket-chip will add their own Peripheries to add more interesting stuff between the Coreplex and the I/Os of a chip.  This change is intended to supersede the \"extra\" pattern.\r\n\r\nFor those who are curious about this programming pattern, search for the \"cake pattern\".  h/t @hcook \r\n\r\nDon't merge this PR yet.  I need to do more testing and turn a couple more devices into traits before we merge this upstream.  Once I change all devices which use the device builder infrastructure, I'll respond to this PR, so that the code can be reviewed further and merged upstream.\r\n\r\nPlease let me know if you have feedback in the mean time.\r\n\r\nh/t @terpstra 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