{"push_id":1206922444,"size":38,"distinct_size":0,"ref":"refs/heads/coverity_scan","head":"014e86ec2882e6b7722a043879a00dcef143fccb","before":"7287a5a75cab2e0075c1d997b727ab740f81db5a","commits":[{"sha":"eda93050c75d3f3ef4509d3faccc451b0946b607","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"driver: ioremap the hypervisor firmware to any kernel address\n\nAt the moment the Linux driver maps the Jailhouse binary to\nJAILHOUSE_BASE. The underlying assumption is that Linux may map the\nfirmware (in the Linux kernel space), to the same virtual address it\nhas been built to run from.\n\nThis assumption is unworkable on ARMv8 processors running in AArch64\nmode. Kernel memory is allocated in a high address region, that is\nnot addressable from EL2, where the hypervisor will run from.\n\nThis patch removes the assumption, by introducing the\nJAILHOUSE_BORROW_ROOT_PT define, which signals the behavior of the\ncurrent architectures.\n\nWe also turn the entry point in the header, into an offset from the\nJailhouse load address, so we can enter the image regardless of\nwhere it  will be mapped.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/eda93050c75d3f3ef4509d3faccc451b0946b607"},{"sha":"37f0f7e117964c0c24a67485d3e8ca4781fab734","author":{"name":"Dmitry Voytik","email":"b3e72d9e92287b26a11f1b19454708b74de04109@huawei.com"},"message":"driver: sync I-cache, D-cache and memory\n\nSyncronize I-cache with D-cache after loading the hypervisor\nimage or a cell image. This must be done in arm64 according to\nARMv8 ARM spec. See page 1712, D3.4.6 \"Non-cacheable accesses\nand instruction caches\".\n\nThis patch fixes coherency problems observed on real HW targets.\nOn x86 this operation is a NOP.\n\nSigned-off-by: Dmitry Voytik <dmitry.voytik@huawei.com>\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\n[antonios.motakis@huawei.com: edited comments]\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/37f0f7e117964c0c24a67485d3e8ca4781fab734"},{"sha":"49a683f3a3823a445d88a2021dc69993d6edff8b","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"core: make phys_processor_id() return unsigned long\n\n32 bits ought not be enough for anybody.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/49a683f3a3823a445d88a2021dc69993d6edff8b"},{"sha":"11cc0e0cf21d53544bfe19977af1520981769e34","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"core: panic_stop: print current cell only if it has been set\n\nCurrently during a panic, panic_stop will print the current cell\non the CPU where the panic occurred. However, if the hypervisor\npanics sufficiently early during initialization, we may end up in\na situation where the root cell has not been initialized. This can\neasily cause a trap loop, making the panic output less useful.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/11cc0e0cf21d53544bfe19977af1520981769e34"},{"sha":"6b74f910dc248be969f16dc57e12412412f41b36","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"core: Add support for aligned page allocation\n\nRefactor page_alloc to page_alloc_internal which accepts an additional\nconstraint for its allocation: align_mask. The allocated region will now\nhave its start page chosen so that page_number & align_mask is zero. If\nno alignment is required, align_mask just needs to be set to 0. This is\nwhat page_alloc exploits.\n\nHowever, the new function page_alloc_aligned is introduces to return\npage regions aligned according to their size (num pages will be aligned\nby num * PAGE_SIZE). This implied that num needs to be a power of two.\n\nThis will be used on the AArch64 port of Jailhouse to support physical\naddress ranges from 40 to 44 bits: in these configurations, the initial\npage table level may take up multiple consecutive pages.\n\nBased on patch by Antonios Motakis.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/6b74f910dc248be969f16dc57e12412412f41b36"},{"sha":"af24262ac5020eda9da14db3ab2e84f8297fd4a2","author":{"name":"Claudio Fontana","email":"3eb788fefa10fc6ac0a005ecd36a3f647e9e1baa@huawei.com"},"message":"core: lib: replace ARM memcpy implementation with generic version\n\nRemove the memcpy implementation from the ARM port, and add a\ngeneric version to the core library for all architectures.\n\nSigned-off-by: Claudio Fontana <claudio.fontana@huawei.com>\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\n[antonios.motakis@huawei.com: removed all signs of weakness!]\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/af24262ac5020eda9da14db3ab2e84f8297fd4a2"},{"sha":"6936d5c860976325b6cd4e2fb30f251db0f133fd","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: psci: support multiple affinity levels in MPIDR\n\nPSCI actually takes CPU parameters by the MPIDR id, which may\ndiffer from the logical id of the CPU. This patch is the first step\ninto properly handling the CPU affinity levels in the MPIDR.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\n[Jan: add missing processor.h include to setup.c]\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/6936d5c860976325b6cd4e2fb30f251db0f133fd"},{"sha":"f404b89d34d44bd23dba889d495564c1fbed992d","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: replace IS_PSCI_FN macro with more explicit versions\n\nThe previous version of the macro allows for more false positives\nthan necessary.\n\nReplace the macro with IS_PSCI_32 and IS_PSCI_UBOOT macros, that\nexplicitly check for the 32 bit PSCI IDs, and the PSCI 0.1 IDs\nused by uboot. ARMv8 will need an additinal check for the IDs\nof 64 bit PSCI functions.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/f404b89d34d44bd23dba889d495564c1fbed992d"},{"sha":"bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: move the handle_irq_route function to the GICv3 module\n\nThe handle_irq_route function is not needed with the GICv2.\n\nOn the ARMv8 port we will not assign a virt_id to each CPU,\nopting to use the MPIDR as much as we can from the start.\nGICv3 will need heavier refactoring for this purpose; by moving\nthis function we can reuse the GICv2 code on ARMv8.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\n[Jan: implement stub in v2 to reduce #ifdefs]\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d"},{"sha":"b2b588833a6e9ade955a723242072120de9f1354","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: prepare port for 48 bit PARange support\n\nWe currently support 3 levels of page tables for a 39 bits PA range\non ARM. This patch implements support for 4 level page tables,\nand 3 level page tables with a concatenated level 1 root page\ntable.\n\nOn AArch32 we stick with the current restriction of building for\na 39 bit physical address space; however this change will allow\nus to support a 40 to 48 bit PARange on AArch64.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/b2b588833a6e9ade955a723242072120de9f1354"},{"sha":"0c0a0086c1deabf39aad0d3f0320da2874603139","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: put the value of VTCR for cells in a define\n\nWe can reuse the code under hypervisor/arch/arm/mmu_cell.c for the\nAArch64 port, save for the value we use for the VTCRL. AArch64 will\nneed in addition to the flags set by the AArch32 port, to set the\nsize of the address space.\n\nWe put this behind a define in asm/paging.h to allow this reuse.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/0c0a0086c1deabf39aad0d3f0320da2874603139"},{"sha":"89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6","author":{"name":"Antonios Motakis","email":"5605c9d25b52cbb321fed6fb1f599085341f1519@huawei.com"},"message":"arm: hide TLB flush behind a macro\n\nHide TLB flushes issues by the MMU code behind a macro, so we can\nincrease our chances of reusing some of this code.\n\nSigned-off-by: Antonios Motakis <antonios.motakis@huawei.com>\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6"},{"sha":"c75977ab419f15af28aa57a03dcc2dccdec62428","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"arm: Remove unused struct pending_irq\n\nLeftover of 8b121b498b.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/c75977ab419f15af28aa57a03dcc2dccdec62428"},{"sha":"d99b6e21844e3c99b7195346a08611b3cd46a057","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"config, core: Improve irqchip configuration\n\nThis aims at supporting irqchips with more than 64 pins. The idea is to\nuse multiple entries in this case, each describing a distinct set of the\npins. Therefore, a pin_base field is introduced to jailhouse_irqchip.\nMoreover, we expand the number of pins for each entry to 128.\n\nWe do not exploit the extended pin number on ARM yet, but stick with\n64 pins for now. Succeeding change sets will tackle it.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/d99b6e21844e3c99b7195346a08611b3cd46a057"},{"sha":"f2931b157d70e7257da839588cb2a325dc2a0aa6","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"arm: Use full bitmap to manage per-cell interrupt access","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/f2931b157d70e7257da839588cb2a325dc2a0aa6"},{"sha":"85783c01aa07f911c6eab0f53536a82a7d207f2f","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"config: Correct / comment GIC irqchip addresses\n\nWe will soon evaluate them, so their correct value starts to matter.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/85783c01aa07f911c6eab0f53536a82a7d207f2f"},{"sha":"d14d1703a7f285a93fde6d3198ab639ec72bb0b8","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"arm: Rename reg parameter of handle_irq_target to irq\n\nReflects better what this is about.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/d14d1703a7f285a93fde6d3198ab639ec72bb0b8"},{"sha":"b7857f0e03f4caea5b383a5722ce653bfd7e8ad5","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"arm: Print IRQ number rather than SPI on handle_irq_target errors\n\nConfiguration and other reportings are based on absolute IDs as well.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/b7857f0e03f4caea5b383a5722ce653bfd7e8ad5"},{"sha":"902ee9cfd32652f6926da709b259d46a68bdebf4","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"arm: Rework spi_in_cell to irqchip_irq_in_cell\n\nMake use of the the fully populated irq_bitmap and enhance spi_in_cell\nto consider SGIs and PPIs as well. This allows to simplify\nrestrict_bitmask_access.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/902ee9cfd32652f6926da709b259d46a68bdebf4"},{"sha":"ddc4a66cfa509b422a5c385783d2e863c7f875dd","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"core: Introduce first_cpu\n\nExtracted from patch of Antonios Motakis: Avoid the barely readable\n\"for_each_cpu(...) break;\" pattern.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>","distinct":false,"url":"https://api.github.com/repos/siemens/jailhouse/commits/ddc4a66cfa509b422a5c385783d2e863c7f875dd"}]}
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