{"push_id":1433948989,"size":1000,"distinct_size":4,"ref":"refs/heads/if-convert","head":"71adc6e9b2f0d21dbfff42e74c2ae924de23f896","before":"b5acc51f3a3f4bb4c0680bfadeafc95672143445","commits":[{"sha":"78c322d6f14864d31716000cff32d237768e813d","author":{"name":"Sanjay Patel","email":"8a358757f1b64d62facccc1fd839683fb6856b45@rotateright.com"},"message":"[ValueTracking] recognize obfuscated variants of umin/umax\n\nThe smallest tests that expose this are codegen tests (because SelectionDAGBuilder::visitSelect() uses matchSelectPattern\nto create UMAX/UMIN nodes), but it's also possible to see the effects in IR alone with folds of min/max pairs.\n\nIf these were written as unsigned compares in IR, InstCombine canonicalizes the unsigned compares to signed compares. \nIe, running the optimizer pessimizes the codegen for this case without this patch:\n\ndefine <4 x i32> @umax_vec(<4 x i32> %x) {\n  %cmp = icmp ugt <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>\n  %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>\n  ret <4 x i32> %sel\n}\n\n$ ./opt umax.ll -S | ./llc -o - -mattr=avx\n\nvpmaxud LCPI0_0(%rip), %xmm0, %xmm0\n\n$ ./opt -instcombine umax.ll -S | ./llc -o - -mattr=avx\n\nvpxor %xmm1, %xmm1, %xmm1\nvpcmpgtd  %xmm0, %xmm1, %xmm1\nvmovaps LCPI0_0(%rip), %xmm2    ## xmm2 = [2147483647,2147483647,2147483647,2147483647]\nvblendvps %xmm1, %xmm0, %xmm2, %xmm0\n\nDifferential Revision: https://reviews.llvm.org/D26096\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286318 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/78c322d6f14864d31716000cff32d237768e813d"},{"sha":"f70da781a972f16bdf9270c7df120b1a9bec7127","author":{"name":"Dean Michael Berris","email":"6b0af69dd05a094d46606b1b8f141285184892b2@google.com"},"message":"[XRay][Docs] Add documentation for XRay in LLVM\n\nSummary:\nThis is the initial version of the documentation for how to use XRay as\nit stands in LLVM, Clang, and compiler-rt. We leave some room for later\nexpansion mentioining what is work in progress and what could be\nexpected moving forward.\n\nWe also give a high level overview of future work that's both ongoing\nand planned.\n\nReviewers: echristo, dblaikie, chandlerc\n\nSubscribers: mehdi_amini, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D26386\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286319 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/f70da781a972f16bdf9270c7df120b1a9bec7127"},{"sha":"d9a93c097e4ac496350f195ebe92e70d3e6d2110","author":{"name":"Peter Collingbourne","email":"6214814a67b9688a08e8c6dc7fa5dee076dddc8d@pcc.me.uk"},"message":"Bitcode: Change the BitcodeReader to use llvm::Error internally.\n\nDifferential Revision: https://reviews.llvm.org/D26430\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286323 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/d9a93c097e4ac496350f195ebe92e70d3e6d2110"},{"sha":"3885b5c47869c7fb3b007236c403efcf1171fece","author":{"name":"Dehao Chen","email":"69b64b8e13ca0a46e266cce1ec43a6d7b55ddc1b@google.com"},"message":"Enable Loop Sink pass for functions that has profile.\n\nSummary: For functions with profile data, we are confident that loop sink will be optimal in sinking code.\n\nReviewers: davidxl, hfinkel\n\nSubscribers: mehdi_amini, mzolotukhin, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D26155\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286325 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/3885b5c47869c7fb3b007236c403efcf1171fece"},{"sha":"85f5302a7177e37d80a4506bb913bc5b6f40de72","author":{"name":"Peter Collingbourne","email":"6214814a67b9688a08e8c6dc7fa5dee076dddc8d@pcc.me.uk"},"message":"Bitcode: Remove the remnants of the BitcodeDiagnosticInfo class.\n\nThe BitcodeReader no longer produces BitcodeDiagnosticInfo diagnostics.\nThe only remaining reference was in the gold plugin; the code there has been\ndead since we stopped producing InvalidBitcodeSignature error codes in r225562.\nWhile at it remove the InvalidBitcodeSignature error code.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286326 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/85f5302a7177e37d80a4506bb913bc5b6f40de72"},{"sha":"9e4483688bd446d278b7bb3b807c0c4891956a53","author":{"name":"Mehdi Amini","email":"492be1fd3fd1bc2b95e34c58694617e62f530742@apple.com"},"message":"[doc] Remove explicit CMake version requirement for MSVC\n\nThe global minimum one is way past this version.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286328 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/9e4483688bd446d278b7bb3b807c0c4891956a53"},{"sha":"129c9fcdb8e103a5f9c71d5d1d73277600ef80a6","author":{"name":"Mehdi Amini","email":"492be1fd3fd1bc2b95e34c58694617e62f530742@apple.com"},"message":"Revert \"[ThinLTO] Prevent exporting of locals used/defined in module level asm\"\n\nThis reverts commit r286297.\nIntroduces a dependency from libAnalysis to libObject, which I missed\nduring the review.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286329 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/129c9fcdb8e103a5f9c71d5d1d73277600ef80a6"},{"sha":"2adde22ecd124c153c14ce594d868b3417f4101b","author":{"name":"Dean Michael Berris","email":"6b0af69dd05a094d46606b1b8f141285184892b2@google.com"},"message":"[XRay][docs] Fix llvm snippets to be well-formed\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286330 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/2adde22ecd124c153c14ce594d868b3417f4101b"},{"sha":"f43d5aff8dfbda90444ab5b42f73535ef8ef372a","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled.\n\nSummary:\nThis is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912.\n\nReviewers: delena, zvi\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D26322\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286339 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/f43d5aff8dfbda90444ab5b42f73535ef8ef372a"},{"sha":"89f0495611df29d8468d78d489d89b36ab3d5448","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Add test cases to demonstrate PR30947. We accidentally use 32 byte aligned store instructions when the original store was only 16 byte aligned if the store is from the lower bits of a subvector extract.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286341 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/89f0495611df29d8468d78d489d89b36ab3d5448"},{"sha":"4c1b9a2ab6c7fc7cc325b8096fad3dd0f38d4b51","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Use alignedstore256 in patterns that look for stores of the lower 256-bits of a 512-bit vector to use a 256-bit aligned store.\n\nPreviously we were only checking for 16 byte alignment instead of 32 byte alignment. Fixes PR30947.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286342 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/4c1b9a2ab6c7fc7cc325b8096fad3dd0f38d4b51"},{"sha":"106bb1fe2db88fe77458ec594c461c8428588dab","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Add more varied alignments to tests for storing the lower 128-bits of a 256 or 512-bit subvector extract.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286343 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/106bb1fe2db88fe77458ec594c461c8428588dab"},{"sha":"45b3e8f9df5d37f9c539c103f2ce6cc552c0173d","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[X86] Lower AVX512 and SSE intrinsics for CVTTPD2DQ to X86ISD::CVTTPD2DQ.\n\nSummary: This allows the SSE intrinsic to use the EVEX instruction when available. It also fixes EVEX to not use a weird (v4i32 (fp_to_sint v2f64)) node and it merges some isel patterns. This also fixes some cases that weren't combining vzmovl with cvttpd2dq to remove extra moves.\n\nReviewers: delena, zvi, RKSimon\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D26330\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286344 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/45b3e8f9df5d37f9c539c103f2ce6cc552c0173d"},{"sha":"1f641ae1c59ead4b6e600129c9d6af681450d1d3","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Add lowering to cvttpd2udq/cvttps2udq for fptoui v2f64/2f32 to 2i32\n\nThis patch adds support for fptoui to 2i32 from both 2f64 and 2f32, building on Simon's change for the signed version in r284459 and using AVX-512 instructions.\n\nIf we don't have VLX support we need to use a 512-bit operation for v2f64->v2i32 and extract the result.\n\nIt also recognises that cvttpd2udq zeroes the upper 64-bits of the xmm result.\n\nDifferential Revision: https://reviews.llvm.org/D26331\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286345 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/1f641ae1c59ead4b6e600129c9d6af681450d1d3"},{"sha":"32054b584b1111c4935f84f049e7520eb899679c","author":{"name":"Alexandros Lamprineas","email":"e40fd79cc1bfc1d1e0f6ece17d3742a5e208e269@arm.com"},"message":"[ARM] Loop Strength Reduction crashes when targeting ARM or Thumb.\n\nScalar Evolution asserts when not all the operands of an Add Recurrence\nExpression are loop invariants. Loop Strength Reduction should only\ncreate affine Add Recurrences, so that both the start and the step of\nthe expression are loop invariants.\n\nDifferential Revision: https://reviews.llvm.org/D26185\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286347 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/32054b584b1111c4935f84f049e7520eb899679c"},{"sha":"e9ba8f332af88f95ef59d9f00be5db2ddd4888ea","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[MachineScheduler] Comments fixing.\n\nThe name/comment of the third argument to the ScheduleDAGMI constructor\nis RemoveKillFlags and not IsPostRA. Only the comments are changed.\n\nReview: A Trick\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286350 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/e9ba8f332af88f95ef59d9f00be5db2ddd4888ea"},{"sha":"6192bd795fe9a9c977f49c43bb3697874bc407f2","author":{"name":"Simon Atanasyan","email":"3a69a7dd305e9c7705028afae27095688d25197a@atanasyan.com"},"message":"[mips] Add non-const getter for the Elf_Mips_Options class. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286351 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/6192bd795fe9a9c977f49c43bb3697874bc407f2"},{"sha":"73ce0c00e4f025a6eece55cf125ffaf0a5b06f28","author":{"name":"Pavel Labath","email":"151b4374ae0894129725cbc0ee8b2899fb4039fe@google.com"},"message":"[dsymutil] Replace TimeValue with TimePoint\n\nSummary:\nAll changes are pretty straight-forward. I chose to use TimePoints with\nsecond precision, as that is all that seems to be required here.\n\nReviewers: friss, zturner\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D25908\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286358 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/73ce0c00e4f025a6eece55cf125ffaf0a5b06f28"},{"sha":"517cd170c39f49a067aef93cbc4bd8f0a261f144","author":{"name":"Pavel Labath","email":"151b4374ae0894129725cbc0ee8b2899fb4039fe@google.com"},"message":"Zero-initialize chrono duration objects\n\nThe default duration constructor does not zero-initialize the object, we need to\ndo that manually.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286359 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/517cd170c39f49a067aef93cbc4bd8f0a261f144"},{"sha":"15f3ab0cb6e46004c2d6b47b54fe188fe942b361","author":{"name":"Pavel Labath","email":"151b4374ae0894129725cbc0ee8b2899fb4039fe@google.com"},"message":"Remove TimeValue usage from Scalar/SROA.cpp. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286361 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/15f3ab0cb6e46004c2d6b47b54fe188fe942b361"}]}
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