{"push_id":1156644528,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"fec5a06f964158444d626e04089eefc7737f836c","before":"2cb50bb99555bdfced3d71ab4f79e5c41ce28fbc","commits":[{"sha":"fec5a06f964158444d626e04089eefc7737f836c","author":{"name":"carll","email":"3be4c3ff322728028cba117263a3cdae985444f9@8f6e269a-dfd6-0310-a8e1-e2731360e62c"},"message":"Fix mtfsfi usage of W bit. (isa2.05,ppc64)\n \nFix mtfsfi usage of W bit.\nThe Wbit field was added in ISA 2.05, allowing updates to the 'other'\nhalf of the 64-bit FPSCR field.\nLogic and Support for that bit is in place, but a 'reserved field\nmust contain zeros' check was not updated, preventing the desired\npath from being taken.\n\nBugzilla 362894\n    \nSigned-off-by:  Will Schmidt <will_schmidt@vnet.ibm.com>\nPatch reviewed and verified by: Carl Love <cel@ibm.com>\n\n\ngit-svn-id: svn://svn.valgrind.org/vex/trunk@3221 8f6e269a-dfd6-0310-a8e1-e2731360e62c","distinct":true,"url":"https://api.github.com/repos/svn2github/valgrind-vex/commits/fec5a06f964158444d626e04089eefc7737f836c"}]}
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