{"push_id":1353042091,"size":15,"distinct_size":15,"ref":"refs/heads/linaro/gcc-6-branch","head":"493a6a7da66b065821b3a22446968b272b5c45bc","before":"e1214efb16d937d60b709efd5337d46046b81497","commits":[{"sha":"d9bdefc5f03ca6ce9a0fdd4ad62d32330704d660","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r237475.\n\t2016-06-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>\n\n\t* ifcvt.c (bb_ok_for_noce_multiple_sets): Allow simple lowpart\n\tregister subregs in SET_SRC.\n\n\tgcc/testsuite/\n\tBackport from trunk r237475.\n\t2016-06-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>\n\n\t* gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c: New test.\n\nChange-Id: I4ec7ce4a8f1657808d37c8500e10661401ccecf4","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/d9bdefc5f03ca6ce9a0fdd4ad62d32330704d660"},{"sha":"fd7276f78357492cfa8514b71204d3e4edb8b116","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r238588.\n\t2016-07-21  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>\n\n\t* tree-ssa-strlen.c (strlen_dom_walker::before_dom_children): Fix typo\n\tin comment.\n\nChange-Id: I8f790b9069966539b73b737277404d935a806cfb","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/fd7276f78357492cfa8514b71204d3e4edb8b116"},{"sha":"ef72a016d0245204f7dfb9e524832e0f1d388abc","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tlibgcc/\n\tBackport from trunk r240043.\n\t2016-09-09  James Greenhalgh  <james.greenhalgh@arm.com>\n\n\tPR target/63250\n\t*  Makefile.in (lib2funcs): Build _mulhc3 and _divhc3.\n\t* libgcc2.h (LIBGCC_HAS_HF_MODE): Conditionally define.\n\t(HFtype): Likewise.\n\t(HCtype): Likewise.\n\t(__divhc3): Likewise.\n\t(__mulhc3): Likewise.\n\t* libgcc2.c: Support _mulhc3 and _divhc3.\n\nChange-Id: If5fe0cfd670daca59e709646c53545186663e956","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/ef72a016d0245204f7dfb9e524832e0f1d388abc"},{"sha":"7408c1615036513fa7a2228592c9a35f36f9573c","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r239212.\n\t2016-08-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>\n\n\t* tree-ssa-ccp.c (extend_mask): New param sgn.\n\tRemove ORing with wi::mask.\n\t(get_default_value): Adjust call to extend_mask to pass sign.\n\t(evaluate_stmt): Likewise.\n\nChange-Id: Ia929df985c53ccc0b51d35d801f93d29c850a33d","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/7408c1615036513fa7a2228592c9a35f36f9573c"},{"sha":"ced81b2bb45783b724fbff285716deb61f836570","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tlibgcc/\n\tBackport from trunk r240033.\n\t2016-09-07  Joseph Myers  <joseph@codesourcery.com>\n\n\tPR libgcc/77519\n\t* libgcc2.c (NOTRUNC): Invert settings.\n\nChange-Id: I1e01681bbf86d99e9106e5c2fb60d2e6990415c0","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/ced81b2bb45783b724fbff285716deb61f836570"},{"sha":"0717538f25c9c7a9858cb5fba9f2011ffe1b8816","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r240102.\n\t2016-09-12  Andrew Pinski  <apinski@cavium.com>\n\n\t* config/aarch64/aarch64-tuning-flags.def (SLOW_UNALIGNED_LDPW):\n\tNew tuning option.\n\t* config/aarch64/aarch64.c (thunderx_tunings): Enable\n\tAARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW.\n\t(aarch64_operands_ok_for_ldpstp): Return false if\n\tAARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW and the mode\n\twas SImode and the alignment is less than 8 byte.\n\t(aarch64_operands_adjust_ok_for_ldpstp): Likewise.\n\n\tgcc/testsuite/\n\tBackport from trunk r240102.\n\t2016-09-12  Andrew Pinski  <apinski@cavium.com>\n\n\t* gcc.target/aarch64/thunderxloadpair.c: New testcase.\n\t* gcc.target/aarch64/thunderxnoloadpair.c: New testcase.\n\nChange-Id: I8cc39d2082b5eb901979ca677965c18b4356383b","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/0717538f25c9c7a9858cb5fba9f2011ffe1b8816"},{"sha":"6058e0bf7138591e48403e0c646a263873953bd1","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r238977.\n\t2016-08-02  Tamar Christina  <tamar.christina@arm.com>\n\n\t* config/aarch64/aarch64-simd-builtins.def\n\t(__builtin_aarch64_fmindf): Change BUILTIN_VDQF to BUILTIN_VDQF_DF.\n\t(__builtin_aarch64_fmaxdf): Likewise.\n\t(__builtin_aarch64_smin_nandf): Likewise.\n\t(__builtin_aarch64_smax_nandf): Likewise.\n\t* config/aarch64/aarch64-simd.md (<fmaxmin><mode>3): Remove.\n\t* config/aarch64/aarch64.md (<fmaxmin><mode>3): Rename to...\n\t(<fmaxmin><mode>3): ...this.\n\t* config/aarch64/arm_neon.h (vmaxnm_f64): New.\n\t(vminnm_f64): Likewise.\n\t(vmin_f64): Likewise.\n\t(vmax_f64): Likewise.\n\t* config/aarch64/iterators.md (FMAXMIN): Merge with...\n\t(FMAXMIN_UNS): ...this.\n\t(fmaxmin): Merged with\n\t(fmaxmin_op): ...this...\n\t(maxmin_uns_op): ...in to this.\n\n\tgcc/testsuite/\n\tBackport from trunk r238977.\n\t2016-08-02  Tamar Christina  <tamar.christina@arm.com>\n\n\t* gcc.target/aarch64/vminmaxnm.c: New.\n\t* gcc.target/aarch64/simd/vminmaxnm_1.c (main): Add float64x1_t\n\ttests.\n\n\tgcc/\n\tBackport from trunk r238989.\n\t2016-02-08  James Greenhalgh  <james.greenhalgh@arm.com>\n\n\t* config/aarch64/arm_neon.h (vminnm_f64): Add back missing 'f' from\n\t__builtin_aarch64_fmindf.\n\nChange-Id: Iedd92bb1d08f8e4ba47b0d01d8a66df8683056f9","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/6058e0bf7138591e48403e0c646a263873953bd1"},{"sha":"8e9fa4abbc687110c6c205e5e1466f15bf6809d9","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r237857.\n\t2016-06-29  Jim Wilson  <jim.wilson@linaro.org>\n\n\t* config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning.\n\t* config/aarch64/aarch64.c (qdf24xx_addrcost_table,\n\tqdf24xx_regmove_cost, qdf24xx_tunings): New.\n\t* config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New.\n\t* config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning.\n\t* config/arm/arm.c (arm_qdf24xx_tune): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r237857.\n\t2016-06-29  Jim Wilson  <jim.wilson@linaro.org>\n\n\t* gcc.dg/asr_div1.c: Add aarch64 specific dg-options.\n\nChange-Id: I6937b1e3ec6049a296ab700994cd79ea1c637979","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/8e9fa4abbc687110c6c205e5e1466f15bf6809d9"},{"sha":"d108caf329fb0c7bda126a554c0506c2c5ba25ad","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r238079.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to\n\tdecide whether to prevent some libgcc routines being included for some\n\tmultilibs rather than __ARM_ARCH_6M__ and add comment to indicate the\n\tlink between this condition and the one in\n\tlibgcc/config/arm/lib1func.S.\n\n\tgcc/testsuite/\n\tBackport from trunk r238079.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* lib/target-supports.exp (check_effective_target_arm_cortex_m): Use\n\t__ARM_ARCH_ISA_ARM to test for Cortex-M devices.\n\n\tlibgcc/\n\tBackport from trunk r238079.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/bpabi-v6m.S: Clarify what architectures is the\n\timplementation suitable for.\n\t* config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases\n\tfor all Thumb-1 only targets.\n\t(NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets.\n\t(THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than\n\t__ARM_ARCH_6M__.\n\t(EQUIV): Likewise.\n\t(ARM_FUNC_ALIAS): Likewise.\n\t(umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv\n\tversion.\n\t(modsi3): Likewise.\n\t(clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__.\n\t(clzdi2): Likewise.\n\t(ctzsi2): Likewise.\n\t(L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than\n\t__ARM_ARCH_6M__ in guard for checking whether it is defined.\n\t(final includes): Test for NOT_ISA_TARGET_32BIT rather than\n\t__ARM_ARCH_6M__ and add comment to indicate the connection between\n\tthis condition and the one in gcc/config/arm/elf.h.\n\t* config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and\n\t__ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.\n\t* config/arm/t-softfp: Likewise.\n\n\tlibgcc/\n\tBackport from trunk r238080.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later\n\tand ARMv5t* rather than for a fixed list of architectures.\n\n\tgcc/\n\tBackport from trunk r238081.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm-arches.def (armv8-m.base): Define new architecture.\n\t(armv8-m.main): Likewise.\n\t(armv8-m.main+dsp): Likewise.\n\t* config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define.\n\t(FL_FOR_ARCH8M_MAIN): Likewise.\n\t* config/arm/arm-tables.opt: Regenerate.\n\t* config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and\n\tarmv8-m.main+dsp to BE8_LINK_SPEC.\n\t* config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M.\n\t(enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN.\n\t* config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M\n\tBaseline and Mainline.\n\t(arm_option_override_internal): Also disable arm_restrict_it when\n\t!arm_arch_notm.  Update comment for -munaligned-access to also cover\n\tARMv8-M Baseline.\n\t(arm_file_start): Increase buffer size for printing architecture name.\n\t* doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main\n\tand armv8-m.main+dsp.\n\t(mno-unaligned-access): Clarify that this is disabled by default for\n\tARMv8-M Baseline architectures as well.\n\n\tgcc/testsuite/\n\tBackport from trunk r238081.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and\n\tcheck_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and\n\tARMv8-M Mainline architectures.\n\n\tlibgcc/\n\tBackport from trunk r238081.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M.\n\n\tgcc/\n\tBackport from trunk r238082.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm-protos.h: Reindent FL_FOR_* macro definitions.\n\n\tgcc/\n\tBackport from trunk r238083.\n\t2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm.h (TARGET_USE_MOVT): Check MOVT/MOVW availability\n\twith TARGET_HAVE_MOVT.\n\t(TARGET_HAVE_MOVT): Define.\n\t* config/arm/arm.c (const_ok_for_op): Check MOVT/MOVW\n\tavailability with TARGET_HAVE_MOVT.\n\t* config/arm/arm.md (arm_movt): Use TARGET_HAVE_MOVT to check MOVT\n\tavailability.\n\t(addsi splitter): Use TARGET_THUMB && TARGET_HAVE_MOVT rather than\n\tTARGET_THUMB2.\n\t(symbol_refs movsi splitter): Remove TARGET_32BIT check.\n\t(arm_movtas_ze): Use TARGET_HAVE_MOVT to check MOVT availability.\n\t* config/arm/constraints.md (define_constraint \"j\"): Use\n\tTARGET_HAVE_MOVT to check MOVT availability.\n\n\tgcc/\n\tBackport from trunk r238288.\n\t2016-07-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm.h (TARGET_HAVE_MOVT): Include ARMv8-M as having MOVT.\n\t* config/arm/arm.c (arm_arch_name): (const_ok_for_op): Check MOVT/MOVW\n\tavailability with TARGET_HAVE_MOVT.\n\t(thumb_legitimate_constant_p): Strip the high part of a label_ref.\n\t(thumb1_rtx_costs): Also return 0 if setting a half word constant and\n\tMOVW is available and replace (unsigned HOST_WIDE_INT) INTVAL by\n\tUINTVAL.\n\t(thumb1_size_rtx_costs): Make set of half word constant also cost 1\n\textra instruction if MOVW is available.  Use a cost variable\n\tincremented by COSTS_N_INSNS (1) when the condition match rather than\n\treturning an arithmetic expression based on COSTS_N_INSNS.  Make\n\tconstant with bottom half word zero cost 2 instruction if MOVW is\n\tavailable.\n\t* config/arm/arm.md (define_attr \"arch\"): Add v8mb.\n\t(define_attr \"arch_enabled\"): Set to yes if arch value is v8mb and\n\ttarget is ARMv8-M Baseline.\n\t(arm_movt): New unpredicable alternative for ARMv8-M Baseline.\n\t(arm_movtas_ze): Likewise.\n\t* config/arm/thumb1.md (thumb1_movdi_insn): Add ARMv8-M Baseline only\n\talternative for constants satisfying j constraint.\n\t(thumb1_movsi_insn): Likewise.\n\t(movsi splitter for K alternative): Tighten condition to not trigger\n\tif movt is available and j constraint is satisfied.\n\t(Pe immediate splitter): Likewise.\n\t(thumb1_movhi_insn): Add ARMv8-M Baseline only alternative for\n\tconstant fitting in an halfword to use MOVW.\n\t* doc/sourcebuild.texi (arm_thumb1_movt_ok): Document new ARM\n\teffective target.\n\n\tgcc/testsuite/\n\tBackport from trunk r238288.\n\t2016-07-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* lib/target-supports.exp (check_effective_target_arm_thumb1_movt_ok):\n\tDefine effective target.\n\t* gcc.target/arm/pr42574.c: Require arm_thumb1_ok and\n\t!arm_thumb1_movt_ok to exclude ARMv8-M Baseline.\n\t* gcc.target/arm/movhi_movw.c: New test.\n\t* gcc.target/arm/movsi_movw.c: Likewise.\n\t* gcc.target/arm/movdi_movw.c: Likewise.\n\n\tgcc/\n\tBackport from trunk r238289.\n\t2016-07-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm.h (TARGET_HAVE_CBZ): Define.\n\t(TARGET_IDIV): Set for all Thumb targets provided they have hardware\n\tdivide feature.\n\t* config/arm/arm.md (divsi3): New unpredicable alternative for ARMv8-M\n\tBaseline.  Make initial alternative TARGET_32BIT only.\n\t(udivsi3): Likewise.\n\t* config/arm/thumb1.md (thumb1_cbz): New define_insn.\n\t* doc/sourcebuild.texi (arm_thumb1_cbz_ok): Document new effective\n\ttarget.\n\n\tgcc/testsuite/\n\tBackport from trunk r238289.\n\t2016-07-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* lib/target-supports.exp (check_effective_target_arm_thumb1_cbz_ok):\n\tAdd new arm_thumb1_cbz_ok effective target.\n\t* gcc.target/arm/cbz.c: New test.\n\n\tgcc/testsuite/\n\tBackport from trunk r238331.\n\t2016-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* gcc.target/arm/pr42574.c: Add missing target keyword for the dg-do\n\tselector and enclose boolean expression in curly braces.\n\n\tgcc/\n\tBackport from trunk r238348.\n\t2016-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.\n\t(TARGET_HAVE_LDACQD): New macro.\n\t* config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather\n\tthan TARGET_HAVE_LDACQ.\n\t(arm_load_acquire_exclusivedi): Likewise.\n\t(arm_store_release_exclusivedi): Likewise.\n\n\tgcc/testsuite/\n\tBackport from trunk r238348.\n\t2016-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ...\n\t* gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.\n\t* gcc.target/arm/atomic-op-acq_rel.c: Rename into ...\n\t* gcc.target/arm/atomic-op-acq_rel-1.c: This.\n\t* gcc.target/arm/atomic-op-acquire.c: Rename into ...\n\t* gcc.target/arm/atomic-op-acquire-1.c: This.\n\t* gcc.target/arm/atomic-op-char.c: Rename into ...\n\t* gcc.target/arm/atomic-op-char-1.c: This.\n\t* gcc.target/arm/atomic-op-consume.c: Rename into ...\n\t* gcc.target/arm/atomic-op-consume-1.c: This.\n\t* gcc.target/arm/atomic-op-int.c: Rename into ...\n\t* gcc.target/arm/atomic-op-int-1.c: This.\n\t* gcc.target/arm/atomic-op-relaxed.c: Rename into ...\n\t* gcc.target/arm/atomic-op-relaxed-1.c: This.\n\t* gcc.target/arm/atomic-op-release.c: Rename into ...\n\t* gcc.target/arm/atomic-op-release-1.c: This.\n\t* gcc.target/arm/atomic-op-seq_cst.c: Rename into ...\n\t* gcc.target/arm/atomic-op-seq_cst-1.c: This.\n\t* gcc.target/arm/atomic-op-short.c: Rename into ...\n\t* gcc.target/arm/atomic-op-short-1.c: This.\n\t* gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.\n\t* gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-acquire-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-char-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-consume-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-int-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-relaxed-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-release-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.\n\t* gcc.target/arm/atomic-op-short-2.c: Likewise.\n\n\tgcc/\n\tBackport from trunk r239888.\n\t2016-08-31  Eric Botcazou  <ebotcazou@adacore.com>\n\n\t* config/arm/arm.c (thumb1_size_rtx_costs) <SET>: Add missing guard.\n\n\tgcc/testsuite/\n\tBackport from trunk r241086.\n\t2016-10-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* gcc.target/arm/movhi_movw.c: Enable test for ARM mode.\n\t* gcc.target/arm/movsi_movw.c: Likewise.\n\t* gcc.target/arm/movdi_movw.c: Likewise and adapt scan-assembler\n\tdirective to work on big endian targets.\n\nChange-Id: I9fea67c44aa10d639644c90a4b436d4f809da9fc","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/d108caf329fb0c7bda126a554c0506c2c5ba25ad"},{"sha":"e9d9ea8ecdeb662622d9b6aae23342e6f21d61cf","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r237002.\n\t2016-06-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* doc/sourcebuild.texi (arm_acq_rel): Document new effective target.\n\n\tgcc/testsuite/\n\tBackport from trunk r237002.\n\t2016-06-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>\n\n\t* lib/target-supports.exp (check_effective_target_arm_acq_rel): New\n\tprocedure.\n\nChange-Id: Iab8b0839cebaaf709e73aa30a42ad77f662e7d20","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/e9d9ea8ecdeb662622d9b6aae23342e6f21d61cf"},{"sha":"d4e950cf583d0a617ab9fcf3b8d069125c7a168e","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r238000.\n\t2016-07-05  Christophe Lyon  <christophe.lyon@linaro.org>\n\n\t* config/arm/neon-testgen.ml: Delete.\n\t* config/arm/neon.ml: Delete.\n\n\tgcc/testsuite/\n\tBackport from trunk r238000.\n\t2016-07-05  Christophe Lyon  <christophe.lyon@linaro.org>\n\n\t* gcc.target/arm/neon/polytypes.c: Move to ...\n\t* gcc.target/arm/polytypes.c: ... here.\n\t* gcc.target/arm/neon/pr51534.c: Move to ...\n\t* gcc.target/arm/pr51534.c: ... here.\n\t* gcc.target/arm/neon/vect-vcvt.c: Move to ...\n\t* gcc.target/arm/vect-vcvt.c: ... here.\n\t* gcc.target/arm/neon/vect-vcvtq.c: Move to ...\n\t* gcc.target/arm/vect-vcvtq.c: ... here.\n\t* gcc.target/arm/neon/vfp-shift-a2t2.c: Move to ...\n\t* gcc.target/arm/vfp-shift-a2t2.c: ... here.\n\t* gcc.target/arm/neon/vst1Q_laneu64-1.c: Move to ...\n\t* gcc.target/arm/vst1Q_laneu64-1.c: ... here. Fix foo() prototype.\n\t* gcc.target/arm/neon/neon.exp: Delete.\n\t* gcc.target/arm/neon/: Delete.\n\n\tgcc/testsuite/\n\tBackport from trunk r238046.\n\t2016-07-06  Wilco Dijkstra  <wdijkstr@arm.com>\n\n\t* gcc.target/arm/vst1Q_laneu64-1.c (foo): Use unsigned char*.\n\nChange-Id: I000858c7a70325f7b6f5b00055b34d76955b8594","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/d4e950cf583d0a617ab9fcf3b8d069125c7a168e"},{"sha":"266614143ba16d6b228ab1e8359963ce86c41416","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r240256.\n\t2016-09-20  Tamar Christina  <tamar.christina@arm.com>\n\n\t* config/aarch64/arm_neon.h: Add gnu_inline and artificial\n\tattributes to all inlined functions and make them extern.\n\n\tgcc/\n\tBackport from trunk r240271.\n\t2016-09-20  Tamar Christina  <tamar.christina@arm.com>\n\n\t* config/aarch64/arm_neon.h\n\t(vst2_s64, vst2_u64, vst2_f64, vst2_s8): Add missing attributes.\n\t(vst3_s64, vst3_u64, vst3_f64, vst3_s8): Likewise.\n\t(vst4_s64, vst4_u64, vst4_f64, vst4_s8): Likewise.\n\nChange-Id: Iacc298c3d1cf6a713a2ed96e8331b0794b03708a","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/266614143ba16d6b228ab1e8359963ce86c41416"},{"sha":"faa305b774c43035fa1f34aadd6dfb803105dfa2","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r240791.\n\t2016-10-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>\n\n\t* fold-const.c (native_encode_real): Fix logic for selecting offset\n\tto write to when BYTES_BIG_ENDIAN.\n\nChange-Id: I0ce72bead9880c0064f34a629499271b9337cdf8","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/faa305b774c43035fa1f34aadd6dfb803105dfa2"},{"sha":"fe89a30c89f79a4ddbb0c22c4ceaf6a1b2e34197","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"\tgcc/\n\tBackport from trunk r240398.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm-arches.def (\"armv8.1-a\"): Add FL_CRC32.\n\t(\"armv8.2-a\"): New.\n\t(\"armv8.2-a+fp16\"): New.\n\t* config/arm/arm-protos.h (FL2_ARCH8_2): New.\n\t(FL2_FP16INST): New.\n\t(FL2_FOR_ARCH8_2A): New.\n\t* config/arm/arm-tables.opt: Regenerate.\n\t* config/arm/arm.c (arm_arch8_2): New.\n\t(arm_fp16_inst): New.\n\t(arm_option_override): Set arm_arch8_2 and arm_fp16_inst.  Check\n\tfor incompatible fp16-format settings.\n\t* config/arm/arm.h (TARGET_VFP_FP16INST): New.\n\t(TARGET_NEON_FP16INST): New.\n\t(arm_arch8_2): Declare.\n\t(arm_fp16_inst): Declare.\n\t* config/arm/bpabi.h (BE8_LINK_SPEC): Add entries for\n\tmarch=armv8.2-a and march=armv8.2-a+fp16.\n\t* config/arm/t-aprofile (Arch Matches): Add entries for armv8.2-a\n\tand armv8.2-a+fp16.\n\t* doc/invoke.texi (ARM Options): Add \"-march=armv8.1-a\",\n\t\"-march=armv8.2-a\" and \"-march=armv8.2-a+fp16\".\n\n\tgcc/\n\tBackport from trunk r240400.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* doc/sourcebuild.texi (ARM-specific attributes): Add entries for\n\tarm_fp16_alternative_ok and arm_fp16_none_ok.\n\n\tgcc/testsuite/\n\tBackport from trunk r240400.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* g++.dg/ext/arm-fp16/arm-fp16-ops-3.C: Use\n\tarm_fp16_alternative_ok.\n\t* g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise.\n\t* gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise.\n\t* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c: Likewise.\n\t* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-1.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-10.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-11.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-12.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-2.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-3.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-4.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-5.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-6.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-7.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-8.c: Likewise.\n\t* gcc.target/arm/fp16-compile-alt-9.c: Likewise.\n\t* gcc.target/arm/fp16-compile-none-1.c: Use arm_fp16_none_ok.\n\t* gcc.target/arm/fp16-compile-none-2.c: Likewise.\n\t* gcc.target/arm/fp16-rounding-alt-1.c: Use\n\tarm_fp16_alternative_ok.\n\t* lib/target-supports.exp\n\t(check_effective_target_arm_fp16_alternative_ok_nocache): New.\n\t(check_effective_target_arm_fp16_alternative_ok): New.\n\t(check_effective_target_arm_fp16_none_ok_nocache): New.\n\t(check_effective_target_arm_fp16_none_ok): New.\n\n\tgcc/\n\tBackport from trunk r240401.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* doc/sourcebuild.texi (ARM-specific attributes): Add anchor for\n\tarm_v8_1a_neon_ok.  Add entries for arm_v8_2a_fp16_scalar_ok,\n\tarm_v8_2a_fp16_scalar_hw, arm_v8_2a_fp16_neon_ok and\n\tarm_v8_2a_fp16_neon_hw.\n\t(Add options): Add entries for arm_v8_1a_neon, arm_v8_2a_scalar,\n\tarm_v8_2a_neon.\n\n\tgcc/testsuite/\n\tBackport from trunk r240401.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* lib/target-supports.exp (add_options_for_arm_v8_2a_fp16_scalar):\n\tNew.\n\t(add_options_for_arm_v8_2a_fp16_neon): New.\n\t(check_effective_target_arm_arch_v8_2a_ok): Auto-generate.\n\t(add_options_for_arm_arch_v8_2a): Auto-generate.\n\t(check_effective_target_arm_arch_v8_2a_multilib): Auto-generate.\n\t(check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache): New.\n\t(check_effective_target_arm_v8_2a_fp16_scalar_ok): New.\n\t(check_effective_target_arm_v8_2a_fp16_neon_ok_nocache): New.\n\t(check_effective_target_arm_v8_2a_fp16_neon_ok): New.\n\t(check_effective_target_arm_v8_2a_fp16_scalar_hw): New.\n\t(check_effective_target_arm_v8_2a_fp16_neon_hw): New.\n\n\tgcc/\n\tBackport from trunk r240402.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm-c.c (arm_cpu_builtins): Define\n\t\"__ARM_FEATURE_FP16_SCALAR_ARITHMETIC\" and\n\t\"__ARM_FEATURE_FP16_VECTOR_ARITHMETIC\".\n\n\tgcc/testsuite/\n\tBackport from trunk r240402.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/attr-fp16-arith-1.c: New.\n\n\tgcc/\n\tBackport from trunk r240403.\n\t2016-09-23  Jiong Wang  <jiong.wang@arm.com>\n\t    Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm.c (output_move_vfp): Weaken assert to allow\n\tHImode.\n\t(arm_hard_regno_mode_ok): Allow HImode values in VFP registers.\n\t* config/arm/arm.md (*movhi_bytes): Disable when VFP registers are\n\tavailable.  Also fix some white-space.\n\t* config/arm/vfp.md (*arm_movhi_vfp): New.\n\t(*thumb2_movhi_vfp): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240403.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/short-vfp-1.c: New.\n\n\tgcc/\n\tBackport from trunk r240404.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm.c (arm_evpc_neon_vuzp): Add support for V8HF and\n\tV4HF modes.\n\t(arm_evpc_neon_vtrn): Likewise.\n\t(arm_evpc_neon_vrev): Likewise.\n\t(arm_evpc_neon_vext): Likewise.\n\t* config/arm/arm_neon.h (vbsl_f16): New.\n\t(vbslq_f16): New.\n\t(vdup_n_f16): New.\n\t(vdupq_n_f16): New.\n\t(vdup_lane_f16): New.\n\t(vdupq_lane_f16): New.\n\t(vext_f16): New.\n\t(vextq_f16): New.\n\t(vmov_n_f16): New.\n\t(vmovq_n_f16): New.\n\t(vrev64_f16): New.\n\t(vrev64q_f16): New.\n\t(vtrn_f16): New.\n\t(vtrnq_f16): New.\n\t(vuzp_f16): New.\n\t(vuzpq_f16): New.\n\t(vzip_f16): New.\n\t(vzipq_f16): New.\n\t* config/arm/arm_neon_buillins.def (vdup_n): New (v8hf, v4hf variants).\n\t(vdup_lane): New (v8hf, v4hf variants).\n\t(vext): New (v8hf, v4hf variants).\n\t(vbsl): New (v8hf, v4hf variants).\n\t* config/arm/iterators.md (VDQWH): New.\n\t(VH): New.\n\t(V_double_vector_mode): Add V8HF and V4HF.  Fix white-space.\n\t(Scalar_mul_8_16): Fix white-space.\n\t(Is_d_reg): Add V4HF and V8HF.\n\t* config/arm/neon.md (neon_vdup_lane<mode>_internal): New.\n\t(neon_vdup_lane<mode>): New.\n\t(neon_vtrn<mode>_internal): Replace VDQW with VDQWH.\n\t(*neon_vtrn<mode>_insn): Likewise.\n\t(neon_vzip<mode>_internal): Likewise. Also fix white-space.\n\t(*neon_vzip<mode>_insn): Likewise\n\t(neon_vuzp<mode>_internal): Likewise.\n\t(*neon_vuzp<mode>_insn): Likewise\n\t* config/arm/vec-common.md (vec_perm_const<mode>): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240404.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h\n\t(FP16_SUPPORTED): New\n\t(expected-hfloat-16x4): Make conditional on __fp16 support.\n\t(expected-hfloat-16x8): Likewise.\n\t(vdup_n_f16): Disable for non-AArch64 targets.\n\t* gcc.target/aarch64/advsimd-intrinsics/vbsl.c: Add __fp16 tests,\n\tconditional on FP16_SUPPORTED.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vext.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Add support\n\tfor testing __fp16.\n\t* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: Add __fp16 tests,\n\tconditional on FP16_SUPPORTED.\n\t* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise.\n\n\tgcc/\n\tBackport from trunk r240407.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\t    Jiong Wang <jiong.wang@arm.com>\n\n\t* config/arm/arm.c (coproc_secondary_reload_class): Make HFmode\n\tavailable when FP16 instructions are available.\n\t(output_move_vfp): Add support for 16-bit data moves.\n\t(arm_validize_comparison): Fix some white-space.  Support HFmode\n\tby conversion to SFmode.\n\t* config/arm/arm.md (truncdfhf2): Fix a comment.\n\t(extendhfdf2): Likewise.\n\t(cstorehf4): New.\n\t(movsicc): Fix some white-space.\n\t(movhfcc): New.\n\t(movsfcc): Fix some white-space.\n\t(*cmovhf): New.\n\t* config/arm/vfp.md (*arm_movhi_vfp): Disable when VFP FP16\n\tinstructions are available.\n\t(*thumb2_movhi_vfp): Likewise.\n\t(*arm_movhi_fp16): New.\n\t(*thumb2_movhi_fp16): New.\n\t(*movhf_vfp_fp16): New.\n\t(*movhf_vfp_neon): Disable when VFP FP16 instructions are\n\tavailable.\n\t(*movhf_vfp): Likewise.\n\t(extendhfsf2): Enable when VFP FP16 instructions are available.\n\t(truncsfhf2):  Enable when VFP FP16 instructions are available.\n\n\tgcc/testsuite/\n\tBackport from trunk r240407.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/armv8_2_fp16-move-1.c: New.\n\t* gcc.target/arm/fp16-aapcs-1.c: Update expected output.\n\n\tgcc/\n\tBackport from trunk r240411.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/iterators.md (Code iterators): Fix some white-space\n\tin the comments.\n\t(GLTE): New.\n\t(ABSNEG): New\n\t(FCVT): Moved from vfp.md.\n\t(VCVT_HF_US_N): New.\n\t(VCVT_SI_US_N): New.\n\t(VCVT_HF_US): New.\n\t(VCVTH_US): New.\n\t(FP16_RND): New.\n\t(absneg_str): New.\n\t(FCVTI32typename): Moved from vfp.md.\n\t(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,\n\tUNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,\n\tUNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,\n\tUNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N,  UNSPEC_VCVTH_S_N,\n\tUNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.\n\t(vcvth_op): New.\n\t(fp16_rnd_str): New.\n\t(fp16_rnd_insn): New.\n\t* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.\n\t(UNSPEC_VCVT_HF_U_N): New.\n\t(UNSPEC_VCVT_SI_S_N): New.\n\t(UNSPEC_VCVT_SI_U_N): New.\n\t(UNSPEC_VCVTH_S): New.\n\t(UNSPEC_VCVTH_U): New.\n\t(UNSPEC_VCVTA_S): New.\n\t(UNSPEC_VCVTA_U): New.\n\t(UNSPEC_VCVTM_S): New.\n\t(UNSPEC_VCVTM_U): New.\n\t(UNSPEC_VCVTN_S): New.\n\t(UNSPEC_VCVTN_U): New.\n\t(UNSPEC_VCVTP_S): New.\n\t(UNSPEC_VCVTP_U): New.\n\t(UNSPEC_VCVTP_S): New.\n\t(UNSPEC_VCVTP_U): New.\n\t(UNSPEC_VRND): New.\n\t(UNSPEC_VRNDA): New.\n\t(UNSPEC_VRNDI): New.\n\t(UNSPEC_VRNDM): New.\n\t(UNSPEC_VRNDN): New.\n\t(UNSPEC_VRNDP): New.\n\t(UNSPEC_VRNDX): New.\n\t* config/arm/vfp.md (<absneg_str>hf2): New.\n\t(neon_vabshf): New.\n\t(neon_v<fp16_rnd_str>hf): New.\n\t(neon_vrndihf): New.\n\t(addhf3): New.\n\t(subhf3): New.\n\t(divhf3): New.\n\t(mulhf3): New.\n\t(*mulsf3neghf_vfp): New.\n\t(*negmulhf3_vfp): New.\n\t(*mulsf3addhf_vfp): New.\n\t(*mulhf3subhf_vfp): New.\n\t(*mulhf3neghfaddhf_vfp): New.\n\t(*mulhf3neghfsubhf_vfp): New.\n\t(fmahf4): New.\n\t(neon_vfmahf): New.\n\t(fmsubhf4_fp16): New.\n\t(neon_vfmshf): New.\n\t(*fnmsubhf4): New.\n\t(*fnmaddhf4): New.\n\t(neon_vsqrthf): New.\n\t(neon_vrsqrtshf): New.\n\t(FCVT): Move to iterators.md.\n\t(FCVTI32typename): Likewise.\n\t(neon_vcvth<sup>hf): New.\n\t(neon_vcvth<sup>si): New.\n\t(neon_vcvth<sup>_nhf_unspec): New.\n\t(neon_vcvth<sup>_nhf): New.\n\t(neon_vcvth<sup>_nsi_unspec): New.\n\t(neon_vcvth<sup>_nsi): New.\n\t(neon_vcvt<vcvth_op>h<sup>si): New.\n\t(neon_<fmaxmin_op>hf): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240411.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/armv8_2-fp16-arith-1.c: New.\n\t* gcc.target/arm/armv8_2-fp16-conv-1.c: New.\n\n\tgcc/\n\tBackport from trunk r240415.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/iterators.md (VCVTHI): New.\n\t(NEON_VCMP): Add UNSPEC_VCLT and UNSPEC_VCLE.  Fix a long line.\n\t(NEON_VAGLTE): New.\n\t(VFM_LANE_AS): New.\n\t(VH_CVTTO): New.\n\t(V_reg): Add HF, V4HF and V8HF.  Fix white-space.\n\t(V_HALF): Add V4HF.  Fix white-space.\n\t(V_if_elem): Add HF, V4HF and V8HF.  Fix white-space.\n\t(V_s_elem): Likewise.\n\t(V_sz_elem): Fix white-space.\n\t(V_elem_ch): Likewise.\n\t(VH_elem_ch): New.\n\t(scalar_mul_constraint): Add V8HF and V4HF.\n\t(Is_float_mode): Fix white-space.\n\t(Is_d_reg): Add V4HF and V8HF.  Fix white-space.\n\t(q): Add HF.  Fix white-space.\n\t(float_sup): New.\n\t(float_SUP): New.\n\t(cmp_op_unsp): Add UNSPEC_VCALE and UNSPEC_VCALT.\n\t(neon_vfm_lane_as): New.\n\t* config/arm/neon.md (add<mode>3_fp16): New.\n\t(sub<mode>3_fp16): New.\n\t(mul<mode>3add<mode>_neon): New.\n\t(fma<VH:mode>4_intrinsic): New.\n\t(fmsub<VCVTF:mode>4_intrinsic): Fix white-space.\n\t(fmsub<VH:mode>4_intrinsic): New.\n\t(<absneg_str><mode>2): New.\n\t(neon_v<absneg_str><mode>): New.\n\t(neon_v<fp16_rnd_str><mode>): New.\n\t(neon_vrsqrte<mode>): New.\n\t(neon_vpaddv4hf): New.\n\t(neon_vadd<mode>): New.\n\t(neon_vsub<mode>): New.\n\t(neon_vmulf<mode>): New.\n\t(neon_vfma<VH:mode>): New.\n\t(neon_vfms<VH:mode>): New.\n\t(neon_vc<cmp_op><mode>): New.\n\t(neon_vc<cmp_op><mode>_fp16insn): New\n\t(neon_vc<cmp_op_unsp><mode>_fp16insn_unspec): New.\n\t(neon_vca<cmp_op><mode>): New.\n\t(neon_vca<cmp_op><mode>_fp16insn): New.\n\t(neon_vca<cmp_op_unsp><mode>_fp16insn_unspec): New.\n\t(neon_vc<cmp_op>z<mode>): New.\n\t(neon_vabd<mode>): New.\n\t(neon_v<maxmin>f<mode>): New.\n\t(neon_vp<maxmin>fv4hf: New.\n\t(neon_<fmaxmin_op><mode>): New.\n\t(neon_vrecps<mode>): New.\n\t(neon_vrsqrts<mode>): New.\n\t(neon_vrecpe<mode>): New (VH variant).\n\t(neon_vdup_lane<mode>_internal): New.\n\t(neon_vdup_lane<mode>): New.\n\t(neon_vcvt<sup><mode>): New (VCVTHI variant).\n\t(neon_vcvt<sup><mode>): New (VH variant).\n\t(neon_vcvt<sup>_n<mode>): New (VH variant).\n\t(neon_vcvt<sup>_n<mode>): New (VCVTHI variant).\n\t(neon_vcvt<vcvth_op><sup><mode>): New.\n\t(neon_vmul_lane<mode>): New.\n\t(neon_vmul_n<mode>): New.\n\t* config/arm/unspecs.md (UNSPEC_VCALE): New\n\t(UNSPEC_VCALT): New.\n\t(UNSPEC_VFMA_LANE): New.\n\t(UNSPECS_VFMS_LANE): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240415.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/armv8_2-fp16-arith-1.c: Use arm_v8_2a_fp16_neon\n\toptions.  Add tests for float16x4_t and float16x8_t.\n\n\tgcc/\n\tBackport from trunk r240416.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm-builtins.c (arm_init_neon_builtin): New.\n\t(arm_init_builtins): Move body of a loop to the standalone\n\tfunction arm_init_neon_builtin.\n\t(arm_expand_neon_builtin_1): New.  Update comment.  Function body\n\tmoved from arm_neon_builtin with some white-space fixes.\n\t(arm_expand_neon_builtin): Move code into the standalone function\n\tarm_expand_neon_builtin_1.\n\n\tgcc/\n\tBackport from trunk r240421.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm-builtins.c (hf_UP): New.\n\t(si_UP): New.\n\t(vfp_builtin_data): New.  Update comment.\n\t(enum arm_builtins): Include \"arm_vfp_builtins.def\".\n\t(ARM_BUILTIN_VFP_PATTERN_START): New.\n\t(arm_init_vfp_builtins): New.\n\t(arm_init_builtins): Add arm_init_vfp_builtins.\n\t(arm_expand_vfp_builtin): New.\n\t(arm_expand_builtins): Update for arm_expand_vfp_builtin.  Fix\n\tlong line.\n\t* config/arm/arm_vfp_builtins.def: New file.\n\t* config/arm/t-arm (arm.o): Add arm_vfp_builtins.def.\n\t(arm-builtins.o): Likewise.\n\n\tgcc/\n\tBackport from trunk r240422.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm_neon_builtins.def (vadd): New (v8hf, v4hf\n\tvariants).\n\t(vmulf): New (v8hf, v4hf variants).\n\t(vfma): New (v8hf, v4hf variants).\n\t(vfms): New (v8hf, v4hf variants).\n\t(vsub): New (v8hf, v4hf variants).\n\t(vcage): New (v8hf, v4hf variants).\n\t(vcagt): New (v8hf, v4hf variants).\n\t(vcale): New (v8hf, v4hf variants).\n\t(vcalt): New (v8hf, v4hf variants).\n\t(vceq): New (v8hf, v4hf variants).\n\t(vcgt): New (v8hf, v4hf variants).\n\t(vcge): New (v8hf, v4hf variants).\n\t(vcle): New (v8hf, v4hf variants).\n\t(vclt): New (v8hf, v4hf variants).\n\t(vceqz): New (v8hf, v4hf variants).\n\t(vcgez): New (v8hf, v4hf variants).\n\t(vcgtz): New (v8hf, v4hf variants).\n\t(vcltz): New (v8hf, v4hf variants).\n\t(vclez): New (v8hf, v4hf variants).\n\t(vabd): New (v8hf, v4hf variants).\n\t(vmaxf): New (v8hf, v4hf variants).\n\t(vmaxnm): New (v8hf, v4hf variants).\n\t(vminf): New (v8hf, v4hf variants).\n\t(vminnm): New (v8hf, v4hf variants).\n\t(vpmaxf): New (v4hf variant).\n\t(vpminf): New (v4hf variant).\n\t(vpadd): New (v4hf variant).\n\t(vrecps): New (v8hf, v4hf variants).\n\t(vrsqrts): New (v8hf, v4hf variants).\n\t(vabs): New (v8hf, v4hf variants).\n\t(vneg): New (v8hf, v4hf variants).\n\t(vrecpe): New (v8hf, v4hf variants).\n\t(vrnd): New (v8hf, v4hf variants).\n\t(vrnda): New (v8hf, v4hf variants).\n\t(vrndm): New (v8hf, v4hf variants).\n\t(vrndn): New (v8hf, v4hf variants).\n\t(vrndp): New (v8hf, v4hf variants).\n\t(vrndx): New (v8hf, v4hf variants).\n\t(vrsqrte): New (v8hf, v4hf variants).\n\t(vmul_lane): Add v4hf and v8hf variants.\n\t(vmul_n): Add v4hf and v8hf variants.\n\t(vext): New (v8hf, v4hf variants).\n\t(vcvts): New (v8hi, v4hi variants).\n\t(vcvts): New (v8hf, v4hf variants).\n\t(vcvtu): New (v8hi, v4hi variants).\n\t(vcvtu): New (v8hf, v4hf variants).\n\t(vcvts_n): New (v8hf, v4hf variants).\n\t(vcvtu_n): New (v8hi, v4hi variants).\n\t(vcvts_n): New (v8hi, v4hi variants).\n\t(vcvtu_n): New (v8hf, v4hf variants).\n\t(vbsl): New (v8hf, v4hf variants).\n\t(vcvtas): New (v8hf, v4hf variants).\n\t(vcvtau): New (v8hf, v4hf variants).\n\t(vcvtms): New (v8hf, v4hf variants).\n\t(vcvtmu): New (v8hf, v4hf variants).\n\t(vcvtns): New (v8hf, v4hf variants).\n\t(vcvtnu): New (v8hf, v4hf variants).\n\t(vcvtps): New (v8hf, v4hf variants).\n\t(vcvtpu): New (v8hf, v4hf variants).\n\n\tgcc/\n\tBackport from trunk r240423.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config.gcc (extra_headers): Add arm_fp16.h\n\t* config/arm/arm_fp16.h: New.\n\t* config/arm/arm_neon.h: Include \"arm_fp16.h\".\n\n\tgcc/\n\tBackport from trunk r240424.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm_neon.h (vabd_f16): New.\n\t(vabdq_f16): New.\n\t(vabs_f16): New.\n\t(vabsq_f16): New.\n\t(vadd_f16): New.\n\t(vaddq_f16): New.\n\t(vcage_f16): New.\n\t(vcageq_f16): New.\n\t(vcagt_f16): New.\n\t(vcagtq_f16): New.\n\t(vcale_f16): New.\n\t(vcaleq_f16): New.\n\t(vcalt_f16): New.\n\t(vcaltq_f16): New.\n\t(vceq_f16): New.\n\t(vceqq_f16): New.\n\t(vceqz_f16): New.\n\t(vceqzq_f16): New.\n\t(vcge_f16): New.\n\t(vcgeq_f16): New.\n\t(vcgez_f16): New.\n\t(vcgezq_f16): New.\n\t(vcgt_f16): New.\n\t(vcgtq_f16): New.\n\t(vcgtz_f16): New.\n\t(vcgtzq_f16): New.\n\t(vcle_f16): New.\n\t(vcleq_f16): New.\n\t(vclez_f16): New.\n\t(vclezq_f16): New.\n\t(vclt_f16): New.\n\t(vcltq_f16): New.\n\t(vcltz_f16): New.\n\t(vcltzq_f16): New.\n\t(vcvt_f16_s16): New.\n\t(vcvt_f16_u16): New.\n\t(vcvt_s16_f16): New.\n\t(vcvt_u16_f16): New.\n\t(vcvtq_f16_s16): New.\n\t(vcvtq_f16_u16): New.\n\t(vcvtq_s16_f16): New.\n\t(vcvtq_u16_f16): New.\n\t(vcvta_s16_f16): New.\n\t(vcvta_u16_f16): New.\n\t(vcvtaq_s16_f16): New.\n\t(vcvtaq_u16_f16): New.\n\t(vcvtm_s16_f16): New.\n\t(vcvtm_u16_f16): New.\n\t(vcvtmq_s16_f16): New.\n\t(vcvtmq_u16_f16): New.\n\t(vcvtn_s16_f16): New.\n\t(vcvtn_u16_f16): New.\n\t(vcvtnq_s16_f16): New.\n\t(vcvtnq_u16_f16): New.\n\t(vcvtp_s16_f16): New.\n\t(vcvtp_u16_f16): New.\n\t(vcvtpq_s16_f16): New.\n\t(vcvtpq_u16_f16): New.\n\t(vcvt_n_f16_s16): New.\n\t(vcvt_n_f16_u16): New.\n\t(vcvtq_n_f16_s16): New.\n\t(vcvtq_n_f16_u16): New.\n\t(vcvt_n_s16_f16): New.\n\t(vcvt_n_u16_f16): New.\n\t(vcvtq_n_s16_f16): New.\n\t(vcvtq_n_u16_f16): New.\n\t(vfma_f16): New.\n\t(vfmaq_f16): New.\n\t(vfms_f16): New.\n\t(vfmsq_f16): New.\n\t(vmax_f16): New.\n\t(vmaxq_f16): New.\n\t(vmaxnm_f16): New.\n\t(vmaxnmq_f16): New.\n\t(vmin_f16): New.\n\t(vminq_f16): New.\n\t(vminnm_f16): New.\n\t(vminnmq_f16): New.\n\t(vmul_f16): New.\n\t(vmul_lane_f16): New.\n\t(vmul_n_f16): New.\n\t(vmulq_f16): New.\n\t(vmulq_lane_f16): New.\n\t(vmulq_n_f16): New.\n\t(vneg_f16): New.\n\t(vnegq_f16): New.\n\t(vpadd_f16): New.\n\t(vpmax_f16): New.\n\t(vpmin_f16): New.\n\t(vrecpe_f16): New.\n\t(vrecpeq_f16): New.\n\t(vrnd_f16): New.\n\t(vrndq_f16): New.\n\t(vrnda_f16): New.\n\t(vrndaq_f16): New.\n\t(vrndm_f16): New.\n\t(vrndmq_f16): New.\n\t(vrndn_f16): New.\n\t(vrndnq_f16): New.\n\t(vrndp_f16): New.\n\t(vrndpq_f16): New.\n\t(vrndx_f16): New.\n\t(vrndxq_f16): New.\n\t(vrsqrte_f16): New.\n\t(vrsqrteq_f16): New.\n\t(vrecps_f16): New.\n\t(vrecpsq_f16): New.\n\t(vrsqrts_f16): New.\n\t(vrsqrtsq_f16): New.\n\t(vsub_f16): New.\n\t(vsubq_f16): New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240425.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/arm/armv8_2-fp16-neon-1.c: New.\n\t* gcc.target/arm/armv8_2-fp16-scalar-1.c: New.\n\t* gcc.target/arm/armv8_2-fp16-scalar-2.c: New.\n\t* gcc.target/arm/attr-fp16-arith-1.c: Add a test of intrinsics\n\tsupport.\n\n\tgcc/testsuite/\n\tBackport from trunk r240426.\n\t2016-09-23  Jiong Wang  <jiong.wang@arm.com>\n\t    Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240427.\n\t2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* gcc.target/advsimd-intrinsics/advsimd-intrinsics.exp: Enable\n\t-march=armv8.2-a+fp16 when supported by the hardware.\n\t* gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc:\n\tAdd F16 tests, enabled if macro HAS_FLOAT16_VARIANT is defined.  Add\n\tsemi-colons to a macro invocations.\n\t* gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabd.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcge.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcgt.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcle.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vclez_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vclt.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcvt.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.  Also fix some white-space.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfma.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.  Also fix some long lines and white-space.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfms.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.  Also fix some long lines and white-space.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmax.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmin.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c: New.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul.c: Add F16\n\ttests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is\n\tdefined.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vneg.c:\n\tLikewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpadd.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmax.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmin.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecps.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnd.c:\n\tLikewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:\n\tLikewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:\n\tLikewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.\n\t* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vsub.c:\n\tLikewise.\n\n\tgcc/\n\tBackport from trunk r240541.\n\t2016-09-27  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm.md (*arm_movsi_insn): Add \"arch\" attribute.\n\t* config/arm/vfp.md (*arm_movhi_vfp): Likewise.\n\t(*thumb2_movhi_vfp): Likewise.\n\t(*arm_movhi_fp16): Remove predication operand from VMOV.F16\n\ttemplate.  Expand predicable attribute to mark VMOV.F16 as not\n\tpredicable.  Add \"arch\" attribute.\n\t(*thumb2_movhi_fp16): Likewise.\n\t(*arm_movsi_vfp): Break a long line.  Add \"arch\" attribute.\n\t(*thumb2_movsi_vfp): Add \"arch\" attribute.\n\n\tmissing/\n\tBackport from trunk r240542.\n\tgcc/testsuite/\n\tBackport from trunk r240551.\n\t2016-09-27  Jiong Wang  <jiong.wang@arm.com>\n\n\t* lib/target-supports.exp\n\t(check_effective_target_arm_v8_2a_fp16_scalar_hw): Delete redundant word\n\tin function comment.\n\n\tgcc/\n\tBackport from trunk r240622.\n\t2016-09-29  Matthew Wahab  <matthew.wahab@arm.com>\n\n\t* config/arm/arm.md (*arm_movsi_insn): Replace \"t2\" arch attribute\n\twith \"v6t2\".  Move \"arch\" attribute above \"pool_range\".\n\t* config/arm/vfp.md (*arm_movhi_vfp): Replace \"t2\" arch attribute\n\twith \"v6t2\".\n\t(*thumb2_movhi_vfp): Likewise.\n\t(*arm_movhi_fp16): Likewise.\n\t(*thumb2_movhi_fp16): Likewise.\n\t(*arm_movsi_vfp): Remove \"arch\" attribute.\n\t(*thumb2_movsi_vfp): Likewise.\n\n\tgcc/testsuite/\n\tBackport from trunk r240921.\n\t2016-10-10  Matthew Wahab  <matthew.wahab@arm.com>\n\t    Jiong Wang  <jiong.wang@arm.com>\n\n\t* target-supports.exp (add_options_for_arm_v8_2a_fp16_scalar): Mention\n\tAArch64 support.\n\t(add_options_for_arm_v8_2a_fp16_neon): Likewise.\n\t(check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache): Support\n\tAArch64 targets.\n\t(check_effective_target_arm_v8_2a_fp16_neon_ok_nocache): Support\n\tAArch64 targets.\n\t(check_effective_target_arm_v8_2a_fp16_scalar_hw): Support AArch64\n\ttargets.\n\t(check_effective_target_arm_v8_2a_fp16_neon_hw): Likewise.\n\n\t2016-10-10  Eric Botgazou  <ebotcazou@adacore.com>\n\tgcc/testsuite/\n\tBackport from trunk r240922.\n\t2016-10-10  Jiong Wang  <jiong.wang@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (FP16_SUPPORTED):\n\tEnable AArch64.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Add support for\n\tvdup*_laneq.\n\t* gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240923.\n\t2016-10-10  Jiong Wang  <jiong.wang@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c: New.\n\n\tgcc/testsuite/\n\tBackport from trunk r240924.\n\t2016-10-10  Jiong Wang  <jiong.wang@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: Support FMT64.\n\t* gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c: New.\n\nChange-Id: I4f2c1a2c934a8c101457de5a1ce7134baebe2fb0","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/fe89a30c89f79a4ddbb0c22c4ceaf6a1b2e34197"},{"sha":"493a6a7da66b065821b3a22446968b272b5c45bc","author":{"name":"Yvan Roux","email":"44d02196dbc7995c7b1458626c56a34c51ee0cbb@linaro.org"},"message":"Merge branches/gcc-6-branch rev 241214.\n\nChange-Id: I2fc7e5fc01a9015199e9be293b8a7b503fd5a829","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/493a6a7da66b065821b3a22446968b272b5c45bc"}]}
{"actor":{"display_login":"kraj"}}