{"action":"created","issue":{"url":"https://api.github.com/repos/tgingold/ghdl/issues/111","repository_url":"https://api.github.com/repos/tgingold/ghdl","labels_url":"https://api.github.com/repos/tgingold/ghdl/issues/111/labels{/name}","comments_url":"https://api.github.com/repos/tgingold/ghdl/issues/111/comments","events_url":"https://api.github.com/repos/tgingold/ghdl/issues/111/events","html_url":"https://github.com/tgingold/ghdl/issues/111","id":163503865,"number":111,"title":"GHDL: a complete VHDL parser","user":{"login":"1138-4EB","id":6628437,"avatar_url":"https://avatars.githubusercontent.com/u/6628437?v=3","gravatar_id":"","url":"https://api.github.com/users/1138-4EB","html_url":"https://github.com/1138-4EB","followers_url":"https://api.github.com/users/1138-4EB/followers","following_url":"https://api.github.com/users/1138-4EB/following{/other_user}","gists_url":"https://api.github.com/users/1138-4EB/gists{/gist_id}","starred_url":"https://api.github.com/users/1138-4EB/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/1138-4EB/subscriptions","organizations_url":"https://api.github.com/users/1138-4EB/orgs","repos_url":"https://api.github.com/users/1138-4EB/repos","events_url":"https://api.github.com/users/1138-4EB/events{/privacy}","received_events_url":"https://api.github.com/users/1138-4EB/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2016-07-02T05:52:29Z","updated_at":"2016-07-02T08:08:34Z","closed_at":null,"body":"I've been thinking long about having some multiplatform (windows and gnu/linux), free (libre), lightweight and standalone tool to analize large bodies of VHDL 2008 code at block/RTL level. That tool would provide a hierarchy browser of the compiled/synthetized design, so that all the parameterized types and components are resolved. Ideally, the info in the hierarchy would be enough to build a command line tool to draw diagrams with different levels of abstraction (entities, processes and concurrent black boxes) for documentation purposes. As a dream, a GUI could be built with linked references between diagrams and sources.\r\n\r\nAmong those features, hierarchy browsers are already available in all the big (and heavy) EDA tools and simulators; diagrams and linked references are also supported by most of the big editors. However, most of those tools require several GB to be installed, since they provide lower levels of abstraction and many other utilities. On top of that, the heavy GUIs must be launched even to just analize the hierarchy.\r\n\r\nThe closest alternative I am aware of is [RTLVision](http://www.concept.de/nlview.html#FAMILY). It [seems](http://www.concept.de/flash/RTL_basic.swf) to be very complete technically, it is supported in multiple platforms (windows/linux/solaris), and accepts VHDL, Verilog and System Verilog. Moreover, the [engine](http://www.concept.de/nlview.html#FAMILY) can be used in many GUI environments. Indeed, I believe it is used by some of the big players in the industry. It is not specified which the supported versions of the standard are, but I believe it should be quite complete for 2008, since they [use](http://www.concept.de/nlview.html#FAMILY) [Verific](http://www.verific.com/)'s parser. However, I don't know how fast it is, given that it accepts multiple languages, and that it includes a waveform viewer to allow signal tracing. In any case, it is neither libre nor free or open source.\r\n\r\nThere are some projects from academia, such as [VHDLVisualizer](http://www2.fiit.stuba.sk/~macko/VHDLVisualizer/) and [HDLVisualizer](http://labss2.fiit.stuba.sk/TeamProject/2011/team05pkss/docs/); and even web solutions: [vhdltolatex.mamikon.net](http://vhdltolatex.mamikon.net/). But all of them lack proper language support. Is worth referring to [VisualHDL](http://visualhdl.sysprogs.org/) even though its input is THDL++ and outputs VHDL.\r\n\r\nA a result, I realized that the starting point should be a reliable VHDL parser. So I searched for free alternatives:\r\n\r\n  - Many grammars and parsers for VHDL 1993 (or version not specified) [[tams.informatik.uni-hamburg.de/vhdl](https://tams.informatik.uni-hamburg.de/vhdl/index.php?content=07-tools#grammar)]\r\n  - Not complete VHDL 2008 grammar for Coco/R [[github.com/wltr/coco-vhdl-2008](https://github.com/wltr/coco-vhdl-2008)]\r\n  - Handmade prototype of parser based on regexps [[bitbucket.org/AngelEzquerra/vhdl_analyzer](https://bitbucket.org/AngelEzquerra/vhdl_analyzer)].\r\n  - Parser for Perl last updated in 2002 [[cpan.org/~gslondon/Hardware-Vhdl-Parser-0.12](http://search.cpan.org/~gslondon/Hardware-Vhdl-Parser-0.12/)]\r\n  - Grammar for Lex-Yacc (version not specified) [[vhdlverif.sourceforge.net](http://vhdlverif.sourceforge.net/index.html)]\r\n  - Not complete VHDL 2008 AST [[github.com/grwlf/vsim/blob/master/grammar/vhdl-grammar](https://github.com/grwlf/vsim/blob/master/grammar/vhdl-grammar)]\r\n  - ANTLR4 grammars [[github.com/antlr/grammars-v4](https://github.com/antlr/grammars-v4)]\r\n\r\nSince I found no valid candidate, I had to accept that parsing VHDL is not straightforward. Some others reached the same conclusion before: [Parsing VHDL is [very] hard ](http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard), [A Note on the Parsing of Complete VHDL-2002](http://ceur-ws.org/Vol-255/paper11.pdf).\r\n\r\nThen, even though ANTLR4 could be the least bad starting point, maybe parsing VHDL with a general purpose engine is not the way to go. Since GHDL is a compiler, it actually parses at least part of the code. It's fast, lightweight, multiplatform, standalone and free. Moreover, it is known for being strict at conforming the standard. However, I know nothing about Ada and less about how compilers work. I don't know how much of the structure of the design has to be explicitly known by the GHDL core in order to generate machine code; i.e., whether blocks of VHDL code can be fed directly into an Ada compiler. Anyway, I have analized the content of a library file:\r\n\r\n```\r\n  package pkg at 1( 0) + 0 on 11;\r\n  package body pkg at 6( 93) + 0 on 12;\r\n  package mygpkg at 13( 232) + 0 on 13;\r\n  entity ent at 17( 293) + 0 on 14;\r\n  architecture arch of ent at 23( 400) + 0 on 15;\r\n```\r\n\r\nIt seems that I could build a hierarchy view of the packages, entities and architectures defined in each file. On top of that, the [pretty print command](http://ghdl.readthedocs.io/en/latest/Invoking_GHDL.html#pretty-print-command) and the [cross-reference command](http://ghdl.readthedocs.io/en/latest/Invoking_GHDL.html#cross-reference-command) syntax highlight every word; the second one also links every identifier (packages, entities, architectures, types, signals...) to it's declaration. Then, although I have not found explicit references in the user guide about how the html is generated, I would say that GHDL could be a good candidate. Nevertheless, the [interfacing to other languages](http://ghdl.readthedocs.io/en/latest/GHDL_implementation_of_VHDL.html#interfacing-to-other-languages) section of the user guide explains how to import subprograms, but not how to access to information about the design. I would say that the only choice at now is `AVHPI`, which is *a very light and slightly adapted version of VHPI*. I suppose that it is a very first step forward to something similar to [Aldec's VHPI Applications](https://www.aldec.com/en/support/resources/documentation/articles/1457).\r\n\r\nIn the end, the questions:\r\n\r\n- @tgingold, is GHDL suitable for this purposes, or is it focused on generating executable machine code?\r\n- Is Ada the only language which can be used to extract information of the elaborated design from GHDL?\r\n- Which are the supported VHPI functions and objects?\r\n- Given the actual status, how much effort would be needed to print the complete hierarchy of a design (top entity, ports, signals, processes, generate blocks, instantiated modules...) in any format (ascii tree to stdout, json, xml...).\r\n\r\nAlthough I don't feel confident enough to dive into the sources of GHDL, I wouldn't mind to give Ada a try someweek in the next months. I'd like to have a big picture, to have a better reference of how much time it would require."},"comment":{"url":"https://api.github.com/repos/tgingold/ghdl/issues/comments/230090108","html_url":"https://github.com/tgingold/ghdl/issues/111#issuecomment-230090108","issue_url":"https://api.github.com/repos/tgingold/ghdl/issues/111","id":230090108,"user":{"login":"tgingold","id":13433645,"avatar_url":"https://avatars.githubusercontent.com/u/13433645?v=3","gravatar_id":"","url":"https://api.github.com/users/tgingold","html_url":"https://github.com/tgingold","followers_url":"https://api.github.com/users/tgingold/followers","following_url":"https://api.github.com/users/tgingold/following{/other_user}","gists_url":"https://api.github.com/users/tgingold/gists{/gist_id}","starred_url":"https://api.github.com/users/tgingold/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tgingold/subscriptions","organizations_url":"https://api.github.com/users/tgingold/orgs","repos_url":"https://api.github.com/users/tgingold/repos","events_url":"https://api.github.com/users/tgingold/events{/privacy}","received_events_url":"https://api.github.com/users/tgingold/received_events","type":"User","site_admin":false},"created_at":"2016-07-02T08:08:34Z","updated_at":"2016-07-02T08:08:34Z","body":"On 02/07/16 07:52, 1138-4EB wrote:\n> I've been thinking long about having some multiplatform (windows and\n> gnu/linux), free (libre), lightweight and standalone tool to analize\n> large bodies of VHDL 2008 code at block/RTL level. That tool would\n> provide a hirarchy browser of the compiled/synthetized design, so that\n> all the parameterized types and components are resolved. Ideally, the\n> info in the hierarchy would be enough to build a command line tool to\n> draw diagrams with different levels of abstraction (entities, processes\n> and concurrent black boxes) for documentation purposes. As a dream, a\n> GUI could be built with linked references between diagrams and sources.\n>\n> Among those features, hierarchy browsers are already available in all\n> the big (and heavy) EDA tools and simulators; diagrams and linked\n> references are also supported by most of the big editors. However, most\n> of those tools require several GB to be installed, since they provide\n> lower levels of abstraction and many other utilities. On top of that,\n> the heavy GUIs must be launched even to just analize the hierarchy.\n>\n> The closest alternative I am aware of is RTLVision\n> <http://www.concept.de/nlview.html#FAMILY>. It seems\n> <http://www.concept.de/flash/RTL_basic.swf> to be very complete\n> technically, it is supported in multiple platforms\n> (windows/linux/solaris), and accepts VHDL, Verilog and System Verilog.\n> Moreover, the engine <http://www.concept.de/nlview.html#FAMILY> can be\n> used in many GUI environments. Indeed, I believe it is used by some of\n> the big players in the industry. It is not specified which the supported\n> versions of the standard are, but I believe it should be quite complete\n> for 2008, since they use <http://www.concept.de/nlview.html#FAMILY>\n> Verific <http://www.verific.com/>'s parser. However, I don't know how\n> fast it is, given that it accepts multiple languages, and that it\n> includes a waveform viewer to allow signal tracing. In any case, it is\n> neither libre nor free or open source.\n>\n> There are some projects from academia, such as VHDLVisualizer\n> <http://www2.fiit.stuba.sk/%7Emacko/VHDLVisualizer/> and HDLVisualizer\n> <http://labss2.fiit.stuba.sk/TeamProject/2011/team05pkss/docs/>; and\n> even web solutions: vhdltolatex.mamikon.net\n> <http://vhdltolatex.mamikon.net/>. But all of them lack proper language\n> support. Is worth referring to VisualHDL\n> <http://visualhdl.sysprogs.org/> even though its input is THDL++ and\n> outputs VHDL.\n>\n> A a result, I realized that the starting point should be a reliable VHDL\n> parser. So I searched for free alternatives:\n>\n>   * Many grammars and parsers for VHDL 1993 (or version not specified)\n>     [tams.informatik.uni-hamburg.de/vhdl\n>     <https://tams.informatik.uni-hamburg.de/vhdl/index.php?content=07-tools#grammar>]\n>   * Not complete VHDL 2008 grammar for Coco/R\n>     [github.com/wltr/coco-vhdl-2008\n>     <https://github.com/wltr/coco-vhdl-2008>]\n>   * Handmade prototype of parser based on regexps\n>     [bitbucket.org/AngelEzquerra/vhdl_analyzer\n>     <https://bitbucket.org/AngelEzquerra/vhdl_analyzer>].\n>   * Parser for Perl last updated in 2002\n>     [cpan.org/~gslondon/Hardware-Vhdl-Parser-0.12\n>     <http://search.cpan.org/%7Egslondon/Hardware-Vhdl-Parser-0.12/>]\n>   * Grammar for Lex-Yacc (version not specified)\n>     [vhdlverif.sourceforge.net\n>     <http://vhdlverif.sourceforge.net/index.html>]\n>   * Not complete VHDL 2008 AST\n>     [github.com/grwlf/vsim/blob/master/grammar/vhdl-grammar\n>     <https://github.com/grwlf/vsim/blob/master/grammar/vhdl-grammar>]\n>   * ANTLR4 grammars [github.com/antlr/grammars-v4\n>     <https://github.com/antlr/grammars-v4>]\n>\n> Since I found no valid candidate, I had to accept that parsing VHDL is\n> not straightforward. Some others reached the same conclusion before:\n> Parsing VHDL is [very] hard\n> <http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard>, A\n> Note on the Parsing of Complete VHDL-2002\n> <http://ceur-ws.org/Vol-255/paper11.pdf>.\n>\n> Then, even though ANTLR4 could be the least bad starting point, maybe\n> parsing VHDL with a general purpose engine is not the way to go. Since\n> GHDL is a compiler, it actually parses at least part of the code. It's\n> fast, lightweight, multiplatform, standalone and free. Moreover, it is\n> known for being strict at conforming the standard. However, I know\n> nothing about Ada and less about how compilers work. I don't know how\n> much of the structure of the design has to be explicitly known by the\n> GHDL core in order to generate machine code; i.e., whether blocks of\n> VHDL code can be fed directly into an Ada compiler. Anyway, I have\n> analized the content of a library file:\n>\n> |package pkg at 1( 0) + 0 on 11; package body pkg at 6( 93) + 0 on 12;\n> package mygpkg at 13( 232) + 0 on 13; entity ent at 17( 293) + 0 on 14;\n> architecture arch of ent at 23( 400) + 0 on 15; |\n>\n> It seems that I could build a hierarchy view of the packages, entities\n> and architectures defined in each file. On top of that, the pretty print\n> command\n> <http://ghdl.readthedocs.io/en/latest/Invoking_GHDL.html#pretty-print-command>\n> and the cross-reference command\n> <http://ghdl.readthedocs.io/en/latest/Invoking_GHDL.html#cross-reference-command>\n> syntax highlight every word; the second one also links every identifier\n> (packages, entities, architectures, types, signals...) to it's\n> declaration. Then, although I have not found explicit references in the\n> user guide, I would say that GHDL could be a good candidate.\n> Nevertheless, the interfacing to other languages\n> <http://ghdl.readthedocs.io/en/latest/GHDL_implementation_of_VHDL.html#interfacing-to-other-languages>\n> section of the user guide explains how to import subprograms, but not\n> how to access to information about the design. I would say that the only\n> choice at now is |AVHPI|, which is /a very light and slightly adapted\n> version of VHPI/. I suppose that it is a very first step forward to\n> something similar to Aldec's VHPI Applications\n> <https://www.aldec.com/en/support/resources/documentation/articles/1457>.\n\nWow, a lot of references.  I haven't yet read all these pages, but I can\nstill try to answer to your questions.\n\n> In the end, the questions:\n>\n>   * @tgingold <https://github.com/tgingold>, is GHDL suitable for this\n>     purposes, or is it focused on generating executable machine code?\n\nYes, it is suitable.  GHDL is able to parse and analyze vhdl sources and\nuses an AST as an internal representation of vhdl source.  This part is\nclearly separated from the code generation and simulation part.\nFor example, the cross-reference only uses the parser and analyzer, but\nnot at all the code generation part.\n\n>   * Is Ada the only language which can be used to extract information of\n>     the elaborated design from GHDL?\n\nNo.  The AST representation (documented in iirs.ads) could be read from\nany language.  It shouldn't be very hard to have a python interface\nfor example.\n\n>   * Which are the supported VHPI functions and objects?\n\nFar from being complete.  VHPI is only supported for the simulation\naspect, and just complete enough to support cocotb.\n\n>   * Given the actual status, how much effort would be needed to print\n>     the complete hierarchy of a design (top entity, ports, signals,\n>     processes, generate blocks, instantiated modules...) in any format\n>     (ascii tree to stdout, json, xml...).\n\nIt is already possible to display the hierarchy using the --disp-tree\noption.  The output is an ascii tree, but it wouldn't be that difficult\nto generate a json file.\n\nI will comment on the first part of your message later.\n\nTristan.\n\n"}}
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