{"push_id":1290536879,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"c68299484eb9161109c92f111b35419b115e306a","before":"6ff9c199caa9a7962e808420faf58e08689ce76a","commits":[{"sha":"847743b22a4438c476df81f87276d6d9dcae2440","author":{"name":"Chris Dewhurst","email":"4fe5183a5f31d288d84ba1f278a5aba47106ce56@lero.ie"},"message":"[Sparc][LEON] Unit test for CASA instruction supported by some LEON processors added.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281021 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/847743b22a4438c476df81f87276d6d9dcae2440"},{"sha":"43cc6f867615db404e17bf426b174d76113b4fee","author":{"name":"Simon Dardis","email":"2cadd7fe860cffe179363c66eef45424daae0f62@imgtec.com"},"message":"[mips] Fix c.<cc>.<fmt> instruction definition.\n\nAs part of this effort, remove MipsFCmp nodes and use tablegen\npatterns rather than custom lowering through C++.\n\nUnexpectedly, this improves codesize for microMIPS as previous floating\npoint setcc expansions would materialize 0 and 1 into GPRs before using\nthe relevant mov[tf].[sd] instruction. Now $zero is used directly.\n\nReviewers: dsanders, vkalintiris, zoran.jovanovic\n\nDifferential Review: https://reviews.llvm.org/D23118\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281022 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/43cc6f867615db404e17bf426b174d76113b4fee"},{"sha":"93211d99f1c184810399b4eb66c36d9303e4cd0b","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"[AMDGPU] Assembler: match e32 VOP instructions before e64.\n\nSummary:\nSplit assembler match table in 4 tables with assembler variants:\n\nDefault - all instructions except VOP3, SDWA and DPP\n  - VOP3\n  - SDWA\n  - DPP\nFirst match Default table then VOP3, SDWA and DPP.\n\nReviewers:  tstellarAMD, artem.tamazov, vpykhtin\n\nSubscribers: arsenm, wdng, nhaehnle, AMDGPU\n\nDifferential Revision: https://reviews.llvm.org/D24252\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281023 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/93211d99f1c184810399b4eb66c36d9303e4cd0b"},{"sha":"c68299484eb9161109c92f111b35419b115e306a","author":{"name":"James Molloy","email":"a1191294e96700f9c9e822da6f975d4f6164ab8d@arm.com"},"message":"[Thumb1] Teach optimizeCompareInstr about thumb1 compares\n\nThis avoids us doing a completely unneeded \"cmp r0, #0\" after a flag-setting instruction if we only care about the Z or C flags.\n\nAdd LSL/LSR to the whitelist while we're here and add testing. This code could really do with a spring clean.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281027 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/c68299484eb9161109c92f111b35419b115e306a"}]}
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