{"action":"opened","issue":{"url":"https://api.github.com/repos/michaeljclark/riscv-meta/issues/29","repository_url":"https://api.github.com/repos/michaeljclark/riscv-meta","labels_url":"https://api.github.com/repos/michaeljclark/riscv-meta/issues/29/labels{/name}","comments_url":"https://api.github.com/repos/michaeljclark/riscv-meta/issues/29/comments","events_url":"https://api.github.com/repos/michaeljclark/riscv-meta/issues/29/events","html_url":"https://github.com/michaeljclark/riscv-meta/issues/29","id":198217193,"number":29,"title":"Instruction sequence for bit sign extention","user":{"login":"jbrandmeyer","id":24849988,"avatar_url":"https://avatars.githubusercontent.com/u/24849988?v=3","gravatar_id":"","url":"https://api.github.com/users/jbrandmeyer","html_url":"https://github.com/jbrandmeyer","followers_url":"https://api.github.com/users/jbrandmeyer/followers","following_url":"https://api.github.com/users/jbrandmeyer/following{/other_user}","gists_url":"https://api.github.com/users/jbrandmeyer/gists{/gist_id}","starred_url":"https://api.github.com/users/jbrandmeyer/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jbrandmeyer/subscriptions","organizations_url":"https://api.github.com/users/jbrandmeyer/orgs","repos_url":"https://api.github.com/users/jbrandmeyer/repos","events_url":"https://api.github.com/users/jbrandmeyer/events{/privacy}","received_events_url":"https://api.github.com/users/jbrandmeyer/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2016-12-31T04:22:04Z","updated_at":"2016-12-31T04:22:04Z","closed_at":null,"body":"I think that you can perform bit sign extension in fewer instructions than claimed.  I'm using an ARMish syntax here (since that's what I'm familiar with...)\r\n\r\n; a0: argument\r\n; a1: value less than XLEN for the bit position to be extended\r\naddi a1 a1 #-32   ; Assuming 32-bit arch.  For RV64 or 128, replace as appropriate\r\nneg  a1 a1\r\nsll     a0 a0 a1\r\nsra   a0 a0 a1\r\n\r\nSimilarly, for signed bit extend by an immediate, you can just perform the left shift and arithmetic right shift."}}
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