{"push_id":1293401284,"size":110,"distinct_size":110,"ref":"refs/heads/master","head":"56e56fbc576ea68823bdd2057cee7df9e43737a8","before":"6ff9c199caa9a7962e808420faf58e08689ce76a","commits":[{"sha":"847743b22a4438c476df81f87276d6d9dcae2440","author":{"name":"Chris Dewhurst","email":"4fe5183a5f31d288d84ba1f278a5aba47106ce56@lero.ie"},"message":"[Sparc][LEON] Unit test for CASA instruction supported by some LEON processors added.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281021 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/847743b22a4438c476df81f87276d6d9dcae2440"},{"sha":"43cc6f867615db404e17bf426b174d76113b4fee","author":{"name":"Simon Dardis","email":"2cadd7fe860cffe179363c66eef45424daae0f62@imgtec.com"},"message":"[mips] Fix c.<cc>.<fmt> instruction definition.\n\nAs part of this effort, remove MipsFCmp nodes and use tablegen\npatterns rather than custom lowering through C++.\n\nUnexpectedly, this improves codesize for microMIPS as previous floating\npoint setcc expansions would materialize 0 and 1 into GPRs before using\nthe relevant mov[tf].[sd] instruction. Now $zero is used directly.\n\nReviewers: dsanders, vkalintiris, zoran.jovanovic\n\nDifferential Review: https://reviews.llvm.org/D23118\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281022 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/43cc6f867615db404e17bf426b174d76113b4fee"},{"sha":"93211d99f1c184810399b4eb66c36d9303e4cd0b","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"[AMDGPU] Assembler: match e32 VOP instructions before e64.\n\nSummary:\nSplit assembler match table in 4 tables with assembler variants:\n\nDefault - all instructions except VOP3, SDWA and DPP\n  - VOP3\n  - SDWA\n  - DPP\nFirst match Default table then VOP3, SDWA and DPP.\n\nReviewers:  tstellarAMD, artem.tamazov, vpykhtin\n\nSubscribers: arsenm, wdng, nhaehnle, AMDGPU\n\nDifferential Revision: https://reviews.llvm.org/D24252\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281023 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/93211d99f1c184810399b4eb66c36d9303e4cd0b"},{"sha":"c68299484eb9161109c92f111b35419b115e306a","author":{"name":"James Molloy","email":"a1191294e96700f9c9e822da6f975d4f6164ab8d@arm.com"},"message":"[Thumb1] Teach optimizeCompareInstr about thumb1 compares\n\nThis avoids us doing a completely unneeded \"cmp r0, #0\" after a flag-setting instruction if we only care about the Z or C flags.\n\nAdd LSL/LSR to the whitelist while we're here and add testing. This code could really do with a spring clean.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281027 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/c68299484eb9161109c92f111b35419b115e306a"},{"sha":"442deaa85b1e3e4adbf452762f361cd72ebdda32","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"[AMDGPU] Assembler: rename amd_kernel_code_t asm names according to spec\n\nSummary:\nAlso removed duplicate code from AMDGPUTargetAsmStreamer.\nThis change only change how amd_kernel_code_t is parsed and printed. No variable names are changed.\n\nReviewers: vpykhtin, tstellarAMD\n\nSubscribers: arsenm, wdng, nhaehnle\n\nDifferential Revision: https://reviews.llvm.org/D24296\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281028 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/442deaa85b1e3e4adbf452762f361cd72ebdda32"},{"sha":"80f518b791ffd34aabe619a3529f57e0c2cc6a59","author":{"name":"Simon Dardis","email":"2cadd7fe860cffe179363c66eef45424daae0f62@imgtec.com"},"message":"Revert \"[mips] Fix c.<cc>.<fmt> instruction definition.\"\n\nThis reverts commit r281022. Mips buildbot broke, due to unhandled register\nclass FCC.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281033 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/80f518b791ffd34aabe619a3529f57e0c2cc6a59"},{"sha":"59282d3fd2c0b8b949e51dd2b37b07931f63c513","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"GlobalISel: move type information to MachineRegisterInfo.\n\nWe want each register to have a canonical type, which means the best place to\nstore this is in MachineRegisterInfo rather than on every MachineInstr that\nhappens to use or define that register.\n\nMost changes following from this are pretty simple (you need an MRI anyway if\nyou're going to be doing any transformations, so just check the type there).\nBut legalization doesn't really want to check redundant operands (when, for\nexample, a G_ADD only ever has one type) so I've made use of MCInstrDesc's\noperand type field to encode these constraints and limit legalization's work.\n\nAs an added bonus, more validation is possible, both in MachineVerifier and\nMachineIRBuilder (coming soon).\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281035 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/59282d3fd2c0b8b949e51dd2b37b07931f63c513"},{"sha":"bc6470c4cd2bc950e929d147aeae1ebee4380836","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"GlobalISel: fix comments and add assertions for valid instructions.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281036 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/bc6470c4cd2bc950e929d147aeae1ebee4380836"},{"sha":"3c6f3f0961d2722354ac4b3da3f00d14cf6aa92c","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"GlobalISel: remove G_TYPE and G_PHI\n\nThese instructions were only necessary when type information was stored in the\nMachineInstr (because only generic MachineInstrs possessed a type). Now that\nit's in MachineRegisterInfo, COPY and PHI work fine.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281037 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/3c6f3f0961d2722354ac4b3da3f00d14cf6aa92c"},{"sha":"5349cafffb46c7a71fa6c695cc8aab32e048b555","author":{"name":"James Molloy","email":"a1191294e96700f9c9e822da6f975d4f6164ab8d@arm.com"},"message":"[Thumb] Select (CMPZ X, -C) -> (CMPZ (ADDS X, C), 0)\n\nThe CMPZ #0 disappears during peepholing, leaving just a tADDi3, tADDi8 or t2ADDri. This avoids having to materialize the expensive negative constant in Thumb-1, and allows a shrinking from a 32-bit CMN to a 16-bit ADDS in Thumb-2.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281040 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/5349cafffb46c7a71fa6c695cc8aab32e048b555"},{"sha":"31bcc1eeed93a3db76000a24d6c61468da70ea42","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type\n\nFixes issue with rL280927 identified by Mikael Holmén\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281042 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/31bcc1eeed93a3db76000a24d6c61468da70ea42"},{"sha":"f53c39572282cc566b084269758bf3e33e5d1bce","author":{"name":"James Molloy","email":"a1191294e96700f9c9e822da6f975d4f6164ab8d@arm.com"},"message":"[ARM] icmp %x, -C can be lowered to a simple ADDS or CMN\n\nTell TargetTransformInfo about this so ConstantHoisting is informed.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281043 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/f53c39572282cc566b084269758bf3e33e5d1bce"},{"sha":"b2500d218681aa1986132baa03e8dd07e76874b6","author":{"name":"James Molloy","email":"a1191294e96700f9c9e822da6f975d4f6164ab8d@arm.com"},"message":"[ARM] ADD with a negative offset can become SUB for free\n\nSo model that directly in TTI::getIntImmCost().\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281044 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/b2500d218681aa1986132baa03e8dd07e76874b6"},{"sha":"b68584d6d79b22d01d9d101ea991c1b7e197e172","author":{"name":"Chris Dewhurst","email":"4fe5183a5f31d288d84ba1f278a5aba47106ce56@lero.ie"},"message":"[Sparc][LEON] Removed the parts of the errata fixes implemented using inline assembly as this is not the desired behaviour for end-users. Small change to a unit test to implement this without requiring the inline assembly.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281047 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/b68584d6d79b22d01d9d101ea991c1b7e197e172"},{"sha":"03d317688de7f8f127391d4a75156f26fe4c9058","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"AMDGPU] Assembler: better support for immediate literals in assembler.\n\nSummary:\nPrevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.\nE.g. in instruction \"v_fract_f64 v[0:1], 0.5\", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.\n\nWith this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).\nHere are rules how we convert literals:\n    - We parsed fp literal:\n        - Instruction expects 64-bit operand:\n            - If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)\n                - then we do nothing this literal\n            - Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)\n                - report error\n            - Else literal is not-inlinable but we can encode it as additional 32-bit literal constant\n                - If instruction expect fp operand type (f64)\n                    - Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)\n                        - If so then do nothing\n                    - Else (e.g. v_fract_f64 v[0:1], 3.1415)\n                        - report warning that low 32 bits will be set to zeroes and precision will be lost\n                        - set low 32 bits of literal to zeroes\n                - Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)\n                    - report error as it is unclear how to encode this literal\n        - Instruction expects 32-bit operand:\n            - Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow\n            - Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)\n                - do nothing\n                - Else report error\n            - Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)\n    - Parsed binary literal:\n        - Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)\n            - do nothing\n        - Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)\n            - report error\n        - Else, literal is not-inlinable and we are not required to inline it\n            - Are high 32 bit of literal zeroes or same as sign bit (32 bit)\n                - do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)\n            - Else\n                - report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)\n\nFor this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:\n'''\nenum OperandType {\n    OPERAND_REG_IMM32_INT,\n    OPERAND_REG_IMM32_FP,\n    OPERAND_REG_INLINE_C_INT,\n    OPERAND_REG_INLINE_C_FP,\n}\n'''\n\nThis is not working yet:\n    - Several tests are failing\n    - Problems with predicate methods for inline immediates\n    - LLVM generated assembler parts try to select e64 encoding before e32.\nMore changes are required for several AsmOperands.\n\nReviewers: vpykhtin, tstellarAMD\n\nSubscribers: arsenm, kzhuravl, artem.tamazov\n\nDifferential Revision: https://reviews.llvm.org/D22922\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281050 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/03d317688de7f8f127391d4a75156f26fe4c9058"},{"sha":"a71022e182120f74214241b307dd9c9e900af58c","author":{"name":"Justin Lebar","email":"dbafad1a1f60894b4f707e683e2d6fa3d30dfa40@google.com"},"message":"[SelectionDAG] Fix two issues with SDNode::getRawSubclassData().\n\n1) On some platforms, sizeof(SDNodeBits) == 1, so we were only copying\none byte out of the bitfield when we wanted to copy two, and we were\nleaving half of the return value of getRawSubclassData() undefined.\n\n2) Something something bitfields, not sure exactly what the issue or fix\nis, yet.  (TODO)\n\nSummary:\nPreviously we were assuming that SDNodeBits covered all of SDNode's\nanonymous subclass data bitfield union.  But that's not right; it might\nhave size 1, in which it clearly doesn't.\n\nThis patch adds a field that does cover the whole union and adds\nstatic_asserts to ensure it stays correct.\n\nReviewers: ahatanak, chandlerc\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D24223\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281051 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/a71022e182120f74214241b307dd9c9e900af58c"},{"sha":"bb15e0c82d7c447c8779083b4de0777d6796945e","author":{"name":"Justin Lebar","email":"dbafad1a1f60894b4f707e683e2d6fa3d30dfa40@google.com"},"message":"Attempt to fix static_asserts in SelectionDAGNodes.h that MSVC chokes on.\n\nThese were added in r281051, which, I am embarrassed to admit, has an\nincomplete commit message that I forgot to update before pushing.  You\ncan ignore element (2) in that list.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281054 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/bb15e0c82d7c447c8779083b4de0777d6796945e"},{"sha":"6128d7f073fa08d69102162794c2d756ae9e12ee","author":{"name":"Sanjay Patel","email":"8a358757f1b64d62facccc1fd839683fb6856b45@rotateright.com"},"message":"[InstCombine] add tests to show pattern matching failures due to commutation\n\nI was looking to fix a bug in getComplexity(), and these cases showed up as \nobvious failures. I'm not sure how to find these in general though.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281055 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/6128d7f073fa08d69102162794c2d756ae9e12ee"},{"sha":"a8f2db504cc700faa606bf4c558ae894ddc0f66b","author":{"name":"Vedant Kumar","email":"e06201a831a99f4a997d7618bb35ffb5726917fe@apple.com"},"message":"[Bitcode] Add compatibility test for the 3.9 release\n\nFork off compatibility.ll for the 3.9 release. The *.bc file in this\ncommit was produced using a Release build of the release_39 branch.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281059 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/a8f2db504cc700faa606bf4c558ae894ddc0f66b"},{"sha":"a8b8839447d252494c885a888872c3b54f7f753c","author":{"name":"Reid Kleckner","email":"52b754ec9164ffe1549cbed996e28ab476b86804@google.com"},"message":"[codeview] Don't assert if the array element type is incomplete\n\nThis can happen when the frontend knows the debug info will be emitted\nsomewhere else. Usually this happens for dynamic classes with out of\nline constructors or key functions, but it can also happen when modules\nare enabled.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281060 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/omtcyfz/llvm/commits/a8b8839447d252494c885a888872c3b54f7f753c"}]}
{"actor":{"display_login":"omtcyfz"}}