{"action":"created","issue":{"url":"https://api.github.com/repos/cliffordwolf/yosys/issues/148","repository_url":"https://api.github.com/repos/cliffordwolf/yosys","labels_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/148/labels{/name}","comments_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/148/comments","events_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/148/events","html_url":"https://github.com/cliffordwolf/yosys/issues/148","id":146896791,"number":148,"title":"Simulation mismatch RTL vs. Synthesized.","user":{"login":"Kmanfi","id":14261732,"avatar_url":"https://avatars.githubusercontent.com/u/14261732?v=3","gravatar_id":"","url":"https://api.github.com/users/Kmanfi","html_url":"https://github.com/Kmanfi","followers_url":"https://api.github.com/users/Kmanfi/followers","following_url":"https://api.github.com/users/Kmanfi/following{/other_user}","gists_url":"https://api.github.com/users/Kmanfi/gists{/gist_id}","starred_url":"https://api.github.com/users/Kmanfi/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Kmanfi/subscriptions","organizations_url":"https://api.github.com/users/Kmanfi/orgs","repos_url":"https://api.github.com/users/Kmanfi/repos","events_url":"https://api.github.com/users/Kmanfi/events{/privacy}","received_events_url":"https://api.github.com/users/Kmanfi/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":{"login":"cliffordwolf","id":619764,"avatar_url":"https://avatars.githubusercontent.com/u/619764?v=3","gravatar_id":"","url":"https://api.github.com/users/cliffordwolf","html_url":"https://github.com/cliffordwolf","followers_url":"https://api.github.com/users/cliffordwolf/followers","following_url":"https://api.github.com/users/cliffordwolf/following{/other_user}","gists_url":"https://api.github.com/users/cliffordwolf/gists{/gist_id}","starred_url":"https://api.github.com/users/cliffordwolf/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cliffordwolf/subscriptions","organizations_url":"https://api.github.com/users/cliffordwolf/orgs","repos_url":"https://api.github.com/users/cliffordwolf/repos","events_url":"https://api.github.com/users/cliffordwolf/events{/privacy}","received_events_url":"https://api.github.com/users/cliffordwolf/received_events","type":"User","site_admin":false},"milestone":null,"comments":14,"created_at":"2016-04-08T11:11:19Z","updated_at":"2016-04-26T21:05:02Z","closed_at":"2016-04-26T21:05:02Z","body":"Copy all files from Archive.zip and simlib.v to same directory and execute ./st.sh\r\nIverilog and vsim both give same simulation output. b_out will change to 1 at 135.\r\nSynthesized result gives different output. b_out doesn't change to 1.\r\n\r\nFiles:\r\nSCRIPT: st.sh\r\nRTL: stg_bug.v\r\nTB: tb_stg.v\r\nYS: stg.ys\r\nNET: y_stg_bug.v (script will generate this)\r\n\r\n[Archive.zip](https://github.com/cliffordwolf/yosys/files/210035/Archive.zip)\r\n"},"comment":{"url":"https://api.github.com/repos/cliffordwolf/yosys/issues/comments/214885883","html_url":"https://github.com/cliffordwolf/yosys/issues/148#issuecomment-214885883","issue_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/148","id":214885883,"user":{"login":"cliffordwolf","id":619764,"avatar_url":"https://avatars.githubusercontent.com/u/619764?v=3","gravatar_id":"","url":"https://api.github.com/users/cliffordwolf","html_url":"https://github.com/cliffordwolf","followers_url":"https://api.github.com/users/cliffordwolf/followers","following_url":"https://api.github.com/users/cliffordwolf/following{/other_user}","gists_url":"https://api.github.com/users/cliffordwolf/gists{/gist_id}","starred_url":"https://api.github.com/users/cliffordwolf/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cliffordwolf/subscriptions","organizations_url":"https://api.github.com/users/cliffordwolf/orgs","repos_url":"https://api.github.com/users/cliffordwolf/repos","events_url":"https://api.github.com/users/cliffordwolf/events{/privacy}","received_events_url":"https://api.github.com/users/cliffordwolf/received_events","type":"User","site_admin":false},"created_at":"2016-04-26T21:05:02Z","updated_at":"2016-04-26T21:05:02Z","body":"The test case from two days ago turned out to be a case where undefs propagate differently in verilog ieee-std conforming simulation and synthesis. (Essentially: An `if` is just a MUX in synthesis, as is `?:`, but in simulation `if (foo)` treats an undefined (aka `x`) value for `foo` like a false. Most verilog designers will have seen cases where designs reset properly in simulation *and sometimes also in hardware*, but in post-synthesis simulation the x's just keep floating around and just won't go away. That's usually something like this.) So no bug."}}