{"push_id":980039989,"size":294,"distinct_size":51,"ref":"refs/heads/ti-lsk-linux-4.1.y","head":"b24a60815e58a7d19d8be88d6af4c37329e933a5","before":"317999e14119ae36bc26acdb1502fd1557dc0939","commits":[{"sha":"011837f72748e4096c8729f024eeeb0cadc5da88","author":{"email":"90cd1a2bf502062a09a1a38db4b5d470886df04b@linaro.org","name":"Jon Medhurst"},"message":"configs: vexpress64: Add PCI related configs use by for Juno r1\n\nSigned-off-by: Jon Medhurst <tixy@linaro.org>\n(cherry picked from commit 4e6c80894bb36f635ce8b8de1dd7655346add3aa)\nSigned-off-by: Alex Shi <alex.shi@linaro.org>\n\nConflicts solution:\n\t/* only pick pci kconfigs */\n\tlinaro/configs/vexpress64.conf","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/011837f72748e4096c8729f024eeeb0cadc5da88"},{"sha":"6844488aaa6b23d45106c9c3c3ba2f2ee4a612f9","author":{"email":"1abc5746028550adcf7742cb5d47df86766285d8@linaro.org","name":"Alex Shi"},"message":"Merge branch 'v4.1/topic/configs' into linux-linaro-lsk-v4.1","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/6844488aaa6b23d45106c9c3c3ba2f2ee4a612f9"},{"sha":"957bf614f97a0bc51a0ce64d0e02c57ef5be2d25","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"arm64: alternative: Introduce feature for GICv3 CPU interface\n\ncommit 94a9e04aa16abd1194d9b4158c618ba87f5d01e6 upstream.\n\nAdd a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF)\nto indicate that we have a system register GIC CPU interface\n\nThis will help KVM switching to alternative instruction patching.\n\nReviewed-by: Andre Przywara <andre.przywara@arm.com>\nReviewed-by: Christoffer Dall <christoffer.dall@linaro.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/957bf614f97a0bc51a0ce64d0e02c57ef5be2d25"},{"sha":"6d776fcf056f77d0169c4ea59ff97b8f46d2928c","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"arm64: lib: use pair accessors for copy_*_user routines\n\ncommit 23e94994464a7281838785675e09c8ed1055f62f upstream.\n\nThe AArch64 instruction set contains load/store pair memory accessors,\nso use these in our copy_*_user routines to transfer 16 bytes per\niteration.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/6d776fcf056f77d0169c4ea59ff97b8f46d2928c"},{"sha":"7a1da008242b6680e737bb220921a73db3ebf58d","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Move config_sctlr_el1\n\ncommit 870828e57b141eff76a5325f20e4691dd2a599b1 upstream.\n\nLater patches need config_sctlr_el1 to set/clear bits in the sctlr_el1\nregister.\n\nThis patch moves this function into header a file.\n\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: James Morse <james.morse@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/7a1da008242b6680e737bb220921a73db3ebf58d"},{"sha":"789e7a25029267e9472be672de6a6dcaccbd0b0e","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Add cpuid_feature_extract_field() for 4bit sign extension\n\ncommit 79b0e09a3c9bd74ee54582efdb351179d7c00351 upstream.\n\nBased on arch/arm/include/asm/cputype.h, this function does the\nshifting and sign extension necessary when accessing cpu feature fields.\n\nSigned-off-by: James Morse <james.morse@arm.com>\nSuggested-by: Russell King <linux@arm.linux.org.uk>\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/789e7a25029267e9472be672de6a6dcaccbd0b0e"},{"sha":"53ca685578587b717a4d1cbc1a7d2abbaf2ce943","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Add cpufeature 'enable' callback\n\ncommit 1c0763037f1e1caef739e36e09c6d41ed7b61b2d upstream.\n\nThis patch adds an 'enable()' callback to cpu capability/feature\ndetection, allowing features that require some setup or configuration\nto get this opportunity once the feature has been detected.\n\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: James Morse <james.morse@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/53ca685578587b717a4d1cbc1a7d2abbaf2ce943"},{"sha":"c6b421909cc9cc0053fd38e35800caf3113b881d","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Add min_field_value and use '>=' for feature detection\n\ncommit 18ffa046c509d0cd011eeea2c0418f2d014771fc upstream.\n\nWhen a new cpu feature is available, the cpu feature bits will have some\ninitial value, which is incremented when the feature is updated.\nThis patch changes 'register_value' to be 'min_field_value', and checks\nthe feature bits value (interpreted as a signed int) is greater than this\nminimum.\n\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: James Morse <james.morse@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/c6b421909cc9cc0053fd38e35800caf3113b881d"},{"sha":"d63c0243c5ffba7ca58b08685135b0f8d82cfdae","author":{"email":"25f0e69a3d23ed1d9a060214a9ff1a9504ba3f49@arm.com","name":"Suzuki K. Poulose"},"message":"arm64: Generalise msr_s/mrs_s operations\n\ncommit 9ded63aaf83eba76e1a54ac02581c2badc497f1a upstream.\n\nThe system register encoding generated by sys_reg() works only\nfor MRS/MSR(Register) operations, as we hardcode Bit20 to 1 in\nmrs_s/msr_s mask. This makes it unusable for generating instructions\naccessing registers with Op0 < 2(e.g, PSTATE.x with Op0=0).\n\nAs per ARMv8 ARM, (Ref: ARMv8 ARM, Section: \"System instruction class\nencoding overview\", C5.2, version:ARM DDI 0487A.f), the instruction\nencoding reserves bits [20-19] for Op0.\n\nThis patch generalises the sys_reg, mrs_s and msr_s macros, so that\nwe could use them to access any of the supported system register.\n\nCc: James Morse <james.morse@arm.com>\nCc: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/d63c0243c5ffba7ca58b08685135b0f8d82cfdae"},{"sha":"4739dc10110863af3ccbe7e923b061c04ca5069a","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"arm64: alternative: Merge alternative-asm.h into alternative.h\n\ncommit 8d883b23aed73cad844ba48051c7e96eddf0f51c upstream.\n\nasm/alternative-asm.h and asm/alternative.h are extremely similar,\nand really deserve to live in the same file (as this makes further\nmodufications a bit easier).\n\nFold the content of alternative-asm.h into alternative.h, and\nupdate the few users.\n\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/4739dc10110863af3ccbe7e923b061c04ca5069a"},{"sha":"348dc8b434c5f78bab436154e1b54e5441805261","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"arm64: alternative: Work around .inst assembler bugs\n\ncommit eb7c11ee3c5ce6c45ac28a5015a8e60ed458b412 upstream.\n\nAArch64 toolchains suffer from the following bug:\n\n$ cat blah.S\n1:\n\t.inst\t0x01020304\n\t.if ((. - 1b) != 4)\n\t\t.error\t\"blah\"\n\t.endif\n$ aarch64-linux-gnu-gcc -c blah.S\nblah.S: Assembler messages:\nblah.S:3: Error: non-constant expression in \".if\" statement\n\nwhich precludes the use of msr_s and co as part of alternatives.\n\nWe workaround this issue by not directly testing the labels\nthemselves, but by moving the current output pointer by a value\nthat should always be zero. If this value is not null, then\nwe will trigger a backward move, which is expclicitely forbidden.\nThis triggers the error we're after:\n\n  AS      arch/arm64/kvm/hyp.o\narch/arm64/kvm/hyp.S: Assembler messages:\narch/arm64/kvm/hyp.S:1377: Error: attempt to move .org backwards\nscripts/Makefile.build:294: recipe for target 'arch/arm64/kvm/hyp.o' failed\nmake[1]: *** [arch/arm64/kvm/hyp.o] Error 1\nMakefile:946: recipe for target 'arch/arm64/kvm' failed\n\nNot pretty, but at least works on the current toolchains.\n\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/348dc8b434c5f78bab436154e1b54e5441805261"},{"sha":"46c377b23c15ab98016e87c54a3513592d657cf9","author":{"email":"4421c302a8f2019ff02452a16ddbdd37770f814c@linaro.org","name":"Daniel Thompson"},"message":"arm64: alternative: Provide if/else/endif assembler macros\n\ncommit 63e40815f02584ba8174e0f6af40924b2b335cae upstream.\n\nThe existing alternative_insn macro has some limitations that make it\nhard to work with. In particular the fact it takes instructions from it\nown macro arguments means it doesn't play very nicely with C pre-processor\nmacros because the macro arguments look like a string to the C\npre-processor. Workarounds are (probably) possible but things start to\nlook ugly.\n\nIntroduce an alternative set of macros that allows instructions to be\npresented to the assembler as normal and switch everything over to the\nnew macros.\n\nSigned-off-by: Daniel Thompson <daniel.thompson@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/46c377b23c15ab98016e87c54a3513592d657cf9"},{"sha":"ec874614a43b6b21ea6de2c5a2e9dffe1d62d969","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Add optional CONFIG_ parameter to ALTERNATIVE()\n\ncommit 91a5cefa2f98bdd3404c2fba57048c4fa225cc37 upstream.\n\nSome uses of ALTERNATIVE() may depend on a feature that is disabled at\ncompile time by a Kconfig option. In this case the unused alternative\ninstructions waste space, and if the original instruction is a nop, it\nwastes time and space.\n\nThis patch adds an optional 'config' option to ALTERNATIVE() and\nalternative_insn that allows the compiler to remove both the original\nand alternative instructions if the config option is not defined.\n\nSuggested-by: Catalin Marinas <catalin.marinas@arm.com>\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: James Morse <james.morse@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/ec874614a43b6b21ea6de2c5a2e9dffe1d62d969"},{"sha":"f45972d0017cff35d576e10f1e276f9f3991bea6","author":{"email":"ebe5c4842edd72edc3a105fa34a4e41fed7a97bc@arm.com","name":"James Morse"},"message":"arm64: kernel: Add support for Privileged Access Never\n\ncommit 338d4f49d6f7114a017d294ccf7374df4f998edc upstream\n\n'Privileged Access Never' is a new arm8.1 feature which prevents\nprivileged code from accessing any virtual address where read or write\naccess is also permitted at EL0.\n\nThis patch enables the PAN feature on all CPUs, and modifies {get,put}_user\nhelpers temporarily to permit access.\n\nThis will catch kernel bugs where user memory is accessed directly.\n'Unprivileged loads and stores' using ldtrb et al are unaffected by PAN.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: James Morse <james.morse@arm.com>\n[will: use ALTERNATIVE in asm and tidy up pan_enable check]\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: David Brown <david.brown@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/f45972d0017cff35d576e10f1e276f9f3991bea6"},{"sha":"8eec3ec7b6576a80fbeda89beed8f9f667f9dc7b","author":{"email":"f9849b02abe18c1ece6bd40346458ed53f49d31b@linaro.org","name":"Kevin Hilman"},"message":"Merge tag 'v4.1.14' of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into linux-linaro-lsk-v4.1\n\nThis is the 4.1.14 stable release\n\n# gpg: Signature made Wed Dec  9 11:03:49 2015 PST using RSA key ID 6092693E\n# gpg: Good signature from \"Greg Kroah-Hartman (Linux kernel stable release signing key) <greg@kroah.com>\"\n\n* tag 'v4.1.14' of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (97 commits)\n  Linux 4.1.14\n  netlink: Add missing goto statement to netlink_insert\n  KVM: s390: enable SIMD only when no VCPUs were created\n  staging/lustre: use jiffies for lp_last_query times\n  xhci: Workaround to get Intel xHCI reset working more reliably\n  tty: Fix tty_send_xchar() lock order inversion\n  tty: audit: Fix audit source\n  ALSA: usb-audio: work around CH345 input SysEx corruption\n  ALSA: usb-audio: prevent CH345 multiport output SysEx corruption\n  ALSA: usb-audio: add packet size quirk for the Medeli DD305\n  USB: option: add XS Stick W100-2 from 4G Systems\n  USB: serial: option: add support for Novatel MiFi USB620L\n  USB: ti_usb_3410_5052: Add Honeywell HGI80 ID\n  usb: musb: core: fix order of arguments to ulpi write callback\n  USB: qcserial: Fix support for HP lt4112 LTE/HSPA+ Gobi 4G Modem\n  USB: qcserial: Add support for Quectel EC20 Mini PCIe module\n  usblp: do not set TASK_INTERRUPTIBLE before lock\n  usb: ehci-orion: fix probe for !GENERIC_PHY\n  ALSA: usb: Add native DSD support for Aune X1S\n  usb: chipidea: imx: refine clock operations to adapt for all platforms\n  ...","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/8eec3ec7b6576a80fbeda89beed8f9f667f9dc7b"},{"sha":"9f41e6b222c4a04c7b46068df82842a6188b4a57","author":{"email":"f9849b02abe18c1ece6bd40346458ed53f49d31b@linaro.org","name":"Kevin Hilman"},"message":"Merge branch 'v4.1/topic/PAN' into linux-linaro-lsk-v4.1\n\n* v4.1/topic/PAN:\n  arm64: kernel: Add support for Privileged Access Never\n  arm64: kernel: Add optional CONFIG_ parameter to ALTERNATIVE()\n  arm64: alternative: Provide if/else/endif assembler macros\n  arm64: alternative: Work around .inst assembler bugs\n  arm64: alternative: Merge alternative-asm.h into alternative.h\n  arm64: Generalise msr_s/mrs_s operations\n  arm64: kernel: Add min_field_value and use '>=' for feature detection\n  arm64: kernel: Add cpufeature 'enable' callback\n  arm64: kernel: Add cpuid_feature_extract_field() for 4bit sign extension\n  arm64: kernel: Move config_sctlr_el1\n  arm64: lib: use pair accessors for copy_*_user routines\n  arm64: alternative: Introduce feature for GICv3 CPU interface","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/9f41e6b222c4a04c7b46068df82842a6188b4a57"},{"sha":"039b7fca24dba50c09e60b23494ba3c4d19aac7d","author":{"email":"1abc5746028550adcf7742cb5d47df86766285d8@linaro.org","name":"Alex Shi"},"message":"Merge remote-tracking branch 'lts/linux-4.1.y' into linux-linaro-lsk-v4.1\n\nMerge tag 'v4.1.15' into of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into linux-linaro-lsk-v4.1","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/039b7fca24dba50c09e60b23494ba3c4d19aac7d"},{"sha":"c84c1562e9f295206849c42e366b720e6f6d5075","author":{"email":"b07d7e22a002c36e256b78f51f1f0db608e62a13@arm.com","name":"Lorenzo Pieralisi"},"message":"ARM64: kernel: make cpu_ops hooks DT agnostic\n\nARM64 CPU operations such as cpu_init and cpu_init_idle take\na struct device_node pointer as a parameter, which corresponds to\nthe device tree node of the logical cpu on which the operation\nhas to be applied.\n\nWith the advent of ACPI on arm64, where MADT static table entries\nare used to initialize cpus, the device tree node parameter\nin cpu_ops hooks become useless when booting with ACPI, since\nin that case cpu device tree nodes are not present and can not be\nused for cpu initialization.\n\nThe current cpu_init hook requires a struct device_node pointer\nparameter because it is called while parsing the device tree to\ninitialize CPUs, when the cpu_logical_map (that is used to match\na cpu node reg property to a device tree node) for a given logical\ncpu id is not set up yet. This means that the cpu_init hook cannot\nrely on the of_get_cpu_node function to retrieve the device tree\nnode corresponding to the logical cpu id passed in as parameter,\nso the cpu device tree node must be passed in as a parameter to fix\nthis catch-22 dependency cycle.\n\nThis patch reshuffles the cpu_logical_map initialization code so\nthat the cpu_init cpu_ops hook can safely use the of_get_cpu_node\nfunction to retrieve the cpu device tree node, removing the need for\nthe device tree node pointer parameter.\n\nIn the process, the patch removes device tree node parameters\nfrom all cpu_ops hooks, in preparation for SMP DT/ACPI cpus\ninitialization consolidation.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Hanjun Guo <hanjun.guo@linaro.org>\nAcked-by: Sudeep Holla <sudeep.holla@arm.com>\nAcked-by: Mark Rutland <mark.rutland@arm.com>\nTested-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Mark Rutland <mark.rutland@arm.com> [DT]\nCc: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\n(cherry picked from commit 819a88263d5dbe398edd59cc1cf725ed1fdcfd79)\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/c84c1562e9f295206849c42e366b720e6f6d5075"},{"sha":"68b7699ef819190a9fb1e47a27ba2627640dab04","author":{"email":"b07d7e22a002c36e256b78f51f1f0db608e62a13@arm.com","name":"Lorenzo Pieralisi"},"message":"ARM64: kernel: unify ACPI and DT cpus initialization\n\nThe code that initializes cpus on arm64 is currently split in two\ndifferent code paths that carry out DT and ACPI cpus initialization.\n\nMost of the code executing SMP initialization is common and should\nbe merged to reduce discrepancies between ACPI and DT initialization\nand to have code initializing cpus in a single common place in the\nkernel.\n\nThis patch refactors arm64 SMP cpus initialization code to merge\nACPI and DT boot paths in a common file and to create sanity\nchecks that can be reused by both boot methods.\n\nCurrent code assumes PSCI is the only available boot method\nwhen arm64 boots with ACPI; this can be easily extended if/when\nthe ACPI parking protocol is merged into the kernel.\n\nSigned-off-by: Sudeep Holla <sudeep.holla@arm.com>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Hanjun Guo <hanjun.guo@linaro.org>\nAcked-by: Mark Rutland <mark.rutland@arm.com>\nTested-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Mark Rutland <mark.rutland@arm.com> [DT]\nCc: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\n(cherry picked from commit 0f0783365cbb7ec13a8f02198f6e1a146d94a5a9)\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/68b7699ef819190a9fb1e47a27ba2627640dab04"},{"sha":"e870d0f635bbefafbe48b24d9e7a568231da2303","author":{"email":"1db9dd262beaa64f35756dd39531d9747b7778bb@arm.com","name":"Mark Rutland"},"message":"arm/arm64: kvm: add missing PSCI include\n\nWe make use of the PSCI function IDs, but don't explicitly include the\nheader which defines them. Relying on transitive header includes is\nfragile and will be broken as headers are refactored.\n\nThis patch includes the relevant header file directly so as to avoid\nfuture breakage.\n\nSigned-off-by: Mark Rutland <mark.rutland@arm.com>\nAcked-by: Christoffer Dall <christoffer.dall@linaro.org>\nReviewed-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Hanjun Guo <hanjun.guo@linaro.org>\nCc: Marc Zyngier <marc.zyngier@arm.com>\n(cherry picked from commit 538b9b25fa5dd372eeb3eabc85cb24d5df9e317b)\nSigned-off-by: Alex Shi <alex.shi@linaro.org>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/e870d0f635bbefafbe48b24d9e7a568231da2303"}]}