{"push_id":1421970873,"size":36,"distinct_size":36,"ref":"refs/heads/riscv","head":"4abe250f0e63f646e86837a19c80fe1a27a0b957","before":"8157f6879c64011c0391a7ff8de2376b972d15ff","commits":[{"sha":"5872d720e8c9db46a1275f5065712264f8de2e9c","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"devcap: undo a mistake\n\nI forgot we actually are using devcap, and made a mistaken\npush to sha256. That's going to be a while on Harvey.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/5872d720e8c9db46a1275f5065712264f8de2e9c"},{"sha":"3c6379dc2086be0f13ca898f1e0578c07cac6388","author":{"name":"Álvaro Jurado","email":"cc051656c26eb0c52594fa03b0bb3d8a42aa047e@gmail.com"},"message":"Qemu scripts XXI century\n\nq35 = ICH9 (not FX440 with pc)\nsmp 1 is by default, today all the 64 bit processors\nhave at least two cores.\n\nSigned-off-by: Álvaro Jurado <elbingmiss@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/3c6379dc2086be0f13ca898f1e0578c07cac6388"},{"sha":"ba774204c976b3d3232d2e081257a294f15f36fa","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: get further in the boot process\n\nwe have print. Now need to work out meminit.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/ba774204c976b3d3232d2e081257a294f15f36fa"},{"sha":"b05e0e865d415e0bd26073c23b55812c4a886fdd","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: further compiling and panicing\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/b05e0e865d415e0bd26073c23b55812c4a886fdd"},{"sha":"7f47b26cfcaf2f0565104d311a2377e408ca5773","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: adjust computation for mappings in PADDR\n\nI'm working on a long note to put into the code,\nbut the short form here is that riscv memory starts\nat 0x80000000, whereas on x86 it starts at 0. This\nbroke as assumption in PADDR about how to map kernel\nvirtual to physical. This is a simple fix that makes\nit work again.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/7f47b26cfcaf2f0565104d311a2377e408ca5773"},{"sha":"b43a949327a4ad7ae9ad107dd84e50f65b43b41d","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"RISCV: clean up mmu code\n\nFix up PDMAP mapping, and just clean things up\nin general. Change things related to the fact that\nwe're using coreboot-defined page tables for kernel\naddresses.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/b43a949327a4ad7ae9ad107dd84e50f65b43b41d"},{"sha":"e46f3940c8de62121c41f5db2694e2555af82439","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: move main to assembly\n\nThe stack needs to be set before we use C at all.\nWe got fooled because coreboot was mapping memory\nin the wrong place.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/e46f3940c8de62121c41f5db2694e2555af82439"},{"sha":"a139dcfc65811990e3b26d7d971bd2277ef5ba5e","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: further memory map/vm adjustments\n\nplan 9 is really wired to believe memory starts at 0.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/a139dcfc65811990e3b26d7d971bd2277ef5ba5e"},{"sha":"94e0ef81336e539c5fe67b54ad2541a1b4e940b5","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: clean up PADDR\n\nThere were more assumptions that fail the RISCV\n\"physmem starts at 2GiB\" model.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/94e0ef81336e539c5fe67b54ad2541a1b4e940b5"},{"sha":"d93abab213286c9bd9d29855a74911d4a034e1bd","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: handle the fact that we can get 3 or 4 level page tables\n\nThis should work for now, but it's not nice. Basically if we're on a machine\nwith a 3 level pt we fake up the 4th level to make the software simpler. This basically\nis hurl-inducing but gets us further in boot while we work out how we really\nwant to handle it.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/d93abab213286c9bd9d29855a74911d4a034e1bd"},{"sha":"1c102d6ac49ddb0a194cf458dc54cc12c7859c44","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: get rid of the PDMAP and all its badness\n\nPDMAP was always meant to die. No need to bring it\nforward into riscv.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/1c102d6ac49ddb0a194cf458dc54cc12c7859c44"},{"sha":"e0831bc009b38d2a92ed4ba9142c1eab3d8ab948","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: get further get past the first malloc.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/e0831bc009b38d2a92ed4ba9142c1eab3d8ab948"},{"sha":"d58fe20003c7e9a65d3ca14462ef36c1bf313a91","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: bring in trap() and friends\n\nThis gets past trapinit() and dies in timersinit(), which\nis common.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/d58fe20003c7e9a65d3ca14462ef36c1bf313a91"},{"sha":"dd1e2f8d1166aee7d8e77a74e795b71210f3e2e8","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: starting to get timers working\n\nThis gets timers working, though it requires a hacked\nversion of coreboot until the riscv community can finalize\nregister numbers.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/dd1e2f8d1166aee7d8e77a74e795b71210f3e2e8"},{"sha":"ded8f9564e38a569920e2bc4f788fc43a38dc0ab","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: add configstring parsing code\n\nThis is the initial commit, the code is not very nice.\nI'm going to merge this into one file, get rid of the\ntotally unnecessary inlines, and clean up the mess.\n\nThis won't come close to compiling.\n\nWe require this code so we can find the timer\ncomparator register, which can only be found by looking\nat the configstring. It will also allow us to find other neat\nthings such as the UART and # of harts.\n\nThe configstring will be passed from coreboot as the first\nparameter. I'm trying to get the riscv community to settle\non this simple model, i.e. first parameter to kernel\nentrypoint is the configstring, but they keep\nfixating on doing it via a callback to firmware. Ugh.\n\nIt is from lowrisc-bbl 87588c4\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/ded8f9564e38a569920e2bc4f788fc43a38dc0ab"},{"sha":"ac3799ea2383f65a90f0e8f3cb00ec3c714b7752","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: get configstring parsing to build\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/ac3799ea2383f65a90f0e8f3cb00ec3c714b7752"},{"sha":"978e29eb1ef462ee0e174591c9034bf34b592b14","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: change startup to accept the configstring\n\ncoreboot passes the configstring in a0. Extend the bsp\nfunction to take that parameter.\n\nTested and prints a config string.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/978e29eb1ef462ee0e174591c9034bf34b592b14"},{"sha":"5a7fdaa1daba2f2cff3114f9a7d76e8924141fa1","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: set things up for proc 1\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/5a7fdaa1daba2f2cff3114f9a7d76e8924141fa1"},{"sha":"7467db22b22ca2d0410535e0281b3498bedd0cb0","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: get rid of KSEG2 constant\n\nKSEG2 can't be a constant on riscv as the actual\nstart is determined by firmware, not hardware.\n\nIt really should not be constant on amd64, but someone\nelse gets to fix that; since the amd64 port was done\nthe VA size now has three possible values.\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/7467db22b22ca2d0410535e0281b3498bedd0cb0"},{"sha":"d07bad89bdc7d692cb2627988bc190587cc7e71d","author":{"name":"Ronald G. Minnich","email":"1ad177a67c639ec0754cbb464860f28ae81ec22e@gmail.com"},"message":"riscv: uart: use virtual addresses for the uart, not physical\n\nSigned-off-by: Ronald G. Minnich <rminnich@gmail.com>","distinct":true,"url":"https://api.github.com/repos/rminnich/harvey/commits/d07bad89bdc7d692cb2627988bc190587cc7e71d"}]}
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