{"push_id":1356561090,"size":101,"distinct_size":101,"ref":"refs/heads/i965-fp64-gen7-scalar-vec4-rc2","head":"ecce2b062168478c0755bf63d96f20d8852cf4a9","before":"506fef60485757d2417b226324e8f09e3b9c12e4","commits":[{"sha":"9ee74109ff0264cc4eb0a0c86cf19c1956deeb52","author":{"name":"Connor Abbott","email":"876a232321a04c735fc8a036bb66fd20fdea996b@intel.com"},"message":"i965/vec4/nir: allocate two registers for dvec3/dvec4\n\nv2 (Curro):\n  - Do not special-case for a bit-size of 64, divide the bit_size by 32\n    instead.\n  - Use DIV_ROUND_UP so we can handle sub-32-bit types.\n\nv3 (Ian):\n  - Make num_regs const.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/9ee74109ff0264cc4eb0a0c86cf19c1956deeb52"},{"sha":"9c1df6e84072545fb1b5dd91112d1a52370fc7f8","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/nir: Add bit-size information to types\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/9c1df6e84072545fb1b5dd91112d1a52370fc7f8"},{"sha":"99a9629b4321f90fbf24f125000c668ce47d015e","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/nir: support doubles in ALU operations\n\nBasically, this involves considering the bit-size information to set\nthe appropriate type on both operands and destination.\n\nv2 (Curro)\n  - Don't use two temporaries (and write one of them twice ) to obtain\n    the nir_alu_type.\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/99a9629b4321f90fbf24f125000c668ce47d015e"},{"sha":"31fb9a76eee00a37ca7f48f6f4372d73194e0010","author":{"name":"Connor Abbott","email":"876a232321a04c735fc8a036bb66fd20fdea996b@intel.com"},"message":"i965/vec4/nir: set the right type for 64-bit registers","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/31fb9a76eee00a37ca7f48f6f4372d73194e0010"},{"sha":"96a45af7c74afda65681f6c1f8e9307cdf82bacb","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/nir: fix emitting 64-bit immediates\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/96a45af7c74afda65681f6c1f8e9307cdf82bacb"},{"sha":"bf9581634e0d90fd8978482806ff297ee6999c4f","author":{"name":"Connor Abbott","email":"876a232321a04c735fc8a036bb66fd20fdea996b@intel.com"},"message":"i965/vec4: add support for printing DF immediates\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/bf9581634e0d90fd8978482806ff297ee6999c4f"},{"sha":"d9a4f96f428d1c067d7cb3295ad5a67e33b04606","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: add double/float conversion pseudo-opcodes\n\nThese need to be emitted as align1 MOV's, since they need to have a\nstride of 2 on the float register (whether src or dest) so that data\nfrom another thread doesn't cross the middle of a SIMD8 register.\n\nv2 (Iago):\n- The float-to-double needs to align 32-bit data to 64-bit before doing the\nconversion. This was doable in align16 when we tried to use an execsize\nof 4, but with an execsize of 8 we would need another align1 opcode to do\nthat (since we need data to cross the middle of a SIMD register). Just\nmaking the opcode handle this internally seems more practical that adding\nanother opcode just for this purpose and having the caller know about this\nbefore converting.\n- The double-to-float conversion produces 32-bit elements aligned to 64-bit\nso we make the opcode re-pack the result to 32-bit and fit in one register,\nas expected by SIMD4x2 operation. This still requires that callers reserve\ntwo registers for the float data destination because we need to produce\n64-bit aligned data first, and repack it later on the same destination\nregister, but it saves the need for a re-pack opcode only to achieve this\nmaking the operation complete in a single opcode. Hopefully that is worth\nthe weirdness of the double register allocation...\n\nSigned-off-by: Connor Abbott <connor.w.abbott@intel.com>\nSigned-off-by: Iago Toral Quiroga <itoral@igalia.com>\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/d9a4f96f428d1c067d7cb3295ad5a67e33b04606"},{"sha":"e1f32c9dc0c3f5078ad41372c337cf784e3ec36c","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: translate d2f/f2d","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/e1f32c9dc0c3f5078ad41372c337cf784e3ec36c"},{"sha":"7d8d6cacd0b1ee9b52a5dc68c54a2d79c78cf2c2","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965: fix subnr overflow in suboffset()\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/7d8d6cacd0b1ee9b52a5dc68c54a2d79c78cf2c2"},{"sha":"4488da18f942742073d4773fb3abc3d3e5ba2811","author":{"name":"Connor Abbott","email":"876a232321a04c735fc8a036bb66fd20fdea996b@intel.com"},"message":"i965: add brw_vecn_grf()\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/4488da18f942742073d4773fb3abc3d3e5ba2811"},{"sha":"5e4a6181787b3173db2674002971c5d4489cc8f7","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: set correct register regions for 32-bit and 64-bit\n\nFor 32-bit instructions we want to use <4,4,1> regions for VGRF\nsources so we should really set a width of 4 (we were setting 8).\n\nFor 64-bit instructions we want to use a width of 2 because the\nhardware uses 32-bit swizzles, meaning that we can only address 2\nconsecutive 64-bit components in a row. Also, Curro suggested that\nthe hardware is probably fixing the width to 2 for 64-bit instructions\nanyway, so just go with that and use <2,2,1>.\n\nv2:\n - No need to explicitly set the vertical stride of 64-bit regions to 2,\n   brw_vecn_grf with a width of 2 will do that for us.\n - No need to adjust the width of dst registers.\n\nv3 (Ian):\n - Make type_size and width const.\n\nSigned-off-by: Connor Abbott <connor.w.abbott@intel.com>\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/5e4a6181787b3173db2674002971c5d4489cc8f7"},{"sha":"a2124e398b9d67bb1e3703f65bacb684d821fcd7","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/disasm: align16 DF source regions have a width of 2\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/a2124e398b9d67bb1e3703f65bacb684d821fcd7"},{"sha":"05fd88840b0a6effea0a067b1a47a59d25670294","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: We only support 32-bit integer ALU operations for now\n\nAdd asserts so we remember to address this when we enable 64-bit\ninteger support, as suggested by Connor and Jason.\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/05fd88840b0a6effea0a067b1a47a59d25670294"},{"sha":"af9cffde832bf110c0e11f8ed466427f7e49a4c8","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: add dst_null_df()\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/af9cffde832bf110c0e11f8ed466427f7e49a4c8"},{"sha":"18da09d829e92b9ad58deb7960aa65029c07aafb","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes\n\nThese opcodes will pick the low/high 32-bit in each 64-bit data element\nusing Align1 mode. We will use this, for example, to do things like\nunpackDouble2x32.\n\nWe use Align1 mode because in order to implement this in Align16 mode\nwe would need to use 32-bit logical swizzles (XZ for low, YW for high),\nbut the IR works in terms of 64-bit logical swizzles for DF operands\nall the way up to codegen.\n\nv2:\n - use suboffset() instead of get_element_ud()\n - no need to set the width on the dst\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/18da09d829e92b9ad58deb7960aa65029c07aafb"},{"sha":"41eaeceae368ec231c932cbb7890c636dea8270d","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes\n\nThese opcodes will set the low/high 32-bit in each 64-bit data element\nusing Align1 mode. We will use this to implement packDouble2x32.\n\nWe use Align1 mode because in order to implement this in Align16 mode\nwe would need to use 32-bit logical swizzles (XZ for low, YW for high),\nbut the IR works in terms of 64-bit logical swizzles for DF operands\nall the way up to codegen.\n\nv2:\n - use suboffset() instead of get_element_ud()\n - no need to set the width on the dst\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/41eaeceae368ec231c932cbb7890c636dea8270d"},{"sha":"7e84a3768c170bd74cadb9df89e8ee10766bbbdf","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT\n\nThese align1 opcodes do partial writes of 64-bit data. The problem is that we\nwant to use them to write on the same register to implement packDouble2x32 and\nfrom the point of view of DCE, since both opcodes write to the same register,\nonly the last one stands and decides to eliminate the first, which is\nnot correct, so prevent this from happening.\n\nv2: Make a helper in vec4_instruction to know if the instruction is an\n    align1 partial write. This will come in handy when we implement a\n    simd splitting pass in a later patch.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/7e84a3768c170bd74cadb9df89e8ee10766bbbdf"},{"sha":"1778addb0d746e39ca122eac11d8ce55e62591a4","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: don't copy propagate vector opcodes that operate in align1 mode\n\nBasically, ALIGN1 mode will ignore swizzles on the input vectors so we don't\nwant the copy propagation pass to mess with them.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/1778addb0d746e39ca122eac11d8ce55e62591a4"},{"sha":"db1e32161a8f337df10179e11d1966720c4f1606","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: implement double unpacking\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/db1e32161a8f337df10179e11d1966720c4f1606"},{"sha":"6a2b88f898455512ebecafae6d55df31820e8fa3","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: implement double packing","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/6a2b88f898455512ebecafae6d55df31820e8fa3"}]}
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