{"push_id":1166884502,"size":12,"distinct_size":12,"ref":"refs/heads/socfpga_udk2015","head":"6b49b269b9901a8b79da743714328638687452ea","before":"37bea2f7ecc66eed88706a96af55da2e7866c23a","commits":[{"sha":"50032b95b74dfeb07f8a19112920db22f2c8332b","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #360977: Add support for ARMCC ver 5.06\n\nARMCC in SoCEDS 15.1.1 has been updated from version 5.05 to 5.06\nAdd support for ARMCC version 5.06 in UEFI setup.bat file\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/50032b95b74dfeb07f8a19112920db22f2c8332b"},{"sha":"efa6999ace28ee8f17123e6aa2c10d6c9b08d9b5","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #353573: Update Micrel KSZ9031 PHY AN FLP to 16ms instead default 8ms\n\nUpdate Micrel KSZ9031 PHY AN FLP Burst Trasmit\ntiming interval to 16ms instead default 8ms\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/efa6999ace28ee8f17123e6aa2c10d6c9b08d9b5"},{"sha":"1b4940c41d27b933365a4a437879585a294ea6b7","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #364186: Initialize the L2x0 Cache Controller\n\nInitialize the L2x0 Cache Controller\nAUX_CTRL:\nSet BIT0 - Full Line of Zero Enable\nClear BIT27 - Disable non-secure interrupt access control\nSet BIT28 - Data prefetch enable\nSet BIT29 -  Instruction prefetch enable\nSet BIT30 - Early BRESP enable\n\nTAG Lantencies = 0x0\nDATA Lantencies = 0x10\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/1b4940c41d27b933365a4a437879585a294ea6b7"},{"sha":"8d2fb42b5c2f6e2442645241109e1d51da0094f5","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #361312: Add capability to boot Linux zImage\n\nAdd capability to boot Linux zImage\n\n1) To boot Linux by default at PEI phase, set the PcdBoot_LOAD_ZIMAGE_AT_PEI_PHASE to 1\n2) To boot Linux manually from PitStop Utility, type \"bootz\" command\n3) To boot Linux from DXE Phase's UEFI Shell.\na) copy bootz.nsh to SDcard and type \"bootz\"\nb) or type \"LinuxLoader fs1:zImage -d fs1:socfpga_arria10_socdk.dtb -c \"console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait\"\"\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/8d2fb42b5c2f6e2442645241109e1d51da0094f5"},{"sha":"a9db4a289cdf75b404ce4feb04cebacd8e1eb838","author":{"name":"VIET NGA DAO","email":"b827b9ff4d9eeb967b1f95d34342ae11b1fef0f2@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #334562: Implement UEFI update for clock ramping\n\nRamp the PLL frequency to avoid generating a large current inrush\nwhich generates a droop in voltage affecting the PLL.\n\nContributed-under: TianoCore Contribution Agreement 1.0\n\nSigned-off-by: VIET NGA DAO <vndao@altera.com>\n\n---\nv2:\n- Use defined paramters for main_pll and peri_pll\n- Replace the _SET by _GET function for mpu and noc clk count\nv3:\n- Fixed wrong reg def used for MPUCLK","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/a9db4a289cdf75b404ce4feb04cebacd8e1eb838"},{"sha":"9865e7fee3fd34d9264361debc5d2e1ecaee1485","author":{"name":"VIET NGA DAO","email":"b827b9ff4d9eeb967b1f95d34342ae11b1fef0f2@altera.com"},"message":"AlteraPlatformPkg: Fofgbugz #380088: Implement UEFI early IO release\n\nAdding UEFI early IO features that users can program core rbf file\nautomatically or manually from PitStop.\n\nSigned-off-by: VIET NGA DAO <vndao@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/9865e7fee3fd34d9264361debc5d2e1ecaee1485"},{"sha":"4c93eb071a3883ac46ca58ff76385818bc28df2b","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #377715: Enable to boot Linux zImage from QSPI\n\nEnable to boot Linux zImage from QSPI\n\nStep 1: - download the qspiimage.img from GSRD\n==============================================\n\nYou want to start with a pre-build QSPI image with JFFS2 and Linux, and we will just do the replacing of U-boot with UEFI, this is much easier and less error prone than creating the whole QSPI image from scratch.\n\nSo, you need to know your are using A10SOC board with production silicon or ES silicon, because the RBF image is going to be different.\n\nIf you are using RevB.1 board which is ES silicon, goto\n\nhttps://rocketboards.org/foswiki/view/Documentation/A10GSRD151QspiBoot\n\nIf you are using RevC board with Production silicon, goto\n\nhttps://rocketboards.org/foswiki/view/Documentation/A10GSRD160QspiBoot\n\nAt the website search and download the Precompiled binaries .tar.gz file, which name something like linux-socfpga-gsrd-16.0-a10-qspi-bin.tar.gz\n\nAfter you download and extracted this file to a folder, look for another compressed file call qspiimage.tar.gz\n\nExtract the qspiimage.tar.gz to get the qspiimage.img we need.\n\nStep 2: - program the base GSRD QSPI image\n==========================================\nYou need to have latest Quartus programmer installed, run the command:\n\nquartus_hps -c1 -oP C:\\temp\\QSPI\\qspiimage.img --addr=0x0\n\nThis will take quite some time to program the 128MB of flash via JTAG interface.  Go do something else and come back later.\n\nStep 3: - Compile the UEFI to boot zImage by default\n====================================================\n\nOpen the AlteraPlatformPkg\\Arria10SoCPkg\\Arria10SoCPkg.dsc file for edit:\n\nLook for line, if the value is 0 change it to 1:\n\ngAlteraSocFpgaTokenSpaceGuid.PcdBoot_LOAD_ZIMAGE_AT_PEI_PHASE    |1\n\nRecompile the UEFI Bootloader\n\nIMPORTANT: Make sure the device tree (.DTB) you use for your UEFI is the device tree for QSPI not the SDMMC.  Same check for RBF.  Don't use the wrong one.\n\nNote: If you want to skip this step, you can load using DS-5 PEI.256 and type \"bootz\" when you reach pit stop.\n\nStep 4: - Replace the U-Boot with UEFI bootloader\n=================================================\n\nProgram the PEI.ROM to QSPI, example command :\n\nquartus_hps -c1 -oP C:\\uefi-socfpga\\Build\\PEI.ROM --addr=0x00000000\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/4c93eb071a3883ac46ca58ff76385818bc28df2b"},{"sha":"1230289ebf32c2908a2a86c27e73c09d2d42a8f9","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #379292: Updated UEFI HMC Adaptor DRAM IoSize code for SoCEDS 16.0\n\nUpdated UEFI HMC Adaptor DRAM IoSize code for SoCEDS 16.0\nNo longer need to use NIOSRESERVE1 register to make sure NIOSRESERVE0 register is valid.\n15.1.1 onward NIOSRESERVE0 register is always valid.\nThis will drop RevA board support, new code will work on RevB onward.\n\nContributed-under: TianoCore Contribution Agreement 1.0\n\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/1230289ebf32c2908a2a86c27e73c09d2d42a8f9"},{"sha":"2d9675196b9394e10a6033082646d4052bd725dc","author":{"name":"Chin Keong Ang","email":"cc2bed2b63c697051f810da8a74ea923f228066a@altera.com"},"message":"AlteraPlatformPkg: Fogbugz #380995: Make use of DS5_ROOT env var for Windows Build\n\nFor Windows build of UEFI Bootloader for A10 SoCFPGA\nuser need to run setup.bat first before running make\nnormally user just set the SOCEDS_DEST_ROOT env var before running setup.bat\nhowever if user does not install DS-5 under the %SOCEDS_DEST_ROOT%\\DS-5 folder\nuser can now define the %DS5_ROOT% env var,\nfor example set DS5_ROOT=c:\\progra~1\\DS-5 for \"C:\\Program Files\\DS-5\"\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Chin Keong Ang <ckang@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/2d9675196b9394e10a6033082646d4052bd725dc"},{"sha":"30621eb23d59377328d06dd8f960ea12cba11743","author":{"name":"VIET NGA DAO","email":"b827b9ff4d9eeb967b1f95d34342ae11b1fef0f2@altera.com"},"message":"AlteraPlatformPkg: Fofgbugz #381928: Fix UEFI build failed for armcc\n\nFixing the inconsistent type for RbfType and BootSourceType, wrong\nerror messages display for Load core Rbf to ram.\n\nSigned-off-by: VIET NGA DAO <vndao@altera.com>armcc error","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/30621eb23d59377328d06dd8f960ea12cba11743"},{"sha":"7ee7a312e7b7faf73886a3fdf661e873feed6981","author":{"name":"VIET NGA DAO","email":"b827b9ff4d9eeb967b1f95d34342ae11b1fef0f2@altera.com"},"message":"AlteraPlatformPkg: Fofgbugz #382278: UEFI failed to init SDRAM with armcc compiler\n\nRemove programming sync data after fpga program write.\n\nSigned-off-by: VIET NGA DAO <vndao@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/7ee7a312e7b7faf73886a3fdf661e873feed6981"},{"sha":"6b49b269b9901a8b79da743714328638687452ea","author":{"name":"VIET NGA DAO","email":"b827b9ff4d9eeb967b1f95d34342ae11b1fef0f2@altera.com"},"message":"AlteraPlatformPkg: Fofgbugz #382001: UEFI with early IO release in QSPI programs combined RBF\n\nChecking the size of rbf before deciding to program it.\n\nSigned-off-by: VIET NGA DAO <vndao@altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/uefi-socfpga/commits/6b49b269b9901a8b79da743714328638687452ea"}]}
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