{"push_id":1428116175,"size":23,"distinct_size":1,"ref":"refs/heads/ti-rt-linux-4.9.y","head":"2eba6e7c9f65bcdc8eef941e3ef24b84f31b5e5b","before":"200f7382b491338608a34874cc226ef7c23c3392","commits":[{"sha":"b18a8a70c9f0cc5c5daef0a202ce3a5bbfeab35c","author":{"name":"Grygorii Strashko","email":"6313aa67c79f49bbc5c7e7685d9d3910b42c6984@ti.com"},"message":"ARM: omap2: am437x: rollback to use omap3_gptimer_timer_init()\n\nThe commit 55ee7017ee31 (\"arm: omap2: board-generic: use\nomap4_local_timer_init for AM437x\") unintentionally changes the\nclocksource devices for AM437x from OMAP GP Timer to SyncTimer32K.\n\nUnfortunately, the SyncTimer32K is starving from frequency deviation\nas mentioned in commit 5b5c01359152 (\"ARM: OMAP2+: AM43x: Use gptimer\nas clocksource\") and, as reported by Franklin [1], even its monotonic\nnature is under question (most probably there is a HW issue, but it's\nstill under investigation).\n\nTaking into account above facts It's reasonable to rollback to the use\nof omap3_gptimer_timer_init().\n\n[1] http://www.spinics.net/lists/linux-omap/msg127425.html\nReported-by: Cooper Jr., Franklin <fcooper@ti.com>\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b18a8a70c9f0cc5c5daef0a202ce3a5bbfeab35c"},{"sha":"f7c00b537b900fd308734532bebbc090da483d25","author":{"name":"Grygorii Strashko","email":"6313aa67c79f49bbc5c7e7685d9d3910b42c6984@ti.com"},"message":"ARM: omap: timers: reduce rating of gp_timer clocksource\n\nNow ARM Global timer (rating 300) will not be selected as clocksource,\nbecause it's initialized after OMAP GP Timer (rating 300) and\nTimekeeping core will not allow to replace clocksource with new one if\nboth of them have the same rating.\n\nReduce rating of OMAP GP Timer (300->290) when it's used as\nclocksource device - this will allow to select ARM Global timer (300)\nas clocksource when enabled.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Dave Gerlach <d-gerlach@ti.com>\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/f7c00b537b900fd308734532bebbc090da483d25"},{"sha":"a6b8f4ec2868afab9382c84b681712963074b0a6","author":{"name":"Keerthy","email":"291a1b6d3a1977d1bab9cf84a427d4c28ba1c0e6@ti.com"},"message":"Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition\n\nGPIO7 is configured in POWERHOLD mode which has higher priority\nover DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON\nbit is turned off. This property enables driver to over ride the\nPOWERHOLD value to GPIO7 so as to turn off the PMIC in power off\nscenarios.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/a6b8f4ec2868afab9382c84b681712963074b0a6"},{"sha":"b7f19ea9ed9398b5b680614b29d1064c074a5e9a","author":{"name":"Keerthy","email":"291a1b6d3a1977d1bab9cf84a427d4c28ba1c0e6@ti.com"},"message":"mfd: palmas: Remove redundant check in palmas_power_off\n\npalmas_dev and palmas_power_off are always assigned together.\nSo the check for palmas_dev inside palmas_power_off function\nis redundant. Removing the same.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b7f19ea9ed9398b5b680614b29d1064c074a5e9a"},{"sha":"484946dbf11942e6000777f6e0eec86de14c232f","author":{"name":"Keerthy","email":"291a1b6d3a1977d1bab9cf84a427d4c28ba1c0e6@ti.com"},"message":"mfd: palmas: Reset the POWERHOLD mux during power off\n\nPOWERHOLD signal has higher priority  over the DEV_ON bit.\nSo power off will not happen if the POWERHOLD is held high.\nHence reset the MUX to GPIO_7 mode to release the POWERHOLD\nand the DEV_ON bit to take effect to power off the PMIC.\n\nPMIC Power off happens in dire situations like thermal shutdown\nso irrespective of the POWERHOLD setting go ahead and turn off\nthe powerhold.  Currently poweroff is broken on boards that have\npowerhold enabled. This fixes poweroff on those boards.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/484946dbf11942e6000777f6e0eec86de14c232f"},{"sha":"0517a1eca26a658fdf52f6a642ff179e8139e55a","author":{"name":"Keerthy","email":"291a1b6d3a1977d1bab9cf84a427d4c28ba1c0e6@ti.com"},"message":"arm: dts: am57xx-beagle-x15-common: Add overide powerhold property\n\ncommit 1f166499ce006b3770a3166122eda64e160736ab upstream\n\nThe PMICs have POWERHOLD set by default which prevents PMIC shutdown\neven on DEV_CTRL On bit set to 0 as the Powerhold has higher priority.\nSo to enable pmic power off this property lets one over ride the default\nvalue and enable pmic power off.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/0517a1eca26a658fdf52f6a642ff179e8139e55a"},{"sha":"f2fccf67d784094cad6e84771cfa263c914d4c16","author":{"name":"Keerthy","email":"291a1b6d3a1977d1bab9cf84a427d4c28ba1c0e6@ti.com"},"message":"arm: dts: am57xx-idk-common: Add overide powerhold property\n\ncommit 8804755bfb1f3cbc003e4ebe99eac491672f354c upstream\n\nThe PMICs have POWERHOLD set by default which prevents PMIC shutdown\neven on DEV_CTRL On bit set to 0 as the Powerhold has higher priority.\nSo to enable pmic power off this property lets one over ride the default\nvalue and enable pmic power off.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/f2fccf67d784094cad6e84771cfa263c914d4c16"},{"sha":"e718a97e883ccd1878006833328a38808fd8277c","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"watchdog: davinci: add support for deferred probing\n\ndevm_clk_get can fail with EPROBE_DEFER in case the clock provider is\nnot ready yet. Handle this case gracefully, rather than dumping out\na huge warning.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/e718a97e883ccd1878006833328a38808fd8277c"},{"sha":"4012518e4faec1b12a6c7adbe09fbf79ee8a16c9","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"ARM: ds: keystone-k2g: add watchdog support\n\nAdd a watchdog node for keystone-k2g, with the corresponding clock and\npower domain handles.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/4012518e4faec1b12a6c7adbe09fbf79ee8a16c9"},{"sha":"714e02803b5f325001560c8dd2bda720e83f8f84","author":{"name":"Joel Fernandes","email":"0f877ea3a7612f3c6dbe2193ac4d434480e5b326@ti.com"},"message":"ARM: DRA7: hwmod: Add data for DES IP\n\nDRA7 SoC contains DES crypto hardware accelerator. Add hwmod data for\nthis IP so that it can be utilized by crypto frameworks.\n\nSigned-off-by: Joel Fernandes <joelf@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/714e02803b5f325001560c8dd2bda720e83f8f84"},{"sha":"14f3f00c859cdf02624cdbc290e099ce212c7ef7","author":{"name":"Joel Fernandes","email":"0f877ea3a7612f3c6dbe2193ac4d434480e5b326@ti.com"},"message":"ARM: DRA7: hwmod: Add data for AES IP\n\nDRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for\nthis IP so that it can be utilized by crypto frameworks.\n\nSigned-off-by: Joel Fernandes <joelf@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n[t-kristo@ti.com: squash in support for both AES1 and AES2 cores]\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/14f3f00c859cdf02624cdbc290e099ce212c7ef7"},{"sha":"f602b1f335c8bd1ce402791a2728c8c080d7089f","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"ARM: DRA7: hwmod: Add data for SHA IP\n\nDRA7 SoC contains SHA crypto hardware accelerator. Add hwmod data for\nthis IP so that it can be utilized by crypto frameworks.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/f602b1f335c8bd1ce402791a2728c8c080d7089f"},{"sha":"b3c277a1e202d8396905b471ba2bfd2c0e6e7e05","author":{"name":"Joel Fernandes","email":"0f877ea3a7612f3c6dbe2193ac4d434480e5b326@ti.com"},"message":"ARM: DRA7: hwmod: Add data for RNG IP\n\nDRA7 SoC contains hardware random number generator. Add hwmod data for\nthis IP so that it can be utilized.\n\nSigned-off-by: Joel Fernandes <joelf@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n[t-kristo@ti.com: squashed the RNG hwmod IP flag fixes from Lokesh,\n                  squashed the HS chip fix from Daniel Allred]\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b3c277a1e202d8396905b471ba2bfd2c0e6e7e05"},{"sha":"88b596157e8fb057c32f7d3fdcaaacdddbc0a99b","author":{"name":"Joel Fernandes","email":"0f877ea3a7612f3c6dbe2193ac4d434480e5b326@ti.com"},"message":"ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only\n\nUsing HWSUP for l4sec clock domain is causing warnings in HWMOD code for\nDRA7. Based on some observations, once the clock domain goes into an IDLE\nstate (because of no activity etc), the IDLEST for the module goes to '0x2'\nvalue which means Interface IDLE condition. So far so go, however once the\nMODULEMODE is set to disabled for the particular IP, the IDLEST for the\nmodule should go to '0x3', per the HW AUTO IDLE protocol. However this is\nnot observed and there is no reason per the protocl for the transition to\nnot happen. This could potentially be a bug in the HW AUTO state-machine.\n\nWork around for this is to use SWSUP only for the particular clockdomain.\nWith this all the transitions of IDLEST happen correctly and warnings\ndon't occur.\n\nSigned-off-by: Joel Fernandes <joelf@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/88b596157e8fb057c32f7d3fdcaaacdddbc0a99b"},{"sha":"1f9d572f7a4d8a6d13f7043a4dda55a837868d3a","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"ARM: AM43xx: hwmod: Add data for DES\n\nAM43xx SoC contains DES crypto hardware accelerator. Add hwmod data for\nthis IP so that it can be utilized by crypto frameworks.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/1f9d572f7a4d8a6d13f7043a4dda55a837868d3a"},{"sha":"a0048e12237ee13999e63a75b11cf36d8bd141b1","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"ARM: AMx3xx: hwmod: Add data for RNG\n\nHardware random number generator is present in both AM33xx and AM43xx\nSoC's. So moving the hwmod data to common data.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/a0048e12237ee13999e63a75b11cf36d8bd141b1"},{"sha":"99f2c84ba255cda5a83c50bd51b7e80c95778014","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"crypto: omap-aes: drop unused flags attribute from omap_aes_ctx\n\nThis is not used for anything, so drop it.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/99f2c84ba255cda5a83c50bd51b7e80c95778014"},{"sha":"d7b43357ab941dec2f88fc019ffe695ec723e31b","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"crypto: omap-aes: move definitions over to a separate header file\n\nMove over most of the omap-aes driver internal definitions to a separate\nheader file. This is done so that the same definitions can be used in\nthe upcoming AES-GCM support code.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/d7b43357ab941dec2f88fc019ffe695ec723e31b"},{"sha":"460e7be6918936492d1f90ac743aea5a36f9ec13","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"crypto: omap-aes: fix context handling for multiple cores\n\nAES can have multiple HW accelerator cores in the system, in which case\neach core has its own crypto engine in use. Currently, the used hardware\ndevice is stored under the omap_aes_ctx struct, which is global for\nthe algorithm itself, causing conflicts when used with multiple cores.\nFix this by moving the used HW device under reqctx, which is stored\nper-request basis.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/460e7be6918936492d1f90ac743aea5a36f9ec13"},{"sha":"ecbcbd3f4306ff9b16a019119f10c001f5250fb2","author":{"name":"Tero Kristo","email":"183a510432c0612839b152b5f32aa94e5ab64976@ti.com"},"message":"crypto: omap-aes: export some AES driver functionality locally\n\nThese are going to be required by the addition of the GCM support.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/ecbcbd3f4306ff9b16a019119f10c001f5250fb2"}]}
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