{"push_id":1157702658,"size":9,"distinct_size":9,"ref":"refs/heads/master","head":"a28aae041aa76a779df6467a7fe68b9e8a8b2c0a","before":"2c96c379ac7a22424c25d65b73e81b860f902868","commits":[{"sha":"7386ae6372cc07c77a39cb3aa185848b43f7ae34","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"ppc/spapr: Refactor h_client_architecture_support() CPU parsing code\n\nThe h_client_architecture_support() function has become quite big\nand nested already. So factor out the code that takes care of the\nsPAPR compatibility PVRs (which will be modified by the following\npatches).\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nReviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/7386ae6372cc07c77a39cb3aa185848b43f7ae34"},{"sha":"8cd2ce7aaa3c3fadc561f40045d4d53ff72e94ef","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"ppc: Split pcr_mask settings into supported bits and the register mask\n\nThe current pcr_mask values are ambiguous: Should these be the mask\nthat defines valid bits in the PCR register? Or should these rather\nindicate which compatibility levels are possible? Anyway, POWER6 and\nPOWER7 should certainly not use the same values here. So let's\nintroduce an additional variable \"pcr_supported\" here which is\nused to indicate the valid compatibility levels, and use pcr_mask\nto signal the valid bits in the PCR register.\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/8cd2ce7aaa3c3fadc561f40045d4d53ff72e94ef"},{"sha":"52b2519c4ea9a6aa4df7abfe35fd1755c5c8546c","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"ppc: Provide function to get CPU class of the host CPU\n\nWhen running with KVM, we might be interested in some details\nof the host CPU class, too, so provide a function to get the\ncorresponding CPU class.\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nReviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/52b2519c4ea9a6aa4df7abfe35fd1755c5c8546c"},{"sha":"eac4fba965136f61cc239a450bec12adcef6b449","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"ppc: Improve PCR bit selection in ppc_set_compat()\n\nWhen using an olderr PowerISA level, all the upper compatibility\nbits have to be enabled, too. For example when we want to run\nsomething in PowerISA 2.05 compatibility mode on POWER8, the bit\nfor 2.06 has to be set beside the bit for 2.05.\nAdditionally, to make sure that we do not set bits that are not\nsupported by the host, we apply a mask with the known-to-be-good\nbits here, too.\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\n[dwg: Added some #ifs to fix compile on 32-bit targets]\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/eac4fba965136f61cc239a450bec12adcef6b449"},{"sha":"b30ff227c27c931155f768a04c44a6c8757f195f","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"ppc: Add PowerISA 2.07 compatibility mode\n\nMake sure that guests can use the PowerISA 2.07 CPU sPAPR\ncompatibility mode when they request it and the target CPU\nsupports it.\n\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/b30ff227c27c931155f768a04c44a6c8757f195f"},{"sha":"42bff4772ef96d901772240b10eda6d66ef771a1","author":{"name":"Anton Blanchard","email":"ce1a3ad8ea491e2355699b412ffe6d0f9ccbd22e@samba.org"},"message":"Add PowerPC AT_HWCAP2 definitions\n\nWe need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so\nadd the PowerPC AT_HWCAP2 definitions.\n\nSigned-off-by: Anton Blanchard <anton@samba.org>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/42bff4772ef96d901772240b10eda6d66ef771a1"},{"sha":"bc9ca5958d084222cdb233619dfc5046c81fb76d","author":{"name":"Mark Cave-Ayland","email":"d8f5d512409aa32dd23a063424a40bf02a4e4dda@ilande.co.uk"},"message":"macio: call dma_memory_unmap() at the end of each DMA transfer\n\nThis ensures that the underlying memory is marked dirty once the transfer\nis complete and resolves cache coherency problems under MacOS 9.\n\nSigned-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/bc9ca5958d084222cdb233619dfc5046c81fb76d"},{"sha":"d0e5a8f2937de66778d94c20a8fc5cf43501fa04","author":{"name":"Bharata B Rao","email":"4a8a72b12e293da877d43b61ea4a7e65067df7bb@linux.vnet.ibm.com"},"message":"spapr: Ensure all LMBs are represented in ibm,dynamic-memory\n\nMemory hotplug can fail for some combinations of RAM and maxmem when\nDDW is enabled in the presence of devices like nec-usb-xhci. DDW depends\non maximum addressable memory returned by guest and this value is currently\nbeing calculated wrongly by the guest kernel routine memory_hotplug_max().\nWhile there is an attempt to fix the guest kernel, this patch works\naround the problem within QEMU itself.\n\nmemory_hotplug_max() routine in the guest kernel arrives at max\naddressable memory by multiplying lmb-size with the lmb-count obtained\nfrom ibm,dynamic-memory property. There are two assumptions here:\n\n- All LMBs are part of ibm,dynamic memory: This is not true for PowerKVM\n  where only hot-pluggable LMBs are present in this property.\n- The memory area comprising of RAM and hotplug region is contiguous: This\n  needn't be true always for PowerKVM as there can be gap between\n  boot time RAM and hotplug region.\n\nTo work around this guest kernel bug, ensure that ibm,dynamic-memory\nhas information about all the LMBs (RMA, boot-time LMBs, future\nhotpluggable LMBs, and dummy LMBs to cover the gap between RAM and\nhotpluggable region).\n\nRMA is represented separately by memory@0 node. Hence mark RMA LMBs\nand also the LMBs for the gap b/n RAM and hotpluggable region as\nreserved and as having no valid DRC so that these LMBs are not considered\nby the guest.\n\nSigned-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>\nReviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>\nReviewed-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/d0e5a8f2937de66778d94c20a8fc5cf43501fa04"},{"sha":"a28aae041aa76a779df6467a7fe68b9e8a8b2c0a","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160614' into staging\n\nppc patch queue for 2016-06-14\n\nLatest patch queue for ppc.\n    * Allow qemu to support a generic architecture 2.07 (POWER8-era)\n      compatibility mode.  This is useful for guests which are POWER8\n      aware, but don't know about the specific POWER8 variant that\n      qemu (and/or KVM) is emulating. (Thomas Huth)\n    * Fix a bug where macio wasn't removing DMA mappings (Mark Cave-Ayland)\n    * Add a workaround for Linux guest's miscalculation of maximum\n      memory address (including hotplugged memory), which could break\n      when hotplug memory was combined with VFIO.  The previous\n      approach was technically correct by spec, but differed from\n      PowerVM's behaviour enough to trip a guest kernel bug.  This\n      works around the bug, while remaining correct-to-spec. (Bharata Rao)\n\n# gpg: Signature made Tue 14 Jun 2016 06:53:58 BST\n# gpg:                using RSA key 0x6C38CACA20D9B392\n# gpg: Good signature from \"David Gibson <david@gibson.dropbear.id.au>\"\n# gpg:                 aka \"David Gibson (Red Hat) <dgibson@redhat.com>\"\n# gpg:                 aka \"David Gibson (ozlabs.org) <dgibson@ozlabs.org>\"\n# gpg: WARNING: This key is not certified with sufficiently trusted signatures!\n# gpg:          It is not certain that the signature belongs to the owner.\n# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392\n\n* remotes/dgibson/tags/ppc-for-2.7-20160614:\n  spapr: Ensure all LMBs are represented in ibm,dynamic-memory\n  macio: call dma_memory_unmap() at the end of each DMA transfer\n  Add PowerPC AT_HWCAP2 definitions\n  ppc: Add PowerISA 2.07 compatibility mode\n  ppc: Improve PCR bit selection in ppc_set_compat()\n  ppc: Provide function to get CPU class of the host CPU\n  ppc: Split pcr_mask settings into supported bits and the register mask\n  ppc/spapr: Refactor h_client_architecture_support() CPU parsing code\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/a28aae041aa76a779df6467a7fe68b9e8a8b2c0a"}]}
{"actor":{"display_login":"famz"}}