{"action":"opened","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel3/issues/238","repository_url":"https://api.github.com/repos/ucb-bar/chisel3","labels_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/238/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/238/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/238/events","html_url":"https://github.com/ucb-bar/chisel3/issues/238","id":166910061,"number":238,"title":"No support for readwrite ports of memories","user":{"login":"donggyukim","id":5387248,"avatar_url":"https://avatars.githubusercontent.com/u/5387248?v=3","gravatar_id":"","url":"https://api.github.com/users/donggyukim","html_url":"https://github.com/donggyukim","followers_url":"https://api.github.com/users/donggyukim/followers","following_url":"https://api.github.com/users/donggyukim/following{/other_user}","gists_url":"https://api.github.com/users/donggyukim/gists{/gist_id}","starred_url":"https://api.github.com/users/donggyukim/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/donggyukim/subscriptions","organizations_url":"https://api.github.com/users/donggyukim/orgs","repos_url":"https://api.github.com/users/donggyukim/repos","events_url":"https://api.github.com/users/donggyukim/events{/privacy}","received_events_url":"https://api.github.com/users/donggyukim/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2016-07-21T20:27:28Z","updated_at":"2016-07-21T20:27:28Z","closed_at":null,"body":"For now, there's no way to express readwrite ports in Chisel3. In Chisel2, they are inferred from read and write ports by checking their enable signals. I think there should be an explicit way as well as an implicit way to infer in firrtl."}}
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