{"action":"created","comment":{"url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/comments/52151527","id":52151527,"diff_hunk":"@@ -0,0 +1,483 @@\n+/*\n+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * Redistributions of source code must retain the above copyright notice, this\n+ * list of conditions and the following disclaimer.\n+ *\n+ * Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ *\n+ * Neither the name of ARM nor the names of its contributors may be used\n+ * to endorse or promote products derived from this software without specific\n+ * prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <arm_gic.h>\n+#include <assert.h>\n+#include <bl_common.h>\n+#include <console.h>\n+#include <debug.h>\n+#include <mcucfg.h>\n+#include <mmio.h>\n+#include <plat_private.h>\n+#include <platform.h>\n+#include <arch_helpers.h>\n+#include <mtk_sip_svc.h>\n+#include <context_mgmt.h>\n+#include <string.h>\n+#if MTK_RAM_LOG\n+#include <log.h>\n+#endif\n+#include <xlat_tables.h>\n+\n+/*******************************************************************************\n+ * Declarations of linker defined symbols which will help us find the layout\n+ * of trusted SRAM\n+ ******************************************************************************/\n+unsigned long __RO_START__;\n+unsigned long __RO_END__;\n+\n+unsigned long __COHERENT_RAM_START__;\n+unsigned long __COHERENT_RAM_END__;\n+\n+/*\n+ * The next 2 constants identify the extents of the code & RO data region.\n+ * These addresses are used by the MMU setup code and therefore they must be\n+ * page-aligned.  It is the responsibility of the linker script to ensure that\n+ * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.\n+ */\n+#define BL31_RO_BASE (unsigned long)(&__RO_START__)\n+#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)\n+\n+/*\n+ * The next 2 constants identify the extents of the coherent memory region.\n+ * These addresses are used by the MMU setup code and therefore they must be\n+ * page-aligned.  It is the responsibility of the linker script to ensure that\n+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols\n+ * refer to page-aligned addresses.\n+ */\n+#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)\n+#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)\n+\n+/*\n+ * Placeholder variables for copying the arguments that have been passed to\n+ * BL3-1 from BL2.\n+ */\n+static entry_point_info_t bl32_image_ep_info;\n+static entry_point_info_t bl33_image_ep_info;\n+static struct kernel_info k_info;\n+\n+atf_arg_t gteearg;\n+\n+static void platform_setup_cpu(void)\n+{\n+\t/* setup big cores */\n+\tmmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res,\n+\t\tMP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |\n+\t\tMP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |\n+\t\tMP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |\n+\t\tMP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |\n+\t\tMP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);\n+\tmmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS);\n+\tmmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div,\n+\t\tMP1_SW_CG_GEN);\n+\tmmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl,\n+\t\tMP1_L2RSTDISABLE);\n+\n+\t/* set big cores arm64 boot mode */\n+\tmmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg,\n+\t\tMP1_CPUCFG_64BIT);\n+\n+\t/* set LITTLE cores arm64 boot mode */\n+\tmmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw,\n+\t\tMP0_CPUCFG_64BIT);\n+}\n+\n+/*******************************************************************************\n+ * Return a pointer to the 'entry_point_info' structure of the next image for\n+ * the security state specified. BL33 corresponds to the non-secure image type\n+ * while BL32 corresponds to the secure image type. A NULL pointer is returned\n+ * if the image does not exist.\n+ ******************************************************************************/\n+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)\n+{\n+\tentry_point_info_t *next_image_info;\n+\n+\tnext_image_info = (type == NON_SECURE) ?\n+\t\t\t&bl33_image_ep_info : &bl32_image_ep_info;\n+\n+\t/* None of the images on this platform can have 0x0 as the entrypoint */\n+\tif (next_image_info->pc)\n+\t\treturn next_image_info;\n+\telse\n+\t\treturn NULL;\n+}\n+\n+/*******************************************************************************\n+ * Perform any BL3-1 early platform setup. Here is an opportunity to copy\n+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they\n+ * are lost (potentially). This needs to be done before the MMU is initialized\n+ * so that the memory layout can be used while creating page tables.\n+ * BL2 has flushed this information to memory, so we are guaranteed to pick up\n+ * good data.\n+ ******************************************************************************/\n+void bl31_early_platform_setup(bl31_params_t *from_bl2,\n+\t\t\t\t\t\t void *plat_params_from_bl2)\n+{\n+\tmtk_bl_param_t *pmtk_bl_param_t = (mtk_bl_param_t *)from_bl2;\n+\tatf_arg_t_ptr teearg;\n+\n+\t/*\n+\t * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits\n+\t * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit\n+\t * to 64 bit state. So we need to clear high 32bit,\n+\t * which may be random value.\n+\t */\n+\tpmtk_bl_param_t =\n+\t(mtk_bl_param_t *)((uint64_t)pmtk_bl_param_t & 0x00000000ffffffff);\n+\tplat_params_from_bl2 =\n+\t(void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff);\n+\n+\tteearg  = (atf_arg_t_ptr)pmtk_bl_param_t->tee_info_addr;\n+\n+\tconsole_init(teearg->atf_log_port, MT6795_UART_CLOCK, MT6795_BAUDRATE);\n+\tmemcpy((void *)&gteearg, (void *)teearg, sizeof(atf_arg_t));\n+\n+\t/* init system counter in ATF */\n+\tsetup_syscnt();\n+\n+\tVERBOSE(\"bl31_setup\\n\");\n+\n+\tassert(from_bl2 != NULL);\n+\t/* Populate entry point information for BL3-2 and BL3-3 */\n+\tSET_PARAM_HEAD(&bl32_image_ep_info,\n+\t\t\t\tPARAM_EP,\n+\t\t\t\tVERSION_1,\n+\t\t\t\t0);\n+\tSET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);\n+\tbl32_image_ep_info.pc = BL32_BASE;\n+\tbl32_image_ep_info.spsr = plat_get_spsr_for_bl32_entry();\n+\n+\tSET_PARAM_HEAD(&bl33_image_ep_info,\n+\t\t\t\tPARAM_EP,\n+\t\t\t\tVERSION_1,\n+\t\t\t\t0);\n+\t/*\n+\t * Tell BL3-1 where the non-trusted software image\n+\t * is located and the entry state information\n+\t */\n+\t/* BL33_START_ADDRESS */\n+\tbl33_image_ep_info.pc = pmtk_bl_param_t->bl33_start_addr;\n+\tbl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();\n+\tbl33_image_ep_info.args.arg4 =  pmtk_bl_param_t->bootarg_loc;\n+\tbl33_image_ep_info.args.arg5 =  pmtk_bl_param_t->bootarg_size;\n+\tSET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);\n+}\n+/*******************************************************************************\n+ * Perform any BL3-1 platform setup code\n+ ******************************************************************************/\n+\n+const unsigned int mt_irq_sec_array[] = {\n+\tMT_IRQ_SEC_SGI_0,\n+\tMT_IRQ_SEC_SGI_1,\n+\tMT_IRQ_SEC_SGI_2,\n+\tMT_IRQ_SEC_SGI_3,\n+\tMT_IRQ_SEC_SGI_4,\n+\tMT_IRQ_SEC_SGI_5,\n+\tMT_IRQ_SEC_SGI_6,\n+\tMT_IRQ_SEC_SGI_7\n+};\n+\n+void plat_mt_gic_init(void)\n+{\n+\tarm_gic_init(BASE_GICC_BASE,\n+\t\tBASE_GICD_BASE,\n+\t\tBASE_GICR_BASE,\n+\t\tmt_irq_sec_array,\n+\t\tARRAY_SIZE(mt_irq_sec_array));\n+}\n+\n+void bl31_platform_setup(void)\n+{\n+\tplatform_setup_cpu();\n+\n+\tplat_delay_timer_init();\n+\n+\t/* Initialize the gic cpu and distributor interfaces */\n+\tplat_mt_gic_init();\n+\tarm_gic_setup();\n+\n+\t/* Topologies are best known to the platform. */\n+\tmt_setup_topology();\n+}\n+/*******************************************************************************\n+ * Perform the very early platform specific architectural setup here. At the\n+ * moment this is only intializes the mmu in a quick and dirty way.\n+ ******************************************************************************/\n+void bl31_plat_arch_setup(void)\n+{\n+\tatf_arg_t_ptr teearg = &gteearg;\n+\n+\t/* Enable non-secure access to CCI-400 registers */\n+\tmmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET , 0x1);\n+\n+\tplat_cci_init();\n+\tplat_cci_enable();\n+\n+\t{\n+\t\tif (teearg->atf_log_buf_size != 0) {\n+\t\t\tINFO(\"mmap atf buffer : 0x%x, 0x%x\\n\\r\",\n+\t\t\t\t\tteearg->atf_log_buf_start,\n+\t\t\t\t\tteearg->atf_log_buf_size);\n+\n+\t\t\tmmap_add_region(\n+\t\t\t\tteearg->atf_log_buf_start &\n+\t\t\t\t~(PAGE_SIZE_2MB_MASK),\n+\t\t\t\tteearg->atf_log_buf_start &\n+\t\t\t\t~(PAGE_SIZE_2MB_MASK),\n+\t\t\t\tPAGE_SIZE_2MB,\n+\t\t\t\tMT_DEVICE | MT_RW | MT_NS);\n+\n+\t\t\tINFO(\"mmap atf buffer (force 2MB aligned):0x%x, 0x%x\\n\",\n+\t\t\t(teearg->atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)),\n+\t\t\tPAGE_SIZE_2MB);\n+\t\t}\n+\t}\n+\t\t/*\n+\t\t * add TZRAM_BASE to memory map\n+\t\t * then set RO and COHERENT to different attribute\n+\t\t */\n+\t\tplat_configure_mmu_el3(\n+\t\t\tBL31_RO_BASE & ~(PAGE_SIZE_MASK),\n+\t\t\t((TZRAM_SIZE & ~(PAGE_SIZE_MASK)) + PAGE_SIZE),\n+\t\t\t(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),\n+\t\t\tBL31_RO_LIMIT,\n+\t\t\tBL31_COHERENT_RAM_BASE,\n+\t\t\tBL31_COHERENT_RAM_LIMIT);\n+\t/* Initialize for ATF log buffer */\n+\tif (teearg->atf_log_buf_size != 0) {\n+\t\t\tteearg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;\n+\t\t\tteearg->atf_aee_debug_buf_start =\n+\t\t\t\tteearg->atf_log_buf_start +\n+\t\t\t\tteearg->atf_log_buf_size - ATF_AEE_BUFFER_SIZE;\n+#if MTK_RAM_LOG\n+\t\t\tmt_log_setup(teearg->atf_log_buf_start,\n+\t\t\t\tteearg->atf_log_buf_size,\n+\t\t\t\tteearg->atf_aee_debug_buf_size);\n+#endif\n+\t\tINFO(\"ATF log service is registered (0x%x, aee:0x%x)\\n\",\n+\t\t\tteearg->atf_log_buf_start,\n+\t\t\tteearg->atf_aee_debug_buf_start);\n+\t} else{\n+\t\tteearg->atf_aee_debug_buf_size = 0;\n+\t\tteearg->atf_aee_debug_buf_start = 0;\n+\t}\n+\n+\t/*\n+\t * Without this, access to CPUECTRL from NS EL1\n+\t * will cause trap into EL3\n+\t */\n+\tenable_ns_access_to_cpuectlr();\n+\n+\t/* Platform code before bl31_main */\n+\t/* compatible to the earlier chipset */\n+\n+\t/* Show to ATF log buffer & UART */\n+\tINFO(\"BL3-1: %s\\n\", version_string);\n+\tINFO(\"BL3-1: %s\\n\", build_message);\n+\n+}\n+\n+\t\t/* MTK Define */\n+#define ACTLR_CPUECTLR_BIT    (1 << 1)\n+\n+void enable_ns_access_to_cpuectlr(void)\n+{\n+\tunsigned int next_actlr;\n+\n+\n+\t/* ACTLR_EL1 do not implement CUPECTLR  */\n+\tnext_actlr = read_actlr_el2();\n+\tnext_actlr |= ACTLR_CPUECTLR_BIT;\n+\twrite_actlr_el2(next_actlr);\n+\n+\tnext_actlr = read_actlr_el3();\n+\tnext_actlr |= ACTLR_CPUECTLR_BIT;\n+\twrite_actlr_el3(next_actlr);\n+}\n+\n+void save_kernel_info(uint64_t pc,\n+\t\t\tuint64_t r0,\n+\t\t\tuint64_t r1,\n+\t\t\tuint64_t k32_64)\n+{\n+\tk_info.k32_64 = k32_64;\n+\tk_info.pc = pc;\n+\n+\tif (LINUX_KERNEL_32 ==  k32_64) {\n+\t\t\t/* for 32 bits kernel */\n+\t\t\tk_info.r0 = 0;\n+\t\t\tk_info.r1 = r0;   /* machtype */\n+\t\t\tk_info.r2 = r1;   /* tags */\n+\t} else {\n+\t\t\t/* for 64 bits kernel */\n+\t\t\tk_info.r0 = r0;\n+\t\t\tk_info.r1 = r1;\n+\t}\n+}\n+\n+void set_kernel_k32_64(uint64_t k32_64)\n+{\n+\tk_info.k32_64 = k32_64;\n+}\n+\n+uint64_t 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