{"push_id":1173804201,"size":1,"distinct_size":1,"ref":"refs/heads/i965-fp64-gen7-scalar-vec4","head":"bbd5f1dc0bb2a2a40ea40f5db970c689512cf938","before":"011fff2e19a292b9b61ef155a9f402ca4cc9006e","commits":[{"sha":"bbd5f1dc0bb2a2a40ea40f5db970c689512cf938","author":{"name":"Samuel Iglesias Gonsálvez","email":"696499febbb821894b47a781ec89e21f5b31e804@igalia.com"},"message":"MERGE it to i965/vec4: Fix DF UBO loads\n\ni965/vs: fix nir_intrinsic_load_ubo when loading doubles\n\nPreviously the region was gX.2<2,2,1> which spans two registers\nwhile the destination only spans one register. However, there is\na region aligment rule that is not followed.\n\nFrom Haswell PRM vol7, \"Region Alignment Rules for Direct Register\nAddressing\":\n\n\"When an instruction has a source region spanning two registers and a\ndestination region contained in one register the number of elements\nmust be the same between two sources and one of the following must be\ntrue:\na. The destination region is entirely contained in the lower OWord of a\n   register.\nb. The destination region is entirely contained in the upper OWord of a\n   register.\nc. The destination elements are evenly split between the two OWords of a\n   register.\"\n\nDestination region occupies the whole GRF in this case. As we are only\ninterested in picking two values from gX.2, then set the region as\n<0,2,1>.\n\nSigned-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/bbd5f1dc0bb2a2a40ea40f5db970c689512cf938"}]}
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