{"action":"created","issue":{"url":"https://api.github.com/repos/rust-lang/rust/issues/34427","repository_url":"https://api.github.com/repos/rust-lang/rust","labels_url":"https://api.github.com/repos/rust-lang/rust/issues/34427/labels{/name}","comments_url":"https://api.github.com/repos/rust-lang/rust/issues/34427/comments","events_url":"https://api.github.com/repos/rust-lang/rust/issues/34427/events","html_url":"https://github.com/rust-lang/rust/issues/34427","id":161932531,"number":34427,"title":"[MIR] Stage1 `libcore` crashes with SIGILL on ARM","user":{"login":"petevine","id":12054457,"avatar_url":"https://avatars.githubusercontent.com/u/12054457?v=3","gravatar_id":"","url":"https://api.github.com/users/petevine","html_url":"https://github.com/petevine","followers_url":"https://api.github.com/users/petevine/followers","following_url":"https://api.github.com/users/petevine/following{/other_user}","gists_url":"https://api.github.com/users/petevine/gists{/gist_id}","starred_url":"https://api.github.com/users/petevine/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/petevine/subscriptions","organizations_url":"https://api.github.com/users/petevine/orgs","repos_url":"https://api.github.com/users/petevine/repos","events_url":"https://api.github.com/users/petevine/events{/privacy}","received_events_url":"https://api.github.com/users/petevine/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/rust-lang/rust/labels/A-ARM","name":"A-ARM","color":"d7e102"}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":43,"created_at":"2016-06-23T14:10:27Z","updated_at":"2016-08-26T22:50:54Z","closed_at":null,"body":"Since a few days ago, I'm unable to bootstrap rustc on ARM. Stage0 passes ok, but then during `libcore` compilation I'm getting a consistent crash:\r\n\r\n```shell\r\n(gdb) run\r\nStarting program: ../arm-unknown-linux-gnueabihf/stage1/bin/rustc --cfg stage1 -C codegen-units=1 -C target-cpu=cortex-a5 -C target-feature=-neon,-slowfpvmlx -Z orbit -C link-args=-s -O --cfg rtopt -C rpath -C prefer-dynamic --target=arm-unknown-linux-gnueabihf -C target-feature=+v7,+vfp3 -L arm-unknown-linux-gnueabihf/rt -L native=../arm-unknown-linux-gnueabihf/llvm/Release/lib --out-dir arm-unknown-linux-gnueabihf/stage1/lib/rustlib/arm-unknown-linux-gnueabihf/lib -C extra-filename=-fe3cdf61 -C metadata=fe3cdf61 src/libcore/lib.rs\r\n[Thread debugging using libthread_db enabled]\r\nUsing host libthread_db library \"/lib/arm-linux-gnueabihf/libthread_db.so.1\".\r\n[New Thread 0xb23c8280 (LWP 10171)]\r\n\r\nProgram received signal SIGILL, Illegal instruction.\r\n[Switching to Thread 0xb23c8280 (LWP 10171)]\r\n0xb5ccd4c8 in rustc_trans::mir::constant::MirConstContext::new::hfbf8e74461aa3c9a ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n(gdb) bt\r\n#0  0xb5ccd4c8 in rustc_trans::mir::constant::MirConstContext::new::hfbf8e74461aa3c9a ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#1  0xb5cca2bc in rustc_trans::mir::constant::_$LT$impl$u20$mir..MirContext$LT$$u27$bcx$C$$u20$$u27$tcx$GT$$GT$::trans_constant::h0fc06663a5c5fd5c () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#2  0xb5cc97e8 in rustc_trans::mir::operand::_$LT$impl$u20$mir..MirContext$LT$$u27$bcx$C$$u20$$u27$tcx$GT$$GT$::trans_operand::hf76be65ffae28ad3 () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#3  0xb5cda61c in rustc_trans::mir::rvalue::_$LT$impl$u20$mir..MirContext$LT$$u27$bcx$C$$u20$$u27$tcx$GT$$GT$::trans_rvalue_operand::hd939e0a331e9c597 () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#4  0xb5cbff28 in rustc_trans::mir::block::_$LT$impl$u20$mir..MirContext$LT$$u27$bcx$C$$u20$$u27$tcx$GT$$GT$::trans_block::hb1d87007c9e87f30 () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#5  0xb5ba9aa8 in rustc_trans::mir::trans_mir::hf51ccc32c7a8ddd3 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#6  0xb5ba1ff0 in rustc_trans::base::trans_closure::hcb1c30ddf81aba40 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#7  0xb5bab570 in rustc_trans::base::trans_fn::h1508ebeec7351f87 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#8  0xb5bb8950 in rustc_trans::base::trans_item::hd6a260625a685bf2 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#9  0xb5bd3e10 in _$LT$base..TransItemsWithinModVisitor$LT$$u27$a$C$$u20$$u27$tcx$GT$$u20$as$u20$rustc..hir..intravisit..Visitor$LT$$u27$v$GT$$GT$::visit_item::heb661116fa8a1e87 () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#10 0xb5bd2524 in rustc::hir::intravisit::walk_item::hf7ed747a4fa46491 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#11 0xb5bcbbe4 in _$LT$base..TransModVisitor$LT$$u27$a$C$$u20$$u27$tcx$GT$$u20$as$u20$rustc..hir..intravisit..Visitor$LT$$u27$v$GT$$GT$::visit_item::h65d871e71b3668c9 () from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#12 0xb5bbf8ec in rustc_trans::base::trans_crate::hca67d2711539a441 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_trans-fe3cdf61.so\r\n#13 0xb6e06194 in rustc_driver::driver::phase_4_translate_to_llvm::h5f028163cc963293 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\n#14 0xb6e04640 in rustc_driver::driver::compile_input::_$u7b$$u7b$closure$u7d$$u7d$::h540343a1efd859c9 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\n#15 0xb6e10f78 in rustc_driver::driver::phase_3_run_analysis_passes::_$u7b$$u7b$closure$u7d$$u7d$::h0c96940e550f2879 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\n#16 0xb6e16264 in rustc::ty::context::TyCtxt::create_and_enter::h167e75cbc44e6d50 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\n#17 0xb6e0a56c in rustc_driver::driver::phase_3_run_analysis_passes::h75db68819aee0b65 ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\n#18 0xb6dd47b8 in rustc_driver::driver::compile_input::h5e5e4501615d7d4b ()\r\n   from ../arm-unknown-linux-gnueabihf/stage1/lib/librustc_driver-fe3cdf61.so\r\nBacktrace stopped: Cannot access memory at address 0x1d1cfff8\r\n````\r\n```asm\r\n(gdb) disass 0xb5ccd4c8,+1\r\nDump of assembler code from 0xb5ccd4c8 to 0xb5ccd4c9:\r\n=> 0xb5ccd4c8 <_ZN11rustc_trans3mir8constant15MirConstContext3new17hfbf8e74461aa3c9aE+404>:     str     r0, [r0, r8]!\r\n````\r\n\r\nBefore getting that trace I had no idea it was related to MIR in any way. I'll have to give old trans a shot.\r\n\r\n**EDIT:**\r\nYeah, old trans chugs along without a hitch.\r\n"},"comment":{"url":"https://api.github.com/repos/rust-lang/rust/issues/comments/242870545","html_url":"https://github.com/rust-lang/rust/issues/34427#issuecomment-242870545","issue_url":"https://api.github.com/repos/rust-lang/rust/issues/34427","id":242870545,"user":{"login":"eddyb","id":77424,"avatar_url":"https://avatars.githubusercontent.com/u/77424?v=3","gravatar_id":"","url":"https://api.github.com/users/eddyb","html_url":"https://github.com/eddyb","followers_url":"https://api.github.com/users/eddyb/followers","following_url":"https://api.github.com/users/eddyb/following{/other_user}","gists_url":"https://api.github.com/users/eddyb/gists{/gist_id}","starred_url":"https://api.github.com/users/eddyb/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/eddyb/subscriptions","organizations_url":"https://api.github.com/users/eddyb/orgs","repos_url":"https://api.github.com/users/eddyb/repos","events_url":"https://api.github.com/users/eddyb/events{/privacy}","received_events_url":"https://api.github.com/users/eddyb/received_events","type":"User","site_admin":false},"created_at":"2016-08-26T22:50:53Z","updated_at":"2016-08-26T22:50:53Z","body":"Odd, looks like registers are assigined in a way that results in invalid instructions:\r\n```llvm\r\n# *** IR Dump Before Virtual Register Rewriter ***:\r\n# Machine code for function _Z3fooPcS_i: Post SSA\r\nFunction Live Ins: %R0 in %vreg7, %R1 in %vreg8, %R2 in %vreg9\r\n\r\n0B      BB#0: derived from LLVM BB %0\r\n            Live Ins: %R0 %R1 %R2\r\n16B             %vreg9<def> = COPY %R2; GPRnopc:%vreg9\r\n32B             %vreg8<def> = COPY %R1; GPR:%vreg8\r\n48B             %vreg15<def> = COPY %R0; GPR:%vreg15\r\n64B             CMPrr %vreg15, %vreg8, pred:14, pred:%noreg, %CPSR<imp-def>; GPR:%vreg15,%vreg8\r\n80B             Bcc <BB#1>, pred:1, pred:%CPSR<kill>\r\n            Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%)\r\n\r\n96B     BB#4: \r\n            Predecessors according to CFG: BB#0\r\n128B            B <BB#3>\r\n            Successors according to CFG: BB#3(?%)\r\n\r\n144B    BB#1: \r\n            Predecessors according to CFG: BB#0\r\n160B            %vreg4<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg4\r\n            Successors according to CFG: BB#2(?%)\r\n\r\n192B    BB#2: derived from LLVM BB %.lr.ph\r\n            Predecessors according to CFG: BB#2 BB#1\r\n240B            %vreg15<earlyclobber,def,tied2> = STR_PRE_REG %vreg13<undef>, %vreg15<tied0>, %vreg9, 0, pred:14, pred:%noreg; GPR:%vreg15,%vreg13 GPRnopc:%vreg9\r\n256B            STRi12 %vreg4, %vreg15, 4, pred:14, pred:%noreg; mem:ST4[%sunkaddr8+4](tbaa=!4) GPR:%vreg4,%vreg15\r\n272B            CMPrr %vreg8, %vreg15, pred:14, pred:%noreg, %CPSR<imp-def>; GPR:%vreg8,%vreg15\r\n320B            Bcc <BB#2>, pred:1, pred:%CPSR<kill>\r\n336B            B <BB#3>\r\n            Successors according to CFG: BB#3(0x04000000 / 0x80000000 = 3.12%) BB#2(0x7c000000 / 0x80000000 = 96.88%)\r\n\r\n352B    BB#3: derived from LLVM BB %._crit_edge\r\n            Predecessors according to CFG: BB#2 BB#4\r\n384B            %R0<def> = COPY %vreg15; GPR:%vreg15\r\n400B            BX_RET pred:14, pred:%noreg, %R0<imp-use>\r\n\r\n# End machine code for function _Z3fooPcS_i.\r\n\r\n# *** IR Dump After Virtual Register Rewriter ***:\r\n# Machine code for function _Z3fooPcS_i: Post SSA\r\nFunction Live Ins: %R0, %R1, %R2\r\n\r\n0B      BB#0: derived from LLVM BB %0\r\n            Live Ins: %R0 %R1 %R2\r\n64B             CMPrr %R0, %R1, pred:14, pred:%noreg, %CPSR<imp-def>\r\n80B             Bcc <BB#1>, pred:1, pred:%CPSR<kill>\r\n            Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%)\r\n\r\n96B     BB#4: \r\n            Live Ins: %R0\r\n            Predecessors according to CFG: BB#0\r\n128B            B <BB#3>\r\n            Successors according to CFG: BB#3(?%)\r\n\r\n144B    BB#1: \r\n            Live Ins: %R0 %R1 %R2\r\n            Predecessors according to CFG: BB#0\r\n160B            %R3<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg\r\n            Successors according to CFG: BB#2(?%)\r\n\r\n192B    BB#2: derived from LLVM BB %.lr.ph\r\n            Live Ins: %R0 %R1 %R2 %R3\r\n            Predecessors according to CFG: BB#2 BB#1\r\n240B            %R0<earlyclobber,def,tied2> = STR_PRE_REG %R0<undef>, %R0<kill,tied0>, %R2, 0, pred:14, pred:%noreg\r\n256B            STRi12 %R3, %R0, 4, pred:14, pred:%noreg; mem:ST4[%sunkaddr8+4](tbaa=!4)\r\n272B            CMPrr %R1, %R0, pred:14, pred:%noreg, %CPSR<imp-def>\r\n320B            Bcc <BB#2>, pred:1, pred:%CPSR<kill>\r\n336B            B <BB#3>\r\n            Successors according to CFG: BB#3(0x04000000 / 0x80000000 = 3.12%) BB#2(0x7c000000 / 0x80000000 = 96.88%)\r\n\r\n352B    BB#3: derived from LLVM BB %._crit_edge\r\n            Live Ins: %R0\r\n            Predecessors according to CFG: BB#2 BB#4\r\n400B            BX_RET pred:14, pred:%noreg, %R0<imp-use>\r\n\r\n# End machine code for function _Z3fooPcS_i.\r\n```"}}
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