{"push_id":1355310862,"size":4,"distinct_size":4,"ref":"refs/heads/issue-5967","head":"118e7de2a52b363ca8a4628668c76cf0020536fd","before":"34aa13a4c856dd7cd278aecbea1a3770a53c90d3","commits":[{"sha":"90b3b1c8b7e7fe43d4ff5b48799f9388425daa63","author":{"name":"Sven Steinbauer","email":"9d878b831e8ad202268d6003fc179621a34463a2@unlogic.co.uk"},"message":"Error if mov op reg sizes differ\n\nalso add support for 16bit register mov ops","distinct":true,"url":"https://api.github.com/repos/Svenito/radare2/commits/90b3b1c8b7e7fe43d4ff5b48799f9388425daa63"},{"sha":"9b80b736d6362dc292c833788ea6430fb18ff659","author":{"name":"Sven Steinbauer","email":"9d878b831e8ad202268d6003fc179621a34463a2@unlogic.co.uk"},"message":"Improve segment register handling for mov op","distinct":true,"url":"https://api.github.com/repos/Svenito/radare2/commits/9b80b736d6362dc292c833788ea6430fb18ff659"},{"sha":"a85483b2a04296743738034317814096cc91ca29","author":{"name":"Sven Steinbauer","email":"9d878b831e8ad202268d6003fc179621a34463a2@unlogic.co.uk"},"message":"Fix opcode for 64bit instr with 32bits regs","distinct":true,"url":"https://api.github.com/repos/Svenito/radare2/commits/a85483b2a04296743738034317814096cc91ca29"},{"sha":"118e7de2a52b363ca8a4628668c76cf0020536fd","author":{"name":"Sven Steinbauer","email":"9d878b831e8ad202268d6003fc179621a34463a2@unlogic.co.uk"},"message":"Fixing more 64bit related issues","distinct":true,"url":"https://api.github.com/repos/Svenito/radare2/commits/118e7de2a52b363ca8a4628668c76cf0020536fd"}]}
{"actor":{"display_login":"Svenito"}}