{"push_id":964641561,"size":85,"distinct_size":85,"ref":"refs/heads/master","head":"815929bd157503b149d429bc494d1dad92c902e6","before":"18f688d62a69501072d6783bbce34d1a755ef2c9","commits":[{"sha":"141ef75569aa9ffe392f19d7a375bbadebfd08be","author":{"email":"a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com","name":"Jordan Justen"},"message":"i965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONE\n\nGEN8_SURFACE_AUX_MODE_NONE is 0, so this is a no-op.\n\nYet, this also makes it clear that we can compare aux_mode to the\nother GEN8_SURFACE_AUX_MODE_ values. We will want to compare to\nGEN8_SURFACE_AUX_MODE_HIZ.\n\nv2: Some very minor cherry-pick conflicts due to moving it around in the series.\n\nSigned-off-by: Jordan Justen <jordan.l.justen@intel.com>\nReviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>\nReviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>\nSigned-off-by: Ben Widawsky <benjamin.widawsky@intel.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/141ef75569aa9ffe392f19d7a375bbadebfd08be"},{"sha":"848a023c053b312ba5e76a124d7088bbf0b69df0","author":{"email":"7d58aee419d6f9201d75517c885374dff5e7d848@vmware.com","name":"Roland Scheidegger"},"message":"llvmpipe: use scissor_planes_needed helper function\n\nSo it doesn't get out of sync in multiple places.","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/848a023c053b312ba5e76a124d7088bbf0b69df0"},{"sha":"4f598f2173c6555a52aad942ce6ea75c65afe21a","author":{"email":"2cc5244297c0b82e7ea531cc4a868153602775b7@amd.com","name":"Leo Liu"},"message":"vl: add zig zag scan for list 4x4\n\nCc: \"11.0 11.1\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Leo Liu <leo.liu@amd.com>\nReviewed-by: Christian König <christian.koenig@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/4f598f2173c6555a52aad942ce6ea75c65afe21a"},{"sha":"6ad2e55a1405ac3757439dae55ed86425bb65806","author":{"email":"2cc5244297c0b82e7ea531cc4a868153602775b7@amd.com","name":"Leo Liu"},"message":"st/omx/dec/h264: fix corruption when scaling matrix present flag set\n\nThe scaling list should be filled out with zig zag scan\n\nv2: integrate zig zag scan for list 4x4 to vl(Christian)\nv3: move list determination out from the loop(Ilia)\n\nCc: \"11.0 11.1\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Leo Liu <leo.liu@amd.com>\nReviewed-by: Christian König <christian.koenig@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/6ad2e55a1405ac3757439dae55ed86425bb65806"},{"sha":"8b11d8cfbfaaf72755e6c200140e253cb3e3fa8a","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"util/hash_table: add _mesa_hash_table_clear (v4)\n\nv4: coding style change (Matt Turner)\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v3)","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/8b11d8cfbfaaf72755e6c200140e253cb3e3fa8a"},{"sha":"55fb921d691f6d2d9e1ab105adb63a61fea7dc50","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"util/hash_table: add _mesa_hash_table_num_entries\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/55fb921d691f6d2d9e1ab105adb63a61fea7dc50"},{"sha":"54c4a9803bfd59e31bc092229779544b6e636bdf","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"mesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory\n\nWe will want to disable minmax index caching for buffers that are used in this\nway.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/54c4a9803bfd59e31bc092229779544b6e636bdf"},{"sha":"fd7229b4374d7bd8f296e1da4123e0d678d67699","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"mesa/main: add USAGE_PIXEL_PACK_BUFFER flag to buffer UsageHistory\n\nWe will want to disable minmax index caching for buffers that are used in this\nway.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/fd7229b4374d7bd8f296e1da4123e0d678d67699"},{"sha":"46b7a526f551e18a20d07220663652ba011e4fe6","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"mesa/main: bail earlier for size == 0 in _mesa_clear_buffer_sub_data\n\nNote that the conversion of the clear data (when data != NULL) can fail due\nto an out of memory condition, but it does not check any error conditions\nmandated by the spec. Therefore, it is safe to skip when size == 0.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/46b7a526f551e18a20d07220663652ba011e4fe6"},{"sha":"1a570d96a606249ba406da50a61e2eabb88c77ac","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"vbo: move vbo_get_minmax_indices into its own source file\n\nWe will add more code for caching/memoization. Moving the existing code\ninto its own file helps keep things modular.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/1a570d96a606249ba406da50a61e2eabb88c77ac"},{"sha":"6b057f8ecc43be2e190e53599bdd6b8cc96b6f19","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"vbo: cache/memoize the result of vbo_get_minmax_indices (v3)\n\nSome games developers are unaware that an index buffer in a VBO still needs\nto be read by the CPU if some varying data comes from a user pointer (unless\nglDrawRangeElements and friends are used). This is particularly bad when\nthey tell us that the index buffer should live in VRAM.\n\nThis cache helps, e.g. lifting This War Of Mine (a particularly bad\noffender) from under 10fps to slightly over 20fps on a Carrizo.\n\nNote that there is nothing prohibiting a user from rendering from multiple\nthreads simultaneously with the same index buffer, hence the locking. (The\ninternal buffer map taken for the buffer still leads to a race, but at least\nthe locks are a move in the right direction.)\n\nv2: disable the cache on USAGE_TEXTURE_BUFFER as well (Chris Forbes)\n\nv3:\n- use bool instead of GLboolean for MinMaxCacheDirty (Ian Romanick)\n- replace the sticky USAGE_PERSISTENT_WRITE_MAP bit by a direct\n  AccessFlags check\n\nReviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v2)\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/6b057f8ecc43be2e190e53599bdd6b8cc96b6f19"},{"sha":"115c643b1669bd050af8d890adbfc771d9ff8126","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"mesa: add USAGE_DISABLE_MINMAX_CACHE flag to buffer UsageHistory\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/115c643b1669bd050af8d890adbfc771d9ff8126"},{"sha":"761c7d59c4403832c33d931bb097d060ed07e555","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"vbo: disable the minmax cache when the hit rate is low\n\nWhen applications stream their index buffers, the caches for those BOs become\nuseless and add overhead, so we want to disable them. The tricky part is\ncoming up with the right heuristic for *when* to disable them.\n\nThe first question is which hit rate to aim for. Since I'm not aware of any\ninteresting borderline applications that do something like \"draw two or three\ntimes for each upload\", I just kept it simple.\n\nThe second question is how soon we should give up on the caching. Applications\nmight have a warm-up phase where they fill a buffer gradually but then keep\nreusing it. For this reason, I count the number of indices that hit and miss\n(instead of the number of calls that hit or miss), since comparing that to\nthe size of the buffer makes sense.\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/761c7d59c4403832c33d931bb097d060ed07e555"},{"sha":"bc8a6842a95aac4e41d11817f8f05b287f3fea6c","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"mesa: add MESA_NO_MINMAX_CACHE environment variable\n\nWhen set to a truish value, this globally disables the minmax cache for all\nbuffer objects.\n\nNo #ifdef DEBUG guards because this option can be interesting for\nbenchmarking.\n\nReviewed-by: Marek Olšák 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pipe->create_surface can reinterpret a texture\nas a surface with a format of different block width/height (but equal\nblock size).\n\nv2: fix whitespace\n\nReviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/6af6d7b08af5d14b7a5848c87c01ae3c711c7963"},{"sha":"4a448a63adbbece1d9bddacd9428aad7cc68a628","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"st/mesa: use the correct address generation functions in st_TexSubImage blit\n\nWe need to tell the address generation functions about the dimensionality of\nthe texture to correctly implement the part of Section 3.8.1 (Texture Image\nSpecification) of the OpenGL 2.1 specification which says:\n\n    \"For the purposes of decoding the texture image, TexImage2D is\n    equivalent to calling TexImage3D with corresponding arguments\n    and depth of 1, except that\n      ...\n      * UNPACK SKIP IMAGES is ignored.\"\n\nFixes a low impact bug that was found by chance while browsing the spec and\nextending piglit tests.\n\nCc: \"11.0 11.1\" <mesa-stable@lists.freedesktop.org>\nReviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/4a448a63adbbece1d9bddacd9428aad7cc68a628"},{"sha":"757071ca7cdda12d2974614f9a9d02d5a834f38c","author":{"email":"f487c7598f046a9a67757788cf85ee89028a1b14@kde.org","name":"Fredrik Höglund"},"message":"st/mesa: Accelerate PBO uploads\n\nCreate a PIPE_BUFFER sampler view on the pixel-unpack buffer, and draw\nthe image on the texture with a fragment shader that maps fragment\ncoordinates to buffer coordinates.\n\nModifications by Nicolai Hähnle:\n- various cleanups and fixes (e.g. error handling, corner cases)\n- split try_pbo_upload into two functions, which will allow code to be\n  shared with compressed texture uploads\n- modify the source format selection to only test for support against\n  the PIPE_BUFFER target\n\nv2:\n- update handling of TGSI_SEMANTIC_POSITION for recent changes in master\n- MaxTextureBufferSize is number of texels, not bytes (Ilia Mirkin)\n- only enable when integers are supported (Marek Olšák)\n- try harder to hit the TextureBufferOffsetAlignment\n- remove unnecessary MOV from the fragment shader\n\nReviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/757071ca7cdda12d2974614f9a9d02d5a834f38c"},{"sha":"c99f2fe70ec6a9273786d123fa4ac9924b5911b2","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"st/mesa: implement PBO upload for multiple layers\n\nUse instancing to generate two triangles for each destination layer and use\na geometry shader to route the layer index.\n\nv2:\n- directly write layer in VS if supported by the driver (Marek Olšák)\n\nReviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/c99f2fe70ec6a9273786d123fa4ac9924b5911b2"},{"sha":"16c2ea1fcc495580c17a07e3518edffbb5824430","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"st/mesa: inline the implementation of _mesa_store_compressed_teximage\n\nWe will write our own version of texsubimage for PBO uploads, and we will\nwant to call that here as well.\n\nReviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>","distinct":true,"url":"https://api.github.com/repos/tarceri/Mesa_arrays_of_arrays/commits/16c2ea1fcc495580c17a07e3518edffbb5824430"}]}