{"push_id":949170094,"size":975,"distinct_size":5,"ref":"refs/heads/v4.5-next/soc","head":"be29523da38f959799fddceb25d052e498ab625a","before":"21acff361e14ea35bf6170e65b9e1a1c39068b26","commits":[{"sha":"8d3095f4ad47ac409440a0ba1c80e13519ff867d","author":{"email":"5b12a9416e3384398bb726baf00af74a15267cf7@szeredi.hu","name":"Miklos Szeredi"},"message":"ovl: default permissions\n\nAdd mount option \"default_permissions\" to alter the way permissions are\ncalculated.\n\nWithout this option and prior to this patch permissions were calculated by\nunderlying lower or upper filesystem.\n\nWith this option the permissions are calculated by overlayfs based on the\nfile owner, group and mode bits.\n\nThis has significance for example when a read-only exported NFS filesystem\nis used as a lower layer.  In this case the underlying NFS filesystem will\nreply with EROFS, in which case all we know is that the filesystem is\nread-only.  But that's not what we are interested in, we are interested in\nwhether the access would be allowed if the filesystem wasn't read-only; the\nserver doesn't tell us that, and would need updating at various levels,\nwhich doesn't seem practicable.\n\nSigned-off-by: Miklos Szeredi <miklos@szeredi.hu>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/8d3095f4ad47ac409440a0ba1c80e13519ff867d"},{"sha":"0b5da8db145bfd44266ac964a2636a0cf8d7c286","author":{"email":"10460665c63c1e41b922ea2cdf63084aa1a91e2a@redhat.com","name":"Ravishankar N"},"message":"fuse: add support for SEEK_HOLE and SEEK_DATA in lseek\n\nA useful performance improvement for accessing virtual machine images\nvia FUSE mount.\n\nSee https://bugzilla.redhat.com/show_bug.cgi?id=1220173 for a use-case\nfor glusterFS.\n\nSigned-off-by: Ravishankar N <ravishankar@redhat.com>\nSigned-off-by: Miklos Szeredi <miklos@szeredi.hu>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/0b5da8db145bfd44266ac964a2636a0cf8d7c286"},{"sha":"97daf8b97ad6f913a34c82515be64dc9ac08d63e","author":{"email":"5b12a9416e3384398bb726baf00af74a15267cf7@szeredi.hu","name":"Miklos Szeredi"},"message":"ovl: allow zero size xattr\n\nWhen ovl_copy_xattr() encountered a zero size xattr no more xattrs were\ncopied and the function returned success.  This is clearly not the desired\nbehavior.\n\nSigned-off-by: Miklos Szeredi <miklos@szeredi.hu>\nCc: <stable@vger.kernel.org>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/97daf8b97ad6f913a34c82515be64dc9ac08d63e"},{"sha":"e4ad29fa0d224d05e08b2858e65f112fd8edd4fe","author":{"email":"f09eaae3593d4e9e732cdbf62a73c189ff7949e6@coreos.com","name":"Vito Caputo"},"message":"ovl: use a minimal buffer in ovl_copy_xattr\n\nRather than always allocating the high-order XATTR_SIZE_MAX buffer\nwhich is costly and prone to failure, only allocate what is needed and\nrealloc if necessary.\n\nFixes https://github.com/coreos/bugs/issues/489\n\nSigned-off-by: Miklos Szeredi <miklos@szeredi.hu>\nCc: <stable@vger.kernel.org>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/e4ad29fa0d224d05e08b2858e65f112fd8edd4fe"},{"sha":"257f871993474e2bde6c497b54022c362cf398e1","author":{"email":"06fa905d7f2aaced6dc72e9511c71a2a51e8aead@networkplumber.org","name":"Stephen Hemminger"},"message":"ovl: move super block magic number to magic.h\n\nThe overlayfs file system is not recognized by programs\nlike tail because the magic number is not in standard header location.\n\nMove it so that the value will propagate on for the GNU library\nand utilities. Needs to go in the fstatfs manual page as well.\n\nSigned-off-by: Stephen Hemminger <stephen@networkplumber.org>\nSigned-off-by: Miklos Szeredi <miklos@szeredi.hu>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/257f871993474e2bde6c497b54022c362cf398e1"},{"sha":"c7c72c5a127507687c737ede0f97d85bde674433","author":{"email":"f511f818e8a0748edef6b9ee378967da9ed0c78f@linux.vnet.ibm.com","name":"Aneesh Kumar K.V"},"message":"net/9p: Add device name details on error\n\nIf we use wrong device name 9p mount fails with error\n\n\"9pnet_virtio: no channels available\"\n\nImprove the error output as below\n\n\"9pnet_virtio: no channels available for device /dev/root\"\n\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Eric Van Hensbergen <ericvh@gmail.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/c7c72c5a127507687c737ede0f97d85bde674433"},{"sha":"947867aa195b65471f4767fdf761e3841577f90e","author":{"email":"9c69231df81d8a56bd8fc6741579751b95573585@cea.fr","name":"Dominique Martinet"},"message":"9p: trans_fd, read rework to use p9_parse_header\n\nMost of the changes here are no-op and just renaming to use a\nfcall struct, needed for p9_parse_header\n\nIt fixes the unaligned memory access to read the tag and defers to\ncommon functions for part of the protocol knowledge (although header\nlength is still hard-coded...)\n\nReported-By: Rob Landley <rob@landley.net>\nSigned-Off-By: Dominique Martinet <dominique.martinet@cea.fr>\nSigned-off-by: Eric Van Hensbergen <ericvh@gmail.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/947867aa195b65471f4767fdf761e3841577f90e"},{"sha":"3053600ed4f71115631258f0d64eca0d10b11bdc","author":{"email":"9c69231df81d8a56bd8fc6741579751b95573585@cea.fr","name":"Dominique Martinet"},"message":"9p: trans_fd, bail out if recv fcall if missing\n\nreq->rc is pre-allocated early on with p9_tag_alloc and shouldn't be missing\n\nSigned-off-by: Dominique Martinet <dominique.martinet@cea.fr>\nSigned-off-by: Eric Van Hensbergen <ericvh@gmail.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/3053600ed4f71115631258f0d64eca0d10b11bdc"},{"sha":"099a6644f5be438dd63c81ba942e7ffbb2c59099","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"soc/tegra: Provide per-SoC Kconfig symbols\n\nMove per-SoC generation Kconfig symbols to drivers/soc/tegra/Kconfig to\ngather them all in a single place. This directory is a natural location\nfor these options since it already contains the drivers that are shared\nacross 32-bit and 64-bit ARM architectures.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/099a6644f5be438dd63c81ba942e7ffbb2c59099"},{"sha":"9544595262f32f0e6dd6e0170e31ca8582c9cbb0","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"soc/tegra: Add Tegra210 support\n\nAlso known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired\nwith four Cortex-A53 cores in a switched configuration. It features a\nGPU using the Maxwell architecture with support for DX11, SM4, OpenGL\n4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware\naccelerated en- and decoding of various video standards including\nH.265, H.264 and VP8 at 4K resolutions and up to 60 fps.\n\nBesides the multimedia features it also comes with a variety of I/O\ncontrollers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to\nname only a few.\n\nAdd a Kconfig option for Tegra210 to allow SoC-specific support to be\nenabled for this new generation.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/9544595262f32f0e6dd6e0170e31ca8582c9cbb0"},{"sha":"b73c48859895ec32a12ae9670a82c463f280ae35","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"amba: Hide TEGRA_AHB symbol\n\nThe symbol depends on ARCH_TEGRA and will default to y. There are no\ncircumstances under which it is desirable to disable this option.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/b73c48859895ec32a12ae9670a82c463f280ae35"},{"sha":"5883ac2010ef801cb9beb9606d3d50b3dca87113","author":{"email":"cbbc2a491dd609dc667a5c30620606c73351583d@nvidia.com","name":"Jon Hunter"},"message":"ARM: tegra: Ensure entire dcache is flushed on entering LP0/1\n\nTegra support several low-power (LPx) states, which are:\n- LP0: CPU + Core voltage off and DRAM in self-refresh\n- LP1: CPU voltage off and DRAM in self-refresh\n- LP2: CPU voltage off\n\nWhen entering any of the above states the tegra_disable_clean_inv_dcache()\nfunction is called to flush the dcache. The function\ntegra_disable_clean_inv_dcache() will either flush the entire data cache or\nup to the Level of Unification Inner Shareable (LoUIS) depending on the\nvalue in r0. When tegra_disable_clean_inv_dcache() is called by\ntegra20_sleep_core_finish() or tegra30_sleep_core_finish(), to enter LP0\nand LP1 power state, the r0 register contains a physical memory address\nwhich will not be equal to TEGRA_FLUSH_CACHE_ALL (1) and so the data cache\nwill be only flushed to the LoUIS. However, when\ntegra_disable_clean_inv_dcache() called by tegra_sleep_cpu_finish() to\nenter to LP2 power state, r0 is set to TEGRA_FLUSH_CACHE_ALL to flush the\nentire dcache.\n\nPlease note that tegra20_sleep_core_finish(), tegra30_sleep_core_finish()\nand tegra_sleep_cpu_finish() are called by the boot CPU once all other CPUs\nhave been disabled and so it seems appropriate to flush the entire cache at\nthis stage.\n\nTherefore, ensure that r0 is set to TEGRA_FLUSH_CACHE_ALL when calling\ntegra_disable_clean_inv_dcache() from tegra20_sleep_core_finish() and\ntegra30_sleep_core_finish().\n\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\nReviewed-by: Joseph Lo <josephl@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/5883ac2010ef801cb9beb9606d3d50b3dca87113"},{"sha":"a262e87ff354f12447bb6268bd63edf7ba1c20e0","author":{"email":"f2c659f01951776204a6c5b902787d9019fbeebd@arndb.de","name":"Arnd Bergmann"},"message":"ARM: tegra: select USB_ULPI from EHCI rather than platform\n\nFor historic reasons, the tegra platform selects USB_ULPI from architecture\ncode, but that hasn't really made sense for a long time, as the only\nuser of that code is the Tegra EHCI driver that has its own Kconfig\nsymbol.\n\nThis removes the 'select' statements from mach-tegra and drivers/soc/tegra\nand adds them with the device driver that actually needs them.\n\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/a262e87ff354f12447bb6268bd63edf7ba1c20e0"},{"sha":"00ccc34b3e1432bdb4e1892b1eb56898d82db353","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"Merge branch 'for-4.5/clk' into for-4.5/dt","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/00ccc34b3e1432bdb4e1892b1eb56898d82db353"},{"sha":"1d1bac6bbcb771fc685b05d7d32cae6225bb5379","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"Merge branch 'for-4.5/soc' into for-4.5/dt","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/1d1bac6bbcb771fc685b05d7d32cae6225bb5379"},{"sha":"34b4f6d0599e920e0aca34816e5940b418188b03","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"arm64: tegra: Add Tegra132 support\n\nNVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124\nbut with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI\nfile for the SoC, which is mostly similar to the one for Tegra124.\n\nBased on work by Allen Martin <amartin@nvidia.com>\n\nCc: Paul Walmsley <pwalmsley@nvidia.com>\nCc: Allen Martin <amartin@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/34b4f6d0599e920e0aca34816e5940b418188b03"},{"sha":"0f279ebdf3ce5cd3ee23010a46680dca93282e34","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"arm64: tegra: Add NVIDIA Tegra132 Norrin support\n\nNorrin is a Tegra132-based FFD used as reference platform within NVIDIA.\n\nBased on work by Allen Martin <amartin@nvidia.com>\n\nCc: Paul Walmsley <pwalmsley@nvidia.com>\nCc: Allen Martin <amartin@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/0f279ebdf3ce5cd3ee23010a46680dca93282e34"},{"sha":"742af7e7a0a132afe85cc7b8ac82fd20c7b63743","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"arm64: tegra: Add Tegra210 support\n\nAlso known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired\nwith four Cortex-A53 cores in a switched configuration. It features a\nGPU using the Maxwell architecture with support for DX11, SM4, OpenGL\n4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware\naccelerated en- and decoding of various video standards including\nH.265, H.264 and VP8 at 4K resolutions and up to 60 fps.\n\nBesides the multimedia features it also comes with a variety of I/O\ncontrollers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to\nname only a few.\n\nAdd a SoC-level device tree file that describes most of the hardware\navailable on the SoC. This includes only hardware for which a device\ntree binding already exists or which is trivial to describe.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/742af7e7a0a132afe85cc7b8ac82fd20c7b63743"},{"sha":"c552cca31cfdef63182a2114f63d322a9d9bc54f","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"arm64: tegra: Add NVIDIA P2530 main board support\n\nThe NVIDIA P2530 is a processor module used in several reference designs\nthat features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and other\nessentials. It is typically connected to some I/O board that provides\nthe connectors needed to hook it up to the outside world.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/c552cca31cfdef63182a2114f63d322a9d9bc54f"},{"sha":"c24d2e13c6f66ea69adcccd6a74d11de9adfb157","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"arm64: tegra: Add NVIDIA P2595 I/O board support\n\nThe NVIDIA P2595 I/O board is used in several reference designs and has\nthe connectors to connect the P2530 compute module to the outside world.\nIt features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a\nSATA port, an audio codec, a microSD card slot and a display connector,\namong others.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/mbgg/linux-mediatek/commits/c24d2e13c6f66ea69adcccd6a74d11de9adfb157"}]}