{"push_id":1154649635,"size":124,"distinct_size":124,"ref":"refs/heads/linux-4.6.y","head":"536b1f59b9b2be80e5cdc02ca3300d7fe9f44cc1","before":"d3c1ffd75577556662a1e8cac3490a8877f7f557","commits":[{"sha":"0e4c51d2532cc6fd1ff858365e893f2f39aa26b4","author":{"name":"Chao Yu","email":"7390b2c96c78abe47d370032752094fadd04c91d@huawei.com"},"message":"f2fs: fix deadlock when flush inline data\n\ncommit ab47036d8f7227361cad7894adee8e66ab6f95b2 upstream.\n\nBelow backtrace info was reported by Yunlei He:\n\nCall Trace:\n [<ffffffff817a9395>] schedule+0x35/0x80\n [<ffffffff817abb7d>] rwsem_down_read_failed+0xed/0x130\n [<ffffffff813c12a8>] call_rwsem_down_read_failed+0x18/0x\n [<ffffffff817ab1d0>] down_read+0x20/0x30\n [<ffffffffa02a1a12>] f2fs_evict_inode+0x242/0x3a0 [f2fs]\n [<ffffffff81217057>] evict+0xc7/0x1a0\n [<ffffffff81217cd6>] iput+0x196/0x200\n [<ffffffff812134f9>] __dentry_kill+0x179/0x1e0\n [<ffffffff812136f9>] dput+0x199/0x1f0\n [<ffffffff811fe77b>] __fput+0x18b/0x220\n [<ffffffff811fe84e>] ____fput+0xe/0x10\n [<ffffffff81097427>] task_work_run+0x77/0x90\n [<ffffffff81074d62>] exit_to_usermode_loop+0x73/0xa2\n [<ffffffff81003b7a>] do_syscall_64+0xfa/0x110\n [<ffffffff817acf65>] entry_SYSCALL64_slow_path+0x25/0x25\n\nCall Trace:\n [<ffffffff817a9395>] schedule+0x35/0x80\n [<ffffffff81216dc3>] __wait_on_freeing_inode+0xa3/0xd0\n [<ffffffff810bc300>] ? autoremove_wake_function+0x40/0x4\n [<ffffffff8121771d>] find_inode_fast+0x7d/0xb0\n [<ffffffff8121794a>] ilookup+0x6a/0xd0\n [<ffffffffa02bc740>] sync_node_pages+0x210/0x650 [f2fs]\n [<ffffffff8122e690>] ? do_fsync+0x70/0x70\n [<ffffffffa02b085e>] block_operations+0x9e/0xf0 [f2fs]\n [<ffffffff8137b795>] ? bio_endio+0x55/0x60\n [<ffffffffa02b0942>] write_checkpoint+0x92/0xba0 [f2fs]\n [<ffffffff8117da57>] ? mempool_free_slab+0x17/0x20\n [<ffffffff8117de8b>] ? mempool_free+0x2b/0x80\n [<ffffffff8122e690>] ? do_fsync+0x70/0x70\n [<ffffffffa02a53e3>] f2fs_sync_fs+0x63/0xd0 [f2fs]\n [<ffffffff8129630f>] ? ext4_sync_fs+0xbf/0x190\n [<ffffffff8122e6b0>] sync_fs_one_sb+0x20/0x30\n [<ffffffff812002e9>] iterate_supers+0xb9/0x110\n [<ffffffff8122e7b5>] sys_sync+0x55/0x90\n [<ffffffff81003ae9>] do_syscall_64+0x69/0x110\n [<ffffffff817acf65>] entry_SYSCALL64_slow_path+0x25/0x25\n\nWith following excuting serials, we will set inline_node in inode page\nafter inode was unlinked, result in a deadloop described as below:\n1. open file\n2. write file\n3. unlink file\n4. write file\n5. close file\n\nThread A\t\t\t\tThread B\n - dput\n  - iput_final\n   - inode->i_state |= I_FREEING\n   - evict\n    - f2fs_evict_inode\n\t\t\t\t\t - f2fs_sync_fs\n\t\t\t\t\t  - write_checkpoint\n\t\t\t\t\t   - block_operations\n\t\t\t\t\t    - f2fs_lock_all (down_write(cp_rwsem))\n     - f2fs_lock_op (down_read(cp_rwsem))\n\t\t\t\t\t    - sync_node_pages\n\t\t\t\t\t     - ilookup\n\t\t\t\t\t      - find_inode_fast\n\t\t\t\t\t       - __wait_on_freeing_inode\n\t\t\t\t\t         (wait on I_FREEING clear)\n\nHere, we change to set inline_node flag only for linked inode for fixing.\n\nReported-by: Yunlei He <heyunlei@huawei.com>\nSigned-off-by: Chao Yu <yuchao0@huawei.com>\nTested-by: Jaegeuk Kim <jaegeuk@kernel.org>\nSigned-off-by: Jaegeuk Kim <jaegeuk@kernel.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/0e4c51d2532cc6fd1ff858365e893f2f39aa26b4"},{"sha":"2ce206484f16fe353aff89ac890c146cafca1a41","author":{"name":"Leonid Yegoshin","email":"c165e8389c77d27d4341d4e36dd5d4e57f2efc74@imgtec.com"},"message":"MIPS64: R6: R2 emulation bugfix\n\ncommit 41fa29e4d8cf4150568a0fe9bb4d62229f9caed5 upstream.\n\nError recovery pointers for fixups was improperly set as \".word\"\nwhich is unsuitable for MIPS64.\n\nReplaced by STR(PTR)\n\n[ralf@linux-mips.org: Apply changes as requested in the review process.]\n\nSigned-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>\nReviewed-by: James Hogan <james.hogan@imgtec.com>\nReviewed-by: Markos Chandras <markos.chandras@imgtec.com>\nFixes: b0a668fb2038 (\"MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6\")\nCc: macro@linux-mips.org\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/9911/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/2ce206484f16fe353aff89ac890c146cafca1a41"},{"sha":"482a601d4c69eba3900f6ca4f5fa0b7feb0ffb00","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: math-emu: Fix jalr emulation when rd == $0\n\ncommit ab4a92e66741b35ca12f8497896bafbe579c28a1 upstream.\n\nWhen emulating a jalr instruction with rd == $0, the code in\nisBranchInstr was incorrectly writing to GPR $0 which should actually\nalways remain zeroed. This would lead to any further instructions\nemulated which use $0 operating on a bogus value until the task is next\ncontext switched, at which point the value of $0 in the task context\nwould be restored to the correct zero by a store in SAVE_SOME. Fix this\nby not writing to rd if it is $0.\n\nFixes: 102cedc32a6e (\"MIPS: microMIPS: Floating point support.\")\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Maciej W. Rozycki <macro@imgtec.com>\nCc: James Hogan <james.hogan@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/13160/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/482a601d4c69eba3900f6ca4f5fa0b7feb0ffb00"},{"sha":"0ea534fb90a014e7c39225a825be44bef69a1301","author":{"name":"Maciej W. Rozycki","email":"006a10158a5aec37e39763a69b0658f4e7f13280@imgtec.com"},"message":"MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC\n\ncommit e49d38488515057dba8f0c2ba4cfde5be4a7281f upstream.\n\nFix a build regression from commit c9017757c532 (\"MIPS: init upper 64b\nof vector registers when MSA is first used\"):\n\narch/mips/built-in.o: In function `enable_restore_fp_context':\ntraps.c:(.text+0xbb90): undefined reference to `_init_msa_upper'\ntraps.c:(.text+0xbb90): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper'\ntraps.c:(.text+0xbef0): undefined reference to `_init_msa_upper'\ntraps.c:(.text+0xbef0): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper'\n\nto !CONFIG_CPU_HAS_MSA configurations with older GCC versions, which are\nunable to figure out that calls to `_init_msa_upper' are indeed dead.\nOf the many ways to tackle this failure choose the approach we have\nalready taken in `thread_msa_context_live'.\n\n[ralf@linux-mips.org: Drop patch segment to junk file.]\n\nSigned-off-by: Maciej W. Rozycki <macro@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/13271/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/0ea534fb90a014e7c39225a825be44bef69a1301"},{"sha":"f77518651e31b961809cd0fa5f2b6f12af6cc1c5","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Don't unwind to user mode with EVA\n\ncommit a816b306c62195b7c43c92cb13330821a96bdc27 upstream.\n\nWhen unwinding through IRQs and exceptions, the unwinding only continues\nif the PC is a kernel text address, however since EVA it is possible for\nuser and kernel address ranges to overlap, potentially allowing\nunwinding to continue to user mode if the user PC happens to be in the\nkernel text address range.\n\nAdjust the check to also ensure that the register state from before the\nexception is actually running in kernel mode, i.e. !user_mode(regs).\n\nI don't believe any harm can come of this problem, since the PC is only\noutput, the stack pointer is checked to ensure it resides within the\ntask's stack page before it is dereferenced in search of the return\naddress, and the return address register is similarly only output (if\nthe PC is in a leaf function or the beginning of a non-leaf function).\n\nHowever unwind_stack() is only meant for unwinding kernel code, so to be\ncorrect the unwind should stop there.\n\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nReviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11700/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/f77518651e31b961809cd0fa5f2b6f12af6cc1c5"},{"sha":"fd03fca280b377adea93eed19fb6bc3d26ee596a","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Avoid using unwind_stack() with usermode\n\ncommit 81a76d7119f63c359750e4adeff922a31ad1135f upstream.\n\nWhen showing backtraces in response to traps, for example crashes and\naddress errors (usually unaligned accesses) when they are set in debugfs\nto be reported, unwind_stack will be used if the PC was in the kernel\ntext address range. However since EVA it is possible for user and kernel\naddress ranges to overlap, and even without EVA userland can still\ntrigger an address error by jumping to a KSeg0 address.\n\nAdjust the check to also ensure that it was running in kernel mode. I\ndon't believe any harm can come of this problem, since unwind_stack() is\nsufficiently defensive, however it is only meant for unwinding kernel\ncode, so to be correct it should use the raw backtracing instead.\n\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nReviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11701/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\n(cherry picked from commit d2941a975ac745c607dfb590e92bb30bc352dad9)\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/fd03fca280b377adea93eed19fb6bc3d26ee596a"},{"sha":"5cff029679bce51bd181f54c93a8533177d66fd8","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Fix siginfo.h to use strict posix types\n\ncommit 5daebc477da4dfeb31ae193d83084def58fd2697 upstream.\n\nCommit 85efde6f4e0d (\"make exported headers use strict posix types\")\nchanged the asm-generic siginfo.h to use the __kernel_* types, and\ncommit 3a471cbc081b (\"remove __KERNEL_STRICT_NAMES\") make the internal\ntypes accessible only to the kernel, but the MIPS implementation hasn't\nbeen updated to match.\n\nSwitch to proper types now so that the exported asm/siginfo.h won't\nproduce quite so many compiler errors when included alone by a user\nprogram.\n\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Christopher Ferris <cferris@google.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/12477/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/5cff029679bce51bd181f54c93a8533177d66fd8"},{"sha":"2dfc57bd1228a926ac9489d90e1d21d6be0738c6","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Fix uapi include in exported asm/siginfo.h\n\ncommit 987e5b834467c9251ca584febda65ef8f66351a9 upstream.\n\nSince commit 8cb48fe169dd (\"MIPS: Provide correct siginfo_t.si_stime\"),\nMIPS' uapi/asm/siginfo.h has included uapi/asm-generic/siginfo.h\ndirectly before defining MIPS' struct siginfo, in order to get the\nnecessary definitions needed for the siginfo struct without the generic\ncopy_siginfo() hitting compiler errors due to struct siginfo not yet\nbeing defined.\n\nNow that the generic copy_siginfo() is moved out to linux/signal.h we\ncan safely include asm-generic/siginfo.h before defining the MIPS\nspecific struct siginfo, which avoids the uapi/ include as well as\nbreakage due to generic copy_siginfo() being defined before struct\nsiginfo.\n\nReported-by: Christopher Ferris <cferris@google.com>\nFixes: 8cb48fe169dd (\"MIPS: Provide correct siginfo_t.si_stime\")\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Petr Malat <oss@malat.biz>\nCc: linux-mips@linux-mips.org\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/2dfc57bd1228a926ac9489d90e1d21d6be0738c6"},{"sha":"a82fdd38d226913e5b0113582b40b8b75c81e3b2","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Fix watchpoint restoration\n\ncommit a7e89326b415b5d81c4b1016fd4a40db861eb58d upstream.\n\nCommit f51246efee2b (\"MIPS: Get rid of finish_arch_switch().\") moved the\n__restore_watch() call from finish_arch_switch() (i.e. after resume()\nreturns) to before the resume() call in switch_to(). This results in\nwatchpoints only being restored when a task is descheduled, preventing\nthe watchpoints from being effective most of the time, except due to\nchance before the watchpoints are lazily removed.\n\nFix the call sequence from switch_to() through to\nmips_install_watch_registers() to pass the task_struct pointer of the\nnext task, instead of using current. This allows the watchpoints for the\nnext (non-current) task to be restored without reintroducing\nfinish_arch_switch().\n\nFixes: f51246efee2b (\"MIPS: Get rid of finish_arch_switch().\")\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/12726/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/a82fdd38d226913e5b0113582b40b8b75c81e3b2"},{"sha":"7b35229a6d6458c5b2a424470ff1280378d33192","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Flush highmem pages in __flush_dcache_page\n\ncommit 234859e49a15323cf1b2331bdde7f658c4cb45fb upstream.\n\nWhen flush_dcache_page is called on an executable page, that page is\nabout to be provided to userland & we can presume that the icache\ncontains no valid entries for its address range. However if the icache\ndoes not fill from the dcache then we cannot presume that the pages\ncontent has been written back as far as the memories that the dcache\nwill fill from (ie. L2 or further out).\n\nThis was being done for lowmem pages, but not for highmem which can lead\nto icache corruption. Fix this by mapping highmem pages & flushing their\ncontent from the dcache in __flush_dcache_page before providing the page\nto userland, just as is done for lowmem pages.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Lars Persson <lars.persson@axis.com>\nCc: Andrew Morton <akpm@linux-foundation.org>\nCc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/12720/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/7b35229a6d6458c5b2a424470ff1280378d33192"},{"sha":"f497b77b0e907a752b11546337099150db7e1786","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Handle highmem pages in __update_cache\n\ncommit f4281bba818105c7c91799abe40bc05c0dbdaa25 upstream.\n\nThe following patch will expose __update_cache to highmem pages. Handle\nthem by mapping them in for the duration of the cache maintenance, just\nlike in __flush_dcache_page. The code for that isn't shared because we\nneed the page address in __update_cache so sharing became messy. Given\nthat the entirity is an extra 5 lines, just duplicate it.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Lars Persson <lars.persson@axis.com>\nCc: Andrew Morton <akpm@linux-foundation.org>\nCc: Jerome Marchand <jmarchan@redhat.com>\nCc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/12721/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/f497b77b0e907a752b11546337099150db7e1786"},{"sha":"404cb7fb23d3f6a1dd7ccc3f2df9d80a96d92355","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Sync icache & dcache in set_pte_at\n\ncommit 37d22a0d798b5c938b277d32cfd86dc231381342 upstream.\n\nIt's possible for pages to become visible prior to update_mmu_cache\nrunning if a thread within the same address space preempts the current\nthread or runs simultaneously on another CPU. That is, the following\nscenario is possible:\n\n    CPU0                            CPU1\n\n    write to page\n    flush_dcache_page\n    flush_icache_page\n    set_pte_at\n                                    map page\n    update_mmu_cache\n\nIf CPU1 maps the page in between CPU0's set_pte_at, which marks it valid\n& visible, and update_mmu_cache where the dcache flush occurs then CPU1s\nicache will fill from stale data (unless it fills from the dcache, in\nwhich case all is good, but most MIPS CPUs don't have this property).\nCommit 4d46a67a3eb8 (\"MIPS: Fix race condition in lazy cache flushing.\")\nattempted to fix that by performing the dcache flush in\nflush_icache_page such that it occurs before the set_pte_at call makes\nthe page visible. However it has the problem that not all code that\nwrites to pages exposed to userland call flush_icache_page. There are\nmany callers of set_pte_at under mm/ and only 2 of them do call\nflush_icache_page. Thus the race window between a page becoming visible\n& being coherent between the icache & dcache remains open in some cases.\n\nTo illustrate some of the cases, a WARN was added to __update_cache with\nthis patch applied that triggered in cases where a page about to be\nflushed from the dcache was not the last page provided to\nflush_icache_page. That is, backtraces were obtained for cases in which\nthe race window is left open without this patch. The 2 standout examples\nfollow.\n\nWhen forking a process:\n\n[   15.271842] [<80417630>] __update_cache+0xcc/0x188\n[   15.277274] [<80530394>] copy_page_range+0x56c/0x6ac\n[   15.282861] [<8042936c>] copy_process.part.54+0xd40/0x17ac\n[   15.289028] [<80429f80>] do_fork+0xe4/0x420\n[   15.293747] [<80413808>] handle_sys+0x128/0x14c\n\nWhen exec'ing an ELF binary:\n\n[   14.445964] [<80417630>] __update_cache+0xcc/0x188\n[   14.451369] [<80538d88>] move_page_tables+0x414/0x498\n[   14.457075] [<8055d848>] setup_arg_pages+0x220/0x318\n[   14.462685] [<805b0f38>] load_elf_binary+0x530/0x12a0\n[   14.468374] [<8055ec3c>] search_binary_handler+0xbc/0x214\n[   14.474444] [<8055f6c0>] do_execveat_common+0x43c/0x67c\n[   14.480324] [<8055f938>] do_execve+0x38/0x44\n[   14.485137] [<80413808>] handle_sys+0x128/0x14c\n\nThese code paths write into a page, call flush_dcache_page then call\nset_pte_at without flush_icache_page inbetween. The end result is that\nthe icache can become corrupted & userland processes may execute\nunexpected or invalid code, typically resulting in a reserved\ninstruction exception, a trap or a segfault.\n\nFix this race condition fully by performing any cache maintenance\nrequired to keep the icache & dcache in sync in set_pte_at, before the\npage is made valid. This has the added bonus of ensuring the cache\nmaintenance always happens in one location, rather than being duplicated\nin flush_icache_page & update_mmu_cache. It also matches the way other\narchitectures solve the same problem (see arm, ia64 & powerpc).\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nReported-by: Ionela Voinescu <ionela.voinescu@imgtec.com>\nCc: Lars Persson <lars.persson@axis.com>\nFixes: 4d46a67a3eb8 (\"MIPS: Fix race condition in lazy cache flushing.\")\nCc: Steven J. Hill <sjhill@realitydiluted.com>\nCc: David Daney <david.daney@cavium.com>\nCc: Huacai Chen <chenhc@lemote.com>\nCc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nCc: Andrew Morton <akpm@linux-foundation.org>\nCc: Jerome Marchand <jmarchan@redhat.com>\nCc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/12722/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/404cb7fb23d3f6a1dd7ccc3f2df9d80a96d92355"},{"sha":"599eacdcc7fb5539dc36c2f5219d3da8ae7fd0b3","author":{"name":"Huacai Chen","email":"9d0d2ac0186c70d2f0f61b72cb4fe11060be1605@lemote.com"},"message":"MIPS: Loongson-3: Fix build error after ld-version.sh modification\n\ncommit 820880cdba0137baff6cc0e828c3c418c363ae44 upstream.\n\nCommit d5ece1cb074b2c (\"Fix ld-version.sh to handle large 3rd version\npart\") modifies the ld version description. This causes a build error\non Loongson-3, so fix it.\n\nSigned-off-by: Huacai Chen <chenhc@lemote.com>\nCc: Aurelien Jarno <aurelien@aurel32.net>\nCc: Steven J . Hill <sjhill@realitydiluted.com>\nCc: Fuxin Zhang <zhangfx@lemote.com>\nCc: Zhangjin Wu <wuzhangjin@gmail.com>\nCc: Huacai Chen <chenhc@lemote.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/12890/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/599eacdcc7fb5539dc36c2f5219d3da8ae7fd0b3"},{"sha":"5bc4ddc789664910d5e599d35091901fbb4279e4","author":{"name":"Matthias Schiffer","email":"e0fc9444507b5e43a86498c2a43a0d7ed39b4462@universe-factory.net"},"message":"MIPS: ath79: make bootconsole wait for both THRE and TEMT\n\ncommit f5b556c94c8490d42fea79d7b4ae0ecbc291e69d upstream.\n\nThis makes the ath79 bootconsole behave the same way as the generic 8250\nbootconsole.\n\nAlso waiting for TEMT (transmit buffer is empty) instead of just THRE\n(transmit buffer is not full) ensures that all characters have been\ntransmitted before the real serial driver starts reconfiguring the serial\ncontroller (which would sometimes result in garbage being transmitted.)\nThis change does not cause a visible performance loss.\n\nIn addition, this seems to fix a hang observed in certain configurations on\nmany AR7xxx/AR9xxx SoCs during autoconfig of the real serial driver.\n\nA more complete follow-up patch will disable 8250 autoconfig for ath79\naltogether (the serial controller is detected as a 16550A, which is not\nfully compatible with the ath79 serial, and the autoconfig may lead to\nundefined behavior on ath79.)\n\nSigned-off-by: Matthias Schiffer <mschiffer@universe-factory.net>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/5bc4ddc789664910d5e599d35091901fbb4279e4"},{"sha":"ed58c916ae90af0e8e6156435c09dad18051f88c","author":{"name":"Huacai Chen","email":"9d0d2ac0186c70d2f0f61b72cb4fe11060be1605@lemote.com"},"message":"MIPS: Reserve nosave data for hibernation\n\ncommit a95d069204e178f18476f5499abab0d0d9cbc32c upstream.\n\nAfter commit 92923ca3aacef63c92d (\"mm: meminit: only set page reserved\nin the memblock region\"), the MIPS hibernation is broken. Because pages\nin nosave data section should be \"reserved\", but currently they aren't\nset to \"reserved\" at initialization. This patch makes hibernation work\nagain.\n\nSigned-off-by: Huacai Chen <chenhc@lemote.com>\nCc: Aurelien Jarno <aurelien@aurel32.net>\nCc: Steven J . Hill <sjhill@realitydiluted.com>\nCc: Fuxin Zhang <zhangfx@lemote.com>\nCc: Zhangjin Wu <wuzhangjin@gmail.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/12888/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/ed58c916ae90af0e8e6156435c09dad18051f88c"},{"sha":"990a6023ee81c91ed333dfccef03843fe2b73ceb","author":{"name":"Huacai Chen","email":"9d0d2ac0186c70d2f0f61b72cb4fe11060be1605@lemote.com"},"message":"MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPU\n\ncommit 3484de7bcbed20ecbf2b8d80671619e7059e2dd7 upstream.\n\nDue to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is\nnot enough for RS780E integrated GPU's TOM (top of memory) registers\nand MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB\nbelow 4GB).\n\nSigned-off-by: Huacai Chen <chenhc@lemote.com>\nCc: Aurelien Jarno <aurelien@aurel32.net>\nCc: Steven J . Hill <sjhill@realitydiluted.com>\nCc: Fuxin Zhang <zhangfx@lemote.com>\nCc: Zhangjin Wu <wuzhangjin@gmail.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/12889/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/990a6023ee81c91ed333dfccef03843fe2b73ceb"},{"sha":"c841b82e735c2784e29b4472afb52c06433403c7","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Use copy_s.fmt rather than copy_u.fmt\n\ncommit 8a3c8b48aca8771bff3536e40aa26ffb311699d1 upstream.\n\nIn revision 1.12 of the MSA specification, the copy_u.w instruction has\nbeen removed for MIPS32 & the copy_u.d instruction has been removed for\nMIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will\ncomplain about this like so:\n\narch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this\nprocessor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]'\n\nSince we always copy to the width of a GPR, simply use copy_s instead of\ncopy_u to fix this.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/13061/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/c841b82e735c2784e29b4472afb52c06433403c7"},{"sha":"bab73d27b323eb9db1e4b54a393f4f97ceb593bc","author":{"name":"James Hogan","email":"00935fde11ed589f6e5a2cfc70182e355d2baa37@imgtec.com"},"message":"MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDU\n\ncommit ea1688573426adc2587ed52d086b51c7c62eaca3 upstream.\n\nThe MSA ld_*/st_* assembler macros for when the toolchain doesn't\nsupport MSA use addu to offset the base address. However it is a virtual\nmemory pointer so fix it to use PTR_ADDU which expands to daddu for\n64-bit kernels.\n\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/13062/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/bab73d27b323eb9db1e4b54a393f4f97ceb593bc"},{"sha":"2f8a8e57f9ed9044b9890521744a19ea7a215d1f","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Force CPUs to lose FP context during mode switches\n\ncommit 6b8322576e9d325b65c54fbef64e4e8690ad70ce upstream.\n\nCommit 9791554b45a2 (\"MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options\nfor MIPS\") added support for the PR_SET_FP_MODE prctl, which allows a\nuserland program to modify its FP mode at runtime. This is most notably\nrequired if dynamic linking leads to the FP mode requirement changing at\nruntime from that indicated in the initial executable's ELF header. In\norder to avoid overhead in the general FP context restore code, it aimed\nto have threads in the process become unable to enable the FPU during a\nmode switch & have the thread calling the prctl syscall wait for all\nother threads in the process to be context switched at least once. Once\nthat happens we can know that no thread in the process whose mode will\nbe switched has live FP context, and it's safe to perform the mode\nswitch. However in the (rare) case of modeswitches occurring in\nmultithreaded programs this can lead to indeterminate delays for the\nthread invoking the prctl syscall, and the code monitoring for those\ncontext switches was woefully inadequate for all but the simplest cases.\n\nFix this by broadcasting an IPI if other CPUs may have live FP context\nfor an affected thread, with a handler causing those CPUs to relinquish\ntheir FPU ownership. Threads will then be allowed to continue running\nbut will stall on the wait_on_atomic_t in enable_restore_fp_context if\nthey attempt to use FP again whilst the mode switch is still in\nprogress. The end result is less fragile poking at scheduler context\nswitch counts & a more expedient completion of the mode switch.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nFixes: 9791554b45a2 (\"MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS\")\nReviewed-by: Maciej W. Rozycki <macro@imgtec.com>\nCc: Adam Buchbinder <adam.buchbinder@gmail.com>\nCc: James Hogan <james.hogan@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/13145/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/2f8a8e57f9ed9044b9890521744a19ea7a215d1f"},{"sha":"d1692853620495e30f7af687a917d61a2d3efe81","author":{"name":"Paul Burton","email":"6cf344976ede6e423f0f16c3121262bddc8fed82@imgtec.com"},"message":"MIPS: Prevent \"restoration\" of MSA context in non-MSA kernels\n\ncommit 6533af4d4831c421cd9aa4dce7cfc19a3514cc09 upstream.\n\nIf a kernel doesn't support MSA context (ie. CONFIG_CPU_HAS_MSA=n) then\nit will only keep 64 bits per FP register in thread context, and the\ncalls to set_fpr64 in restore_msa_extcontext will overrun the end of the\nFP register context into the FCSR & MSACSR values. GCC 6.x has become\nsmart enough to detect this & complain like so:\n\n    arch/mips/kernel/signal.c: In function 'protected_restore_fp_context':\n    ./arch/mips/include/asm/processor.h:114:17: error: array subscript is above array bounds [-Werror=array-bounds]\n      fpr->val##width[FPR_IDX(width, idx)] = val;   \\\n      ~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~\n    ./arch/mips/include/asm/processor.h:118:1: note: in expansion of macro 'BUILD_FPR_ACCESS'\n     BUILD_FPR_ACCESS(64)\n\nThe only way to trigger this code to run would be for a program to set\nup an artificial extended MSA context structure following a sigframe &\nexecute sigreturn. Whilst this doesn't allow a program to write to any\nstate that it couldn't already, it makes little sense to allow this\n\"restoration\" of MSA context in a system that doesn't support MSA.\n\nFix this by killing a program with SIGSYS if it tries something as crazy\nas \"restoring\" fake MSA context in this way, also fixing the build error\n& allowing for most of restore_msa_extcontext to be optimised out of\nkernels without support for MSA.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nReported-by: Michal Toman <michal.toman@imgtec.com>\nFixes: bf82cb30c7e5 (\"MIPS: Save MSA extended context around signals\")\nTested-by: Aaro Koskinen <aaro.koskinen@iki.fi>\nCc: James Hogan <james.hogan@imgtec.com>\nCc: Michal Toman <michal.toman@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/13164/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/lfd/PreemptRT/commits/d1692853620495e30f7af687a917d61a2d3efe81"}]}
{"actor":{"display_login":"rralf"}}