{"action":"closed","issue":{"url":"https://api.github.com/repos/dotnet/coreclr/issues/8460","repository_url":"https://api.github.com/repos/dotnet/coreclr","labels_url":"https://api.github.com/repos/dotnet/coreclr/issues/8460/labels{/name}","comments_url":"https://api.github.com/repos/dotnet/coreclr/issues/8460/comments","events_url":"https://api.github.com/repos/dotnet/coreclr/issues/8460/events","html_url":"https://github.com/dotnet/coreclr/issues/8460","id":193591627,"number":8460,"title":"RyuJIT: Bad codegen while short circuiting compare against zero involving a shift operation","user":{"login":"sivarv","id":11184808,"avatar_url":"https://avatars.githubusercontent.com/u/11184808?v=3","gravatar_id":"","url":"https://api.github.com/users/sivarv","html_url":"https://github.com/sivarv","followers_url":"https://api.github.com/users/sivarv/followers","following_url":"https://api.github.com/users/sivarv/following{/other_user}","gists_url":"https://api.github.com/users/sivarv/gists{/gist_id}","starred_url":"https://api.github.com/users/sivarv/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sivarv/subscriptions","organizations_url":"https://api.github.com/users/sivarv/orgs","repos_url":"https://api.github.com/users/sivarv/repos","events_url":"https://api.github.com/users/sivarv/events{/privacy}","received_events_url":"https://api.github.com/users/sivarv/received_events","type":"User","site_admin":false},"labels":[{"id":196940911,"url":"https://api.github.com/repos/dotnet/coreclr/labels/area-CodeGen","name":"area-CodeGen","color":"d4c5f9","default":false},{"id":172143003,"url":"https://api.github.com/repos/dotnet/coreclr/labels/bug","name":"bug","color":"1d76db","default":true}],"state":"closed","locked":false,"assignee":{"login":"sivarv","id":11184808,"avatar_url":"https://avatars.githubusercontent.com/u/11184808?v=3","gravatar_id":"","url":"https://api.github.com/users/sivarv","html_url":"https://github.com/sivarv","followers_url":"https://api.github.com/users/sivarv/followers","following_url":"https://api.github.com/users/sivarv/following{/other_user}","gists_url":"https://api.github.com/users/sivarv/gists{/gist_id}","starred_url":"https://api.github.com/users/sivarv/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sivarv/subscriptions","organizations_url":"https://api.github.com/users/sivarv/orgs","repos_url":"https://api.github.com/users/sivarv/repos","events_url":"https://api.github.com/users/sivarv/events{/privacy}","received_events_url":"https://api.github.com/users/sivarv/received_events","type":"User","site_admin":false},"assignees":[{"login":"sivarv","id":11184808,"avatar_url":"https://avatars.githubusercontent.com/u/11184808?v=3","gravatar_id":"","url":"https://api.github.com/users/sivarv","html_url":"https://github.com/sivarv","followers_url":"https://api.github.com/users/sivarv/followers","following_url":"https://api.github.com/users/sivarv/following{/other_user}","gists_url":"https://api.github.com/users/sivarv/gists{/gist_id}","starred_url":"https://api.github.com/users/sivarv/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sivarv/subscriptions","organizations_url":"https://api.github.com/users/sivarv/orgs","repos_url":"https://api.github.com/users/sivarv/repos","events_url":"https://api.github.com/users/sivarv/events{/privacy}","received_events_url":"https://api.github.com/users/sivarv/received_events","type":"User","site_admin":false}],"milestone":null,"comments":0,"created_at":"2016-12-05T19:43:58Z","updated_at":"2016-12-06T00:28:38Z","closed_at":"2016-12-06T00:28:38Z","body":"Repro program:\r\n\r\n```\r\n           // Absolute bits\r\n            int bitCount = 0;\r\n            while ((0 != (100 >> bitCount)) && (31 > bitCount))\r\n            {\r\n                bitCount++;\r\n            }\r\n            // Sign bit\r\n            bitCount++;\r\n```\r\n\r\nHere is the generated code on RyuJIT amd64:\r\n\r\n```\r\n            // Absolute bits\r\n            int bitCount = 0;\r\n00007FFF91B743E0  xor         ecx,ecx  \r\n00007FFF91B743E2  mov         dword ptr [rbp+34h],ecx  \r\n00007FFF91B743E5  nop  \r\n00007FFF91B743E6  jmp         00007FFF91B743F2  \r\n            {\r\n00007FFF91B743E8  nop  \r\n                bitCount++;\r\n00007FFF91B743E9  mov         eax,dword ptr [rbp+34h]  \r\n00007FFF91B743EC  inc         eax  \r\n00007FFF91B743EE  mov         dword ptr [rbp+34h],eax  \r\n            }\r\n00007FFF91B743F1  nop  \r\n            while ((0 != (100 >> bitCount)) && (31 > bitCount))\r\n00007FFF91B743F2  mov         ecx,dword ptr [rbp+34h]  \r\n00007FFF91B743F5  and         ecx,1Fh  \r\n00007FFF91B743F8  mov         eax,64h  \r\n00007FFF91B743FD  sar         eax,cl  \r\n00007FFF91B743FF  je          00007FFF91B74412  \r\n00007FFF91B74401  mov         eax,dword ptr [rbp+34h]  \r\n\r\n```\r\n\r\nSAL/SAR/SHL/SHR do not modify flags if the shift count is zero. In the above repro, the very first iteration through the loop attempts a shift-right by zero and doesn't execute loop body."}}
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