{"push_id":1050407760,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"14341afcfcb81fa4ee5ea9e38596d59bbaef36c7","before":"b6c01ffbf517baa5a9a91cc3281fd91013b806df","commits":[{"sha":"14341afcfcb81fa4ee5ea9e38596d59bbaef36c7","author":{"email":"97e77871b5fcc4941bebceb4338c97c1fd149f8c@FreeBSD.org","name":"avg"},"message":"new x86 smp topology detection code\n\nPreviously, the code determined a topology of processing units\n(hardware threads, cores, packages) and then deduced a cache topology\nusing certain assumptions.  The new code builds a topology that\nincludes both processing units and caches using the information\nprovided by the hardware.\n\nAt the moment, the discovered full topology is used only to creeate\na scheduling topology for SCHED_ULE.\nThere is no KPI for other kernel uses.\n\nSummary:\n- based on APIC ID derivation rules for Intel and AMD CPUs\n- can handle non-uniform topologies\n- requires homogeneous APIC ID assignment (same bit widths for ID\n  components)\n- topology for dual-node AMD CPUs may not be optimal\n- topology for latest AMD CPU models may not be optimal as the code is\n  several years old\n- supports only thread/package/core/cache nodes\n\nTodo:\n  - AMD dual-node processors\n  - latest AMD processors\n  - NUMA nodes\n  - checking for homogeneity of the APIC ID assignment across packages\n  - more flexible cache placement within topology\n  - expose topology to userland, e.g., via sysctl nodes\n\nLong term todo:\n  - KPI for CPU sharing and affinity with respect to various resources\n    (e.g., two logical processors may share the same FPU, etc)\n\nReviewed by:\tmav\nTested by:\tmav\nMFC after:\t1 month\nDifferential Revision:\thttps://reviews.freebsd.org/D2728","distinct":true,"url":"https://api.github.com/repos/bsd-hacker/freebsd/commits/14341afcfcb81fa4ee5ea9e38596d59bbaef36c7"}]}