{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/190","repository_url":"https://api.github.com/repos/ucb-bar/rocket-chip","labels_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/190/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/190/comments","events_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/190/events","html_url":"https://github.com/ucb-bar/rocket-chip/pull/190","id":169264075,"number":190,"title":"Add asynchronous FIFOs as an option for clock domain crossings.","user":{"login":"ben-k","id":2288633,"avatar_url":"https://avatars.githubusercontent.com/u/2288633?v=3","gravatar_id":"","url":"https://api.github.com/users/ben-k","html_url":"https://github.com/ben-k","followers_url":"https://api.github.com/users/ben-k/followers","following_url":"https://api.github.com/users/ben-k/following{/other_user}","gists_url":"https://api.github.com/users/ben-k/gists{/gist_id}","starred_url":"https://api.github.com/users/ben-k/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ben-k/subscriptions","organizations_url":"https://api.github.com/users/ben-k/orgs","repos_url":"https://api.github.com/users/ben-k/repos","events_url":"https://api.github.com/users/ben-k/events{/privacy}","received_events_url":"https://api.github.com/users/ben-k/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":{"login":"terpstra","id":1101706,"avatar_url":"https://avatars.githubusercontent.com/u/1101706?v=3","gravatar_id":"","url":"https://api.github.com/users/terpstra","html_url":"https://github.com/terpstra","followers_url":"https://api.github.com/users/terpstra/followers","following_url":"https://api.github.com/users/terpstra/following{/other_user}","gists_url":"https://api.github.com/users/terpstra/gists{/gist_id}","starred_url":"https://api.github.com/users/terpstra/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/terpstra/subscriptions","organizations_url":"https://api.github.com/users/terpstra/orgs","repos_url":"https://api.github.com/users/terpstra/repos","events_url":"https://api.github.com/users/terpstra/events{/privacy}","received_events_url":"https://api.github.com/users/terpstra/received_events","type":"User","site_admin":false},"assignees":[{"login":"terpstra","id":1101706,"avatar_url":"https://avatars.githubusercontent.com/u/1101706?v=3","gravatar_id":"","url":"https://api.github.com/users/terpstra","html_url":"https://github.com/terpstra","followers_url":"https://api.github.com/users/terpstra/followers","following_url":"https://api.github.com/users/terpstra/following{/other_user}","gists_url":"https://api.github.com/users/terpstra/gists{/gist_id}","starred_url":"https://api.github.com/users/terpstra/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/terpstra/subscriptions","organizations_url":"https://api.github.com/users/terpstra/orgs","repos_url":"https://api.github.com/users/terpstra/repos","events_url":"https://api.github.com/users/terpstra/events{/privacy}","received_events_url":"https://api.github.com/users/terpstra/received_events","type":"User","site_admin":false}],"milestone":null,"comments":3,"created_at":"2016-08-04T00:20:19Z","updated_at":"2016-08-04T01:37:17Z","closed_at":null,"pull_request":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/pulls/190","html_url":"https://github.com/ucb-bar/rocket-chip/pull/190","diff_url":"https://github.com/ucb-bar/rocket-chip/pull/190.diff","patch_url":"https://github.com/ucb-bar/rocket-chip/pull/190.patch"},"body":"This extends AsyncDecoupledTo and AsyncDecoupledFrom to instantiate\r\nasync fifos if requested by setting depth > 0.  The modules use\r\nthe standard technique of gray-coding the read and write pointers\r\nfor synchronization, and are ported from verilog implementations\r\npreviously used for this purpose.\r\n\r\nNote that only FIFO depths which are powers of 2 are supported."},"comment":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/comments/237426615","html_url":"https://github.com/ucb-bar/rocket-chip/pull/190#issuecomment-237426615","issue_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/190","id":237426615,"user":{"login":"terpstra","id":1101706,"avatar_url":"https://avatars.githubusercontent.com/u/1101706?v=3","gravatar_id":"","url":"https://api.github.com/users/terpstra","html_url":"https://github.com/terpstra","followers_url":"https://api.github.com/users/terpstra/followers","following_url":"https://api.github.com/users/terpstra/following{/other_user}","gists_url":"https://api.github.com/users/terpstra/gists{/gist_id}","starred_url":"https://api.github.com/users/terpstra/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/terpstra/subscriptions","organizations_url":"https://api.github.com/users/terpstra/orgs","repos_url":"https://api.github.com/users/terpstra/repos","events_url":"https://api.github.com/users/terpstra/events{/privacy}","received_events_url":"https://api.github.com/users/terpstra/received_events","type":"User","site_admin":false},"created_at":"2016-08-04T01:37:17Z","updated_at":"2016-08-04T01:37:17Z","body":"On Wed, Aug 3, 2016 at 6:08 PM, Ben Keller <notifications@github.com> wrote:\n\n> I don't have a good sense of the intended use of Mem vs. SeqMem when it\n> comes to SRAM mapping - my (apparently incorrect) understanding was that\n> only SeqMem would map to SRAMs as in Chisel2.\n>\nI believe that the intent is that they could both potentially be turned\ninto an SRAM in an ASIC.\nBoth can already be inferred as a block memory by FPGA tools from the\nverilog output by chisel3 today.\n\n> This use case should be safe if the memory is implemented in flip-flops as\n> the pointer synchronization latency guards against any ill-timed reads. (It\n> seems like a dual-ported SRAM should also be safe to use, but I haven't\n> though that case through carefully.)\n>\n> I agree that it is logically safe. However, depending on how the SRAM is\nimplemented, it may not be safe to connect it to two clock domains...\n(analog crap)\n\n> If the Mem were coded as a Vec of Reg, the intent not to map into an SRAM\n> would be clear. Would that be an acceptable solution?\n>\nSadly, no. It might be safe on an ASIC, but on an FPGA it is generally\nnever safe to take inputs from two clock domains through a LUT. Using a\nVec(Reg) would require a mux that takes the index from one clock domain and\nthe registers from another clock domain. I wrote the Handshake version for\nour VC707 board to cross between PCIe and rocket, so this matters to me.\n\nMem and SeqMem just need a way for us to be explicit about our\nrequirements. Once we have that, we'll merge some sort of ASyncFifo.\nFortunately, the users of the From/To API don't need to care about what is\nunder the hood. At some point it will just get faster.\n"}}
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