{"push_id":1008251468,"size":2,"distinct_size":2,"ref":"refs/heads/chisel3","head":"417565332484b2094e1518449b3cb2d80eafb0bf","before":"767be080fc5da1a2b6c27c62578d82a53828676f","commits":[{"sha":"a5a23b6c16a64ce14ebc15908d91ce5f69d5236a","author":{"email":"f895a446007886599f05b907ec63884fb0b638cd@eecs.berkeley.edu","name":"Palmer Dabbelt"},"message":"Avoid generating 0-width UInts\n\nChisel3 requires a 1-bit width to represent UInt(0).","distinct":true,"url":"https://api.github.com/repos/ucb-bar/uncore/commits/a5a23b6c16a64ce14ebc15908d91ce5f69d5236a"},{"sha":"417565332484b2094e1518449b3cb2d80eafb0bf","author":{"email":"f895a446007886599f05b907ec63884fb0b638cd@eecs.berkeley.edu","name":"Palmer Dabbelt"},"message":"Avoid right-shift by larger that the bit width\n\nFIRRTL bails out on this.  There's an outstanding bug, this is just a\nworkaround.  See https://github.com/ucb-bar/firrtl/issues/69","distinct":true,"url":"https://api.github.com/repos/ucb-bar/uncore/commits/417565332484b2094e1518449b3cb2d80eafb0bf"}]}