{"push_id":920182826,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"87648cf13bbc525864d22b4d348c3b35e7952f1f","before":"57e1e5781ffe14303322aee66b8e1541ec3a5569","commits":[{"sha":"87648cf13bbc525864d22b4d348c3b35e7952f1f","author":{"email":"6725196cdacf457761c04b49051a768498322a6e@ieee.org","name":"Eldon Nelson"},"message":"expand strategy pattern to have a checking bits","distinct":true,"url":"https://api.github.com/repos/tenthousandfailures/systemverilog-design-patterns/commits/87648cf13bbc525864d22b4d348c3b35e7952f1f"}]}