{"action":"reopened","issue":{"url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/217","repository_url":"https://api.github.com/repos/UCSBarchlab/PyRTL","labels_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/217/labels{/name}","comments_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/217/comments","events_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/217/events","html_url":"https://github.com/UCSBarchlab/PyRTL/issues/217","id":170552966,"number":217,"title":"Add Support for RAM Initial Contents","user":{"login":"masoug","id":468384,"avatar_url":"https://avatars.githubusercontent.com/u/468384?v=3","gravatar_id":"","url":"https://api.github.com/users/masoug","html_url":"https://github.com/masoug","followers_url":"https://api.github.com/users/masoug/followers","following_url":"https://api.github.com/users/masoug/following{/other_user}","gists_url":"https://api.github.com/users/masoug/gists{/gist_id}","starred_url":"https://api.github.com/users/masoug/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/masoug/subscriptions","organizations_url":"https://api.github.com/users/masoug/orgs","repos_url":"https://api.github.com/users/masoug/repos","events_url":"https://api.github.com/users/masoug/events{/privacy}","received_events_url":"https://api.github.com/users/masoug/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2016-08-11T01:11:23Z","updated_at":"2016-08-11T01:36:18Z","closed_at":null,"body":"http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf page 145 shows how to pre-load memory. This feature should be incorporated into PyRTL's verilog output feature so users who have predefined memory in their PyRTL code can easily transfer it to an FPGA."}}
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