{"push_id":980333001,"size":3,"distinct_size":3,"ref":"refs/heads/master","head":"545a3d0c58c03992b58f3c254acc67205c5c4ed0","before":"8c84165a765fd3511643d3897d8624b31ffca7bb","commits":[{"sha":"78b7290c06d35789c8c8cd11230f77316c0f74e1","author":{"email":"2591e5f46f28d303f9dc027d475a5c60d8dea17a@chalkie.org.uk","name":"chalkie666"},"message":"fix linux and apple priism install path\n\nto fit instructions in top level CMakeLists.txt\n\nSigned-off-by: chalkie666 <dan@chalie.org.uk>","distinct":true,"url":"https://api.github.com/repos/iandobbie/CUDA_SIMrecon/commits/78b7290c06d35789c8c8cd11230f77316c0f74e1"},{"sha":"be39edf29839b2aeeec1dcdcfacc61f66e2c1ad6","author":{"email":"2591e5f46f28d303f9dc027d475a5c60d8dea17a@chalkie.org.uk","name":"chalkie666"},"message":"Add maxwell GPU compute capability 5.0 support to nvcc compiler flags\n\nSigned-off-by: chalkie666 <dan@chalkie.org.uk>","distinct":true,"url":"https://api.github.com/repos/iandobbie/CUDA_SIMrecon/commits/be39edf29839b2aeeec1dcdcfacc61f66e2c1ad6"},{"sha":"545a3d0c58c03992b58f3c254acc67205c5c4ed0","author":{"email":"67183d570cfeb82be10a47d013e2ebe9332c5385@bioch.ox.ac.uk","name":"Ian Dobbie"},"message":"Merge pull request #2 from chalkie666/master\n\nEnables GPU compute capability 5.0 for Maxwell based GPUs","distinct":true,"url":"https://api.github.com/repos/iandobbie/CUDA_SIMrecon/commits/545a3d0c58c03992b58f3c254acc67205c5c4ed0"}]}