{"push_id":1412155349,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"2720b390d8dd15c71a0f8c850ba4fbea3acf13b2","before":"0dcef331ade646f917a51d602178807f39b094aa","commits":[{"sha":"2720b390d8dd15c71a0f8c850ba4fbea3acf13b2","author":{"name":"Sergey Kvachonok","email":"fd3b194fc948303633da241d7483c2c552d0b12a@gmail.com"},"message":"parser: Change generic and port list syntax.\n\nReasons: readability, parseability.\n\nReserve <> and () delimiters for the positional generic and\nport assignments.\nThose will use commas instead of semicolons as separators.\n\nIn the future, short statements like\n\n    put Csmall<100e-9>(vdd, gnd);\n\nequilavent to\n\n    put Csmall\n    generic {\n        capacitance := 100e-9;\n    }\n    port {\n        pos == vdd;\n        neg == gnd;\n    };\n\nwill be supported.\n\nSwitch to more VHDL-like \"generic { }\" and \"port { }\" for both\ndeclarations and named assignments.\n\nDisambiguating named and positional assignments within\nthe same kind of block wouldn't be easy when arbitrary wire and\ngeneric expressions are allowed in the future.","distinct":true,"url":"https://api.github.com/repos/ravenexp/dhdl/commits/2720b390d8dd15c71a0f8c850ba4fbea3acf13b2"}]}
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