{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel3/issues/352","repository_url":"https://api.github.com/repos/ucb-bar/chisel3","labels_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/352/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/352/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/352/events","html_url":"https://github.com/ucb-bar/chisel3/issues/352","id":187795828,"number":352,"title":"Cannot use vector of registers in sequential mux circuit","user":{"login":"edwardcwang","id":10752510,"avatar_url":"https://avatars.githubusercontent.com/u/10752510?v=3","gravatar_id":"","url":"https://api.github.com/users/edwardcwang","html_url":"https://github.com/edwardcwang","followers_url":"https://api.github.com/users/edwardcwang/followers","following_url":"https://api.github.com/users/edwardcwang/following{/other_user}","gists_url":"https://api.github.com/users/edwardcwang/gists{/gist_id}","starred_url":"https://api.github.com/users/edwardcwang/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/edwardcwang/subscriptions","organizations_url":"https://api.github.com/users/edwardcwang/orgs","repos_url":"https://api.github.com/users/edwardcwang/repos","events_url":"https://api.github.com/users/edwardcwang/events{/privacy}","received_events_url":"https://api.github.com/users/edwardcwang/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":5,"created_at":"2016-11-07T18:51:36Z","updated_at":"2016-11-08T22:24:55Z","closed_at":null,"body":"I get a \"Expression key already in stack\" error using Vec.fill(n) or Seq.fill(n) or \"Not bound to synthesizable node, currently only Type description\" error with Vec(Reg()) construct. Code is at the bottom of this issue. @chick\r\n\r\nWith `val num_ones = Vec(Seq.fill(n)(Reg(init=UInt(0, width = 32))))` or `val num_ones = Vec.fill(n){Reg(init=UInt(0, width = 32))}`\r\n\r\n[info]   firrtl_interpreter.InterpreterException: Expression key num_ones_0 already in stack\r\n[info]   at firrtl_interpreter.ExpressionExecutionStack$$anonfun$push$1.apply(ExpressionExecutionStack.scala:42)\r\n[info]   at firrtl_interpreter.ExpressionExecutionStack$$anonfun$push$1.apply(ExpressionExecutionStack.scala:36)\r\n[info]   at scala.Option.foreach(Option.scala:257)\r\n[info]   at firrtl_interpreter.ExpressionExecutionStack.push(ExpressionExecutionStack.scala:36)\r\n[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.evaluate(LoFirrtlExpressionEvaluator.scala:273)\r\n[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator$$anonfun$4.apply(LoFirrtlExpressionEvaluator.scala:429)\r\n[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator$$anonfun$4.apply(LoFirrtlExpressionEvaluator.scala:424)\r\n[info]   at firrtl_interpreter.Timer.apply(Timer.scala:40)\r\n[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.firrtl_interpreter$LoFirrtlExpressionEvaluator$$resolveDependency(LoFirrtlExpressionEvaluator.scala:423)\r\n[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.getValue(LoFirrtlExpressionEvaluator.scala:81)\r\n\r\n\r\nWith: `val num_ones = Vec(n, Reg(init=UInt(0, width = 32)))`\r\n\r\n[info]   chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@28): Not bound to synthesizable node, currently only Type description\r\n[info]   at chisel3.core.Binding$.checkSynthesizable(Binding.scala:185)\r\n[info]   at chisel3.core.Bits.binop(Bits.scala:159)\r\n[info]   at chisel3.core.UInt.do_$plus$amp(Bits.scala:438)\r\n[info]   at chisel3.core.UInt.do_$plus$percent(Bits.scala:440)\r\n[info]   at chisel3.core.UInt.do_$plus(Bits.scala:420)\r\n[info]   at utils.Debouncer$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcVI$sp(Debouncer.scala:46)\r\n[info]   at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:166)\r\n[info]   at utils.Debouncer$$anonfun$1.apply$mcV$sp(Debouncer.scala:45)\r\n[info]   at chisel3.core.WhenContext.<init>(When.scala:57)\r\n[info]   at chisel3.core.when$.apply(When.scala:31)\r\n\r\nDebouncer.scala: https://gist.github.com/edwardcwang/2cc08f26b37e7aafa0f67b71f9b27623\r\n\r\nDebouncerUnitTest.scala: https://gist.github.com/edwardcwang/ec662f80040f935390155c1a0cd9ea8e\r\n"},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel3/issues/comments/259278911","html_url":"https://github.com/ucb-bar/chisel3/issues/352#issuecomment-259278911","issue_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/352","id":259278911,"user":{"login":"edwardcwang","id":10752510,"avatar_url":"https://avatars.githubusercontent.com/u/10752510?v=3","gravatar_id":"","url":"https://api.github.com/users/edwardcwang","html_url":"https://github.com/edwardcwang","followers_url":"https://api.github.com/users/edwardcwang/followers","following_url":"https://api.github.com/users/edwardcwang/following{/other_user}","gists_url":"https://api.github.com/users/edwardcwang/gists{/gist_id}","starred_url":"https://api.github.com/users/edwardcwang/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/edwardcwang/subscriptions","organizations_url":"https://api.github.com/users/edwardcwang/orgs","repos_url":"https://api.github.com/users/edwardcwang/repos","events_url":"https://api.github.com/users/edwardcwang/events{/privacy}","received_events_url":"https://api.github.com/users/edwardcwang/received_events","type":"User","site_admin":false},"created_at":"2016-11-08T22:24:55Z","updated_at":"2016-11-08T22:24:55Z","body":"@chick @ucbjrl Yes, I can confirm that all three of the following variants that put Vec inside Reg don't have the error.\r\n\r\n```\r\nval num_ones = Reg(init = Vec(n, UInt(width=32)).fromBits(0.U)) // nominally preferred\r\nval num_ones = Reg(init = Vec.fill(n)(UInt(0, width=32)))\r\nval num_ones = Reg(Vec(n, UInt(width=32)), init = Vec(Seq.fill(n)(UInt(0))))\r\n```\r\n"}}
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