{"push_id":1478713149,"size":1,"distinct_size":1,"ref":"refs/heads/opp-2016.12-upstream","head":"769d9d6f08eb07ed0be509317a4d2a5fb745cc2d","before":"a5ab22733ba369a45d29abc7e638245e20d463ec","commits":[{"sha":"769d9d6f08eb07ed0be509317a4d2a5fb745cc2d","author":{"name":"Marcin Wojtas","email":"f4a1372cb6d8ecfe0dfc5ddb877a236a745cf429@semihalf.com"},"message":"SdMmc/XenonDxe: Fix HS200 operation\n\n* Set HS_ENABLE bit in HostCtrl1\n* Do not disable clock when switching to HS200 mode\n* Fix HS200 UHS mode value in HostCtrl2 register\n\nTODO: Add optional 1.8V modes setting via PCD.\n\nSigned-off-by: Marcin Wojtas <mw@semihalf.com>","distinct":true,"url":"https://api.github.com/repos/MarvellEmbeddedProcessors/edk2-open-platform/commits/769d9d6f08eb07ed0be509317a4d2a5fb745cc2d"}]}
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