{"push_id":1098607823,"size":368,"distinct_size":368,"ref":"refs/heads/wip/rib/i915-perf-tests","head":"d0babb722781993257d13a197769425d6da0fe1a","before":"b6d58b6ec561bbef4d8466de50b45a86129515de","commits":[{"sha":"e3b68bb66683ad4cb4c80df904a3a21c98a2b6c2","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"lib: Share common __gem_execbuf()\n\nAn oft-repeated function to check EXECBUFFER2 for a particular fail\ncondition.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/e3b68bb66683ad4cb4c80df904a3a21c98a2b6c2"},{"sha":"b7f150b606bc27199a007dab8d248d9510967173","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"lib: Query the kernel for support of a particular exec id\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/b7f150b606bc27199a007dab8d248d9510967173"},{"sha":"04f5215f00962f746c5bd1aa7bdbcaf62280f235","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"Extract array of execution engines\n\nA few tests wish to execute on every engine, so centralise the array of\nknown engines.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/04f5215f00962f746c5bd1aa7bdbcaf62280f235"},{"sha":"01acd70762a17df2f889d4b6a4161c3540a8ce00","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt: Add gem_exec_basic\n\nExtremely basic check that we can dispatch an execbuf on every ring.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/01acd70762a17df2f889d4b6a4161c3540a8ce00"},{"sha":"b09ef449af3ad8dcb0af19c48d716104ce18d76e","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_storedw_loop: Use common array of rings\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/b09ef449af3ad8dcb0af19c48d716104ce18d76e"},{"sha":"7e0853c9c717f8e1ce6ed7f0d2fa6bd973bd0f6a","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_exec_nop: Use common array of rings\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/7e0853c9c717f8e1ce6ed7f0d2fa6bd973bd0f6a"},{"sha":"8cd52893346c647e475e801c5f5267f2f2b75ebe","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_cs_tlb: Use common array of rings\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/8cd52893346c647e475e801c5f5267f2f2b75ebe"},{"sha":"dd6b45235b5f1eea9b37e686460fdf1a1c56f431","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_ringfill: Use common array of rings\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/dd6b45235b5f1eea9b37e686460fdf1a1c56f431"},{"sha":"d1308990842fec5f523c129951a5c649d817be81","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_sync: Use common array of rings\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/d1308990842fec5f523c129951a5c649d817be81"},{"sha":"de70769cc0a24d4d594aaa4c1f99b4a3fc8f05fe","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"Add I915_EXEC_DEFAULT to list of known engines\n\nI dropped this from the list of rings for some tests when refactoring to\na common array. Almost all of the tests should be run over the default\nexec engine to ensure ABI backwards compatiblity.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/de70769cc0a24d4d594aaa4c1f99b4a3fc8f05fe"},{"sha":"5dea5deffc31e833a7cff1f70d29e49a5152fd3e","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_cs_prefetch: Check each ring\n\nSince each engine has its own ring, each is subject to CS prefetching\nand has its own layout that needs probing.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/5dea5deffc31e833a7cff1f70d29e49a5152fd3e"},{"sha":"37f4da0d981f7990e9183be2eab2197d092fb701","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_concurrent_all: Pass buffer data down\n\nIn order reduce the number of parameters being passed everywhere, whilst\nsimultaneously making more information available to the lower levels,\npass the struct buffers around.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/37f4da0d981f7990e9183be2eab2197d092fb701"},{"sha":"a1b47ef6ae6b92be4de0cf87f1ad2ee84029f8b7","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_concurrent_blit: Disable libdrm buffer cache for child inheritance\n\nIt just ends up with buffer leaks all over. On the flip side, it does\nallow us to inherit the bufmgr directly without worry of stomping over\nthe aliased entries (and causing double closes).\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/a1b47ef6ae6b92be4de0cf87f1ad2ee84029f8b7"},{"sha":"d18d1eca811fff9871bb619558aee48568fc1b4d","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_reset_stats: Convert residual calllers of gem_exec() to gem_execbuf()\n\nMissed from e3b68bb66683ad4cb4c80df904a3a21c98a2b6c2 due to rebasing\nfun.\n\ngem_reset_stats.c: In function 'inject_hang_ring':\ngem_reset_stats.c:227:19: error: implicit declaration of function 'gem_exec' [-Werror=implicit-function-declaration]\ngem_reset_stats.c:227:2: warning: nested extern declaration of 'gem_exec' [-Wnested-externs]\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/d18d1eca811fff9871bb619558aee48568fc1b4d"},{"sha":"506d683da138a7b90f5e338d522012f00d3145e9","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"tests: Add gem_exec_reloc\n\nThe first steps towards basic relocation handling. In today's edition,\nwe ask how well does the kernel fare if we pass it relocations via\nmmappings of our buffer objects.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/506d683da138a7b90f5e338d522012f00d3145e9"},{"sha":"eaa03678b00179da89f194113c0740c033857c1c","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"lib: Hide BSD1/BSD2 rings on hardware without BSD2\n\nThe kernel happily lets us run on I915_EXEC_BSD2 even with such hardware\nexisting. Sigh.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/eaa03678b00179da89f194113c0740c033857c1c"},{"sha":"3ec8b1d28e8d5ac924bd8f2e28baa31445bc5279","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_ringfill: Set MI_MEM_VIRTUAL flag for gen<6\n\nbit22 of MI_STORE_DWORD is confusing as the meaning changed between\nphysical/virtual addressing in early gen and GTT/ppGTT in later gen. It\nlooks like gen4 and gen5 still need the flag.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/3ec8b1d28e8d5ac924bd8f2e28baa31445bc5279"},{"sha":"89f81e039636c1fe8a4df846c769bbab7de609dc","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt: More MI_STORE_DWORD fixes for gen5\n\nA few other tests I have updated recently to use MI_STORE_DWORD also need\nthe magic bit for gen4/5.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/89f81e039636c1fe8a4df846c769bbab7de609dc"},{"sha":"d63e72f0ad281f295b058a572741b995a5a0f64a","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"igt/gem_cs_tlb: Increase BB start alignment to 64bytes\n\nIronlake requires 64byte alignment for its MI_BATCH_BUFFER_START.\n\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/d63e72f0ad281f295b058a572741b995a5a0f64a"},{"sha":"be6f3fadaf2c45972f7a9830baa6fd35f4d755a6","author":{"email":"cc0e04a2103c45cd195651d976f79813d0f66bdf@intel.com","name":"Paulo Zanoni"},"message":"lib/igt_fb: make the automatic buffer sizes/strides smaller\n\nThe big motivation behind this patch is that the current power-of-two\ngranularity from igt_fb is way too big. There was more than one\noccasion where I had to work around this problem on\nkms_frontbuffer_tracking, and during my last workaround I was\nrequested to just make igt_fb use more minimal buffers.\n\nI also need to export the size computation function so I won't need to\nreimplement it inside kms_frontbuffer_tracking.\n\nv2:\n - Fix the Yf sizes (Ville).\n - Don't change the Gen 2/3 behavior for both tiled and non-tiled.\nv3:\n - Edit the commit message, clarify that v1 was wrongly treating gen\n   2/3 non-tiled as tiled (Chris).\n\nRequested-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nSigned-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>","distinct":true,"url":"https://api.github.com/repos/rib/intel-gpu-tools/commits/be6f3fadaf2c45972f7a9830baa6fd35f4d755a6"}]}