{"action":"created","issue":{"url":"https://api.github.com/repos/m-labs/sinara/issues/131","repository_url":"https://api.github.com/repos/m-labs/sinara","labels_url":"https://api.github.com/repos/m-labs/sinara/issues/131/labels{/name}","comments_url":"https://api.github.com/repos/m-labs/sinara/issues/131/comments","events_url":"https://api.github.com/repos/m-labs/sinara/issues/131/events","html_url":"https://github.com/m-labs/sinara/issues/131","id":195948630,"number":131,"title":"expected timeline 0.1 -> 0.2 -> 1.0 ","user":{"login":"jbqubit","id":20543958,"avatar_url":"https://avatars.githubusercontent.com/u/20543958?v=3","gravatar_id":"","url":"https://api.github.com/users/jbqubit","html_url":"https://github.com/jbqubit","followers_url":"https://api.github.com/users/jbqubit/followers","following_url":"https://api.github.com/users/jbqubit/following{/other_user}","gists_url":"https://api.github.com/users/jbqubit/gists{/gist_id}","starred_url":"https://api.github.com/users/jbqubit/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jbqubit/subscriptions","organizations_url":"https://api.github.com/users/jbqubit/orgs","repos_url":"https://api.github.com/users/jbqubit/repos","events_url":"https://api.github.com/users/jbqubit/events{/privacy}","received_events_url":"https://api.github.com/users/jbqubit/received_events","type":"User","site_admin":false},"labels":[{"id":470831020,"url":"https://api.github.com/repos/m-labs/sinara/labels/area:admin","name":"area:admin","color":"fef2c0","default":false}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":{"url":"https://api.github.com/repos/m-labs/sinara/milestones/2","html_url":"https://github.com/m-labs/sinara/milestone/2","labels_url":"https://api.github.com/repos/m-labs/sinara/milestones/2/labels","id":2029125,"number":2,"title":"0.1 delivery","description":"PCBs that comprise prototype round 0.1. Delivery to scientists after testing by WUT. \r\n- [ ] PCB_Metlino\r\n- [ ] PCB_Sayma_AMC\r\n- [ ] PCB_Sayma_RTM\r\n- [ ] PCB_mezzanine_analog_allaki","creator":{"login":"jordens","id":1338946,"avatar_url":"https://avatars.githubusercontent.com/u/1338946?v=3","gravatar_id":"","url":"https://api.github.com/users/jordens","html_url":"https://github.com/jordens","followers_url":"https://api.github.com/users/jordens/followers","following_url":"https://api.github.com/users/jordens/following{/other_user}","gists_url":"https://api.github.com/users/jordens/gists{/gist_id}","starred_url":"https://api.github.com/users/jordens/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jordens/subscriptions","organizations_url":"https://api.github.com/users/jordens/orgs","repos_url":"https://api.github.com/users/jordens/repos","events_url":"https://api.github.com/users/jordens/events{/privacy}","received_events_url":"https://api.github.com/users/jordens/received_events","type":"User","site_admin":false},"open_issues":4,"closed_issues":7,"state":"open","created_at":"2016-09-26T14:58:58Z","updated_at":"2016-12-15T23:59:46Z","due_on":"2017-01-10T00:00:00Z","closed_at":null},"comments":3,"created_at":"2016-12-15T23:59:46Z","updated_at":"2016-12-16T14:17:39Z","closed_at":null,"body":"In #97 @hartytp  asks\r\n\r\n> Assuming we don't find any major mistakes in the prototype hardware, when do you think a second hardware order will take place? This will affect how much prototype hardware we buy.\r\n\r\n- [ ] @gkasprow Please predict date when the BOM and layout will be frozen.\r\n\r\n- [ ] @sbourdeauducq Please comment on status of ARTIQ support for Sinara hardware.\r\n\r\n# v0.1 \r\nFrom date order is placed with board house... \r\n    + 2 weeks for printing, stuffing (assuming 100% BOM availability)\r\n    + 1 week for WUT PCB checks using existing test tools (no ARTIQ dependence)\r\n    + 1 week for international shipping\r\n    + 3 weeks for testing, thrashing, bug busting, discussions by end users and M-Labs (@jordens visits JQI for a week)\r\n    + 2 weeks schematic update, layout fixes, repeat SI analysis \r\n\r\n# if v0.2\r\nThe need for a second prototype round will be decided for each PCB. From date order is placed with board house... \r\n    + 2 weeks for printing, stuffing \r\n    + 1 week for WUT PCB checks\r\n    + 1 week for international shipping\r\n    + 2 weeks for testing, thrashing, bug busting, discussions\r\n    + 1 weeks schematic update, layout fixes, repeat SI analysis\r\n\r\n# v1.0 \r\nDesign locked in... purchases are placed with board house (eg technosystem.pl)\r\n    + 4 weeks slack for procurement spool-up by prospective customers\r\n    + 2 weeks for printing, stuffing\r\n    + 1 week for WUT PCB checks\r\n    + 1 week for international shipping\r\n\r\nIf v0.1 is frozen 1/1/2017 and you believe this timeline...\r\n    - one prototype round (v1.1) on the way to delivery of v1.0 4/7/2017\r\n    - two prototype rounds (v0.1 -> v0.2) on the way to delivery of v1.0  6/1/2017\r\n\r\n- [ ] @gkasprow Please comment on how realistic this progression is in your experience. \r\n\r\n# deprecate prototype hardware?\r\nDepending on the type and severity of errors in prototypes it may be expedient to deprecate v0.1/v0.2 once v1.0 becomes available. If the deltas are just loop-filter components and phase-noise motivated layout tweaks I guess extended support of prototype hardware by M-Labs isn't onerous. If substantial monkeying is needed to get the prototype hardware to function at all (eg lots of flying leads, hacks to compensate for cross talk induced bit errors) deprecation may be in order. But this is speculation at this point. "},"comment":{"url":"https://api.github.com/repos/m-labs/sinara/issues/comments/267603150","html_url":"https://github.com/m-labs/sinara/issues/131#issuecomment-267603150","issue_url":"https://api.github.com/repos/m-labs/sinara/issues/131","id":267603150,"user":{"login":"sbourdeauducq","id":720864,"avatar_url":"https://avatars.githubusercontent.com/u/720864?v=3","gravatar_id":"","url":"https://api.github.com/users/sbourdeauducq","html_url":"https://github.com/sbourdeauducq","followers_url":"https://api.github.com/users/sbourdeauducq/followers","following_url":"https://api.github.com/users/sbourdeauducq/following{/other_user}","gists_url":"https://api.github.com/users/sbourdeauducq/gists{/gist_id}","starred_url":"https://api.github.com/users/sbourdeauducq/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sbourdeauducq/subscriptions","organizations_url":"https://api.github.com/users/sbourdeauducq/orgs","repos_url":"https://api.github.com/users/sbourdeauducq/repos","events_url":"https://api.github.com/users/sbourdeauducq/events{/privacy}","received_events_url":"https://api.github.com/users/sbourdeauducq/received_events","type":"User","site_admin":false},"created_at":"2016-12-16T14:17:39Z","updated_at":"2016-12-16T14:17:39Z","body":"Right now there is mostly no ARTIQ support specifically for the new hardware. We have been busy with the PDQ, SAWG and DRTIO, and https://github.com/m-labs/artiq/issues/637 has been a frustrating time sink.\r\n\r\nThe major steps for something interesting (stand-alone Sayma) are:\r\n* Kintex Ultrascale support in OpenOCD, done using KCU105.\r\n* GTH port of the JESD204 core, @enjoy-digital will be working on it, can be done with the KCU105.\r\n* DDR3, not started, needs hardware to test as KCU105 uses DDR4.\r\n* support for the RTM FPGA, not started, preferably needs hardware but KCU105 can be quite easily hooked to KC705 for testing parts of it."}}
{"actor":{"display_login":"sbourdeauducq"}}