{"push_id":1381567252,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"08f7b241492e37a3199eb8e71a8c12ee502f05c9","before":"4c1273222636e393da7584ead9019d9908871a44","commits":[{"sha":"08f7b241492e37a3199eb8e71a8c12ee502f05c9","author":{"name":"Nicolai Haehnle","email":"4e56b600684d1796fade77a494abd6e807914572@gmail.com"},"message":"AMDGPU: Allow additional implicit operands on MOVRELS instructions\n\nSummary:\nThe post-RA scheduler occasionally uses additional implicit operands when\nthe vector implicit operand as a whole is killed, but some subregisters\nare still live because they are directly referenced later. Unfortunately,\nthis seems incredibly subtle to reproduce.\n\nFixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test\nand others.\n\nReviewers: arsenm, tstellarAMD\n\nSubscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D25656\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285835 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm/commits/08f7b241492e37a3199eb8e71a8c12ee502f05c9"}]}
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