{"push_id":1466737347,"size":28,"distinct_size":3,"ref":"refs/heads/integration","head":"e60f1897511c3852bd3e1bfc88c9ca7a6b2a1131","before":"176129530e80491a789ea6402a18b65834c7fe54","commits":[{"sha":"d3d6c6e3e9860024cda8766dbcf62f8022a68002","author":{"name":"Antonio Nino Diaz","email":"27951c91e4e5b5318d623354400ec91d3580508b@arm.com"},"message":"Assert correct granularity when mapping a PA\n\nEach translation table level entry can only map a given virtual\naddress onto physical addresses of the same granularity. For example,\nwith the current configuration, a level 2 entry maps blocks of 2 MB,\nso the physical address must be aligned to 2 MB. If the address is not\naligned, the MMU will just ignore the lower bits.\n\nThis patch adds an assertion to make sure that physical addresses are\nalways aligned to the correct boundary.\n\nChange-Id: I0ab43df71829d45cdbe323301b3053e08ca99c2c\nSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/d3d6c6e3e9860024cda8766dbcf62f8022a68002"},{"sha":"0029624fe2d4c327ac885d04d5933f82f38e7071","author":{"name":"Antonio Nino Diaz","email":"27951c91e4e5b5318d623354400ec91d3580508b@arm.com"},"message":"Add PLAT_xxx_ADDR_SPACE_SIZE definitions\n\nAdded the definitions `PLAT_PHY_ADDR_SPACE_SIZE` and\n`PLAT_VIRT_ADDR_SPACE_SIZE` which specify respectively the physical\nand virtual address space size a platform can use.\n\n`ADDR_SPACE_SIZE` is now deprecated. To maintain compatibility, if any\nof the previous defines aren't present, the value of `ADDR_SPACE_SIZE`\nwill be used instead.\n\nFor AArch64, register ID_AA64MMFR0_EL1 is checked to calculate the\nmax PA supported by the hardware and to verify that the previously\nmentioned definition is valid. For AArch32, a 40 bit physical\naddress space is considered.\n\nAdded asserts to check for overflows.\n\nPorting guide updated.\n\nChange-Id: Ie8ce1da5967993f0c94dbd4eb9841fc03d5ef8d6\nSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/0029624fe2d4c327ac885d04d5933f82f38e7071"},{"sha":"e60e74bd26ca009f005541b93baeb55e465e9d5f","author":{"name":"Antonio Nino Diaz","email":"27951c91e4e5b5318d623354400ec91d3580508b@arm.com"},"message":"ARM platforms: Replace address space size defines\n\nThe now deprecated ADDR_SPACE_SIZE has been replaced by the two\ndefines PLAT_PHY_ADDR_SPACE_SIZE and PLAT_VIRT_ADDR_SPACE_SIZE.\n\nChange-Id: I027a2f02f47ab2f679b8979a6dbfb0f08270a1a4\nSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/e60e74bd26ca009f005541b93baeb55e465e9d5f"},{"sha":"2240f45b1aa238b0bfa6b9ec608ec1574e5088bd","author":{"name":"Antonio Nino Diaz","email":"27951c91e4e5b5318d623354400ec91d3580508b@arm.com"},"message":"Forbid block descriptors in initial xlat table levels\n\nIn AArch64, depending on the granularity of the translation tables,\nlevel 0 and/or level 1 of the translation tables may not support block\ndescriptors, only table descriptors.\n\nThis patch introduces a check to make sure that, even if theoretically\nit could be possible to create a block descriptor to map a big memory\nregion, a new subtable will be created to describe its mapping.\n\nChange-Id: Ieb9c302206bfa33fbaf0cdc6a5a82516d32ae2a7\nSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/2240f45b1aa238b0bfa6b9ec608ec1574e5088bd"},{"sha":"7941816a3428f015a9f4a6c5dc978b4fca568f4b","author":{"name":"dp-arm","email":"85a33b5dd3c6fb868048d5df72df51a994b4344b@arm.com"},"message":"Add two timestamps to measure PSCI cache flush overhead\n\nTesting showed that the time spent in a cluster power down\noperation is dominated by cache flushes.  Add two more timestamps\nin runtime instrumentation to keep track of the time spent\nflushing the L1/L2 caches.\n\nChange-Id: I4c5a04e7663543225a85d3c6b271d7b706deffc4\nSigned-off-by: dp-arm <dimitris.papastamos@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/7941816a3428f015a9f4a6c5dc978b4fca568f4b"},{"sha":"53d703a5554991c0bc21951b6ddf2628e70467ba","author":{"name":"Yatharth Kochar","email":"717ab04ca336be64277e711ee1096558312a35cc@arm.com"},"message":"Enable TRUSTED_BOARD_BOOT support for LOAD_IMAGE_V2=1\n\nThis patch enables TRUSTED_BOARD_BOOT (Authentication and FWU)\nsupport, for AArch64, when LOAD_IMAGE_V2 is enabled.\n\nThis patch also enables LOAD_IMAGE_V2 for ARM platforms.\n\nChange-Id: I294a2eebce7a30b6784c80c9d4ac7752808ee3ad\nSigned-off-by: Yatharth Kochar <yatharth.kochar@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/53d703a5554991c0bc21951b6ddf2628e70467ba"},{"sha":"d780699b5e70337c411bc38e470de4eab03af4b6","author":{"name":"Jeenu Viswambharan","email":"2abd04d83240cfe5182b27463216d9d7aea9a895@arm.com"},"message":"GICv3: Introduce power management APIs for Redistributor\n\nSome GICv3 implementations have provision for power management\noperations at Redistributor level. This patch introduces and provides\nplace-holders for Redistributor power management. The default\nimplementations are empty stubs, but are weakly bound so as to enable\nimplementation-specific drivers to override them.\n\nChange-Id: I4fec1358693d3603ca5dce242a2f7f0e730516d8\nSigned-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/d780699b5e70337c411bc38e470de4eab03af4b6"},{"sha":"d17b953ab39f7915391843a71893264874ba436e","author":{"name":"Jeenu Viswambharan","email":"2abd04d83240cfe5182b27463216d9d7aea9a895@arm.com"},"message":"Introduce ARM platform APIs for GICv3 Redistributor\n\nAs with other ARM platform GIC APIs, these directly invoke the GICv3\ndriver APIs for Redistributor power management.\n\nFor the sake of uniform GIC API, empty stubs are placed for those GIC\ndrivers that lack Redistributor component.\n\nChange-Id: Iad0d760d4dbca790998f7768cda621ff3b15a864\nSigned-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/d17b953ab39f7915391843a71893264874ba436e"},{"sha":"74a9578c209fc96eaed4ffdd26fd0e5fe94e21a9","author":{"name":"Jeenu Viswambharan","email":"2abd04d83240cfe5182b27463216d9d7aea9a895@arm.com"},"message":"FVP: Avail GIC Redistributor power management\n\nEarlier patches introduced GIC Redistributor power management for ARM\nplatforms. This patch modifies FVP power management to power down\nRedistributor during CPU power on/off.\n\nChange-Id: I2adb9c50a7dd750019fe3b4e576b5d5fc364bffb\nSigned-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/74a9578c209fc96eaed4ffdd26fd0e5fe94e21a9"},{"sha":"d35dee23b68366af90502c04da4f3eb29d5fe92a","author":{"name":"dp-arm","email":"85a33b5dd3c6fb868048d5df72df51a994b4344b@arm.com"},"message":"tbbr: Fix updating of Non-Trusted NV counter\n\nThe previous code required that a certificate be signed with the ROT\nkey before the platform's NV counter could be updated with the value\nin the certificate.  This implies that the Non-Trusted NV counter was\nnot being updated for Non-Trusted content certificates, as they cannot\nbe signed with the ROT key in the TBBR CoT scheme.\n\nThe code is reworked to only allow updating the platform's Trusted NV\ncounter when a certificate protected by the Trusted NV counter is\nsigned with the ROT key.\n\nContent certificates protected by the Non-Trusted NV counter are\nallowed to update the platform's Non-Trusted NV counter, assuming\nthat the certificate value is higher than the platform's value.\n\nA new optional platform API has been introduced, named\nplat_set_nv_ctr2().  Platforms may choose to implement it and perform\nadditional checks based on the authentication image descriptor before\nmodifying the NV counters.  A default weak implementation is available\nthat just calls into plat_set_nv_ctr().\n\nFixes ARM-software/tf-issues#426\n\nChange-Id: I4fc978fd28a3007bc0cef972ff1f69ad0413b79c\nSigned-off-by: dp-arm <dimitris.papastamos@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/d35dee23b68366af90502c04da4f3eb29d5fe92a"},{"sha":"5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433","author":{"name":"Jeenu Viswambharan","email":"2abd04d83240cfe5182b27463216d9d7aea9a895@arm.com"},"message":"Add provision to extend CPU operations at more levels\n\nVarious CPU drivers in ARM Trusted Firmware register functions to handle\npower-down operations. At present, separate functions are registered to\npower down individual cores and clusters.\n\nThis scheme operates on the basis of core and cluster, and doesn't cater\nfor extending the hierarchy for power-down operations. For example,\nfuture CPUs might support multiple threads which might need powering\ndown individually.\n\nThis patch therefore reworks the CPU operations framework to allow for\nregistering power down handlers on specific level basis. Henceforth:\n\n  - Generic code invokes CPU power down operations by the level\n    required.\n\n  - CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no\n    reset function.\n\n  - CPU drivers register power down handlers as a list: a mandatory\n    handler for level 0, and optional handlers for higher levels.\n\nAll existing CPU drivers are adapted to the new CPU operations framework\nwithout needing any functional changes within.\n\nAlso update firmware design guide.\n\nChange-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043\nSigned-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433"},{"sha":"e12cb61f0e7d8678a2cd6ef73f0a38af1d460e08","author":{"name":"Jeenu Viswambharan","email":"2abd04d83240cfe5182b27463216d9d7aea9a895@arm.com"},"message":"AArch32: Print ASM_ASSERT and panic messages\n\nASM_ASSERT failure and panic messages are suppressed at present. This\npatch enables printing the PC location for panic messages, and file name\nand line number upon assembly assert failure.\n\nChange-Id: I80cb715988e7ce766f64da1e1d7065a74a096a0c\nSigned-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>","distinct":true,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/e12cb61f0e7d8678a2cd6ef73f0a38af1d460e08"},{"sha":"78b4c5b0785f73eb95a58ac9fe8d696f3fef5224","author":{"name":"danh-arm","email":"68a34f7dc4bfd6205eee9b3d985a5ef6c2a94040@arm.com"},"message":"Merge pull request #778 from antonio-nino-diaz-arm/an/xlat-fixes\n\nFixes and improvements to translation tables library","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/78b4c5b0785f73eb95a58ac9fe8d696f3fef5224"},{"sha":"5d93484ab53bcf58b00c51c9ed800d3f527e9e72","author":{"name":"danh-arm","email":"68a34f7dc4bfd6205eee9b3d985a5ef6c2a94040@arm.com"},"message":"Merge pull request #779 from dp-arm/dp/rtinstr-cache\n\nAdd two timestamps to measure PSCI cache flush overhead","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/5d93484ab53bcf58b00c51c9ed800d3f527e9e72"},{"sha":"28076fad495686ba471928057e98a6c0056ab317","author":{"name":"danh-arm","email":"68a34f7dc4bfd6205eee9b3d985a5ef6c2a94040@arm.com"},"message":"Merge pull request #781 from yatharth-arm/yk/aarch64_tbbr_load_img_v2\n\nEnable TRUSTED_BOARD_BOOT support for LOAD_IMAGE_V2=1","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/28076fad495686ba471928057e98a6c0056ab317"},{"sha":"19d2595d41159f7b71ada18653f4ed7aeb540c76","author":{"name":"Dan Handley","email":"68a34f7dc4bfd6205eee9b3d985a5ef6c2a94040@arm.com"},"message":"Merge pull request #785 from dp-arm/dp/nvcounter","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/19d2595d41159f7b71ada18653f4ed7aeb540c76"},{"sha":"99c5ebafbe7486badd7bf28b28871bae13049301","author":{"name":"Sandrine Bailleux","email":"38551fbe2b1a5bc577af67d14a1247aa0d75053d@arm.com"},"message":"Export is_mem_free() function\n\nThe is_mem_free() function used to be local to bl_common.c.\nThis patch exports it so that it can be used outside of bl_common.c.\n\nChange-Id: I01dcb4229f3a36f56a4724b567c5e6c416dc5e98\nSigned-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/99c5ebafbe7486badd7bf28b28871bae13049301"},{"sha":"9f1489e445321edcbf17c4098a474180c504c13d","author":{"name":"Sandrine Bailleux","email":"38551fbe2b1a5bc577af67d14a1247aa0d75053d@arm.com"},"message":"Minor refactoring of BL1 FWU code\n\nThis patch introduces no functional change, it just changes\nthe serial console output.\n\n - Improve accuracy of error messages by decoupling some\n   error cases;\n\n - Improve comments;\n\n - Move declaration of 'mem_layout' local variable closer to\n   where it is used and make it const;\n\n - Rename a local variable to clarify whether it is a source\n   or a destination address (base_addr -> dest_addr).\n\nChange-Id: I349fcf053e233f316310892211d49e35ef2c39d9\nSigned-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>\nSigned-off-by: Dan Handley <dan.handley@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/9f1489e445321edcbf17c4098a474180c504c13d"},{"sha":"b38a9e5cd765fa1c7e99f20a8236c3594f2f0562","author":{"name":"Sandrine Bailleux","email":"38551fbe2b1a5bc577af67d14a1247aa0d75053d@arm.com"},"message":"bl1_fwu_image_copy() refactoring\n\nThis patch refactors the code of the function handling a FWU_AUTH_COPY\nSMC in BL1. All input validation has been moved upfront so it is now\nshared between the RESET and COPYING states.\n\nChange-Id: I6a86576b9ce3243c401c2474fe06f06687a70e2f\nSigned-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>\nSigned-off-by: Dan Handley <dan.handley@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/b38a9e5cd765fa1c7e99f20a8236c3594f2f0562"},{"sha":"1bfb706851c8606aede8f9f391afde1e5339fbf3","author":{"name":"Sandrine Bailleux","email":"38551fbe2b1a5bc577af67d14a1247aa0d75053d@arm.com"},"message":"Add some debug assertions in BL1 FWU copy code\n\nThese debug assertions sanity check the state of the internal\nFWU state machine data when resuming an incomplete image copy\noperation.\n\nChange-Id: I38a125b0073658c3e2b4b1bdc623ec221741f43e\nSigned-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware/commits/1bfb706851c8606aede8f9f391afde1e5339fbf3"}]}
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