{"push_id":1019226541,"size":1000,"distinct_size":0,"ref":"refs/heads/fixes","head":"b562e44f507e863c6792946e4e1b1449fbbac85d","before":"37c5e942bb2eedd98c1cd1fa1f94d79f6b830c38","commits":[{"sha":"5327c7dbd1a7fd980608f44789076a636e5ee5fc","author":{"email":"a02f5c47ee09ecfb205631316fdc727ed52eb140@qlogic.com","name":"Quinn Tran"},"message":"qla2xxx: use TARGET_SCF_USE_CPUID flag to indiate CPU Affinity\n\nSigned-off-by: Quinn Tran <quinn.tran@qlogic.com>\nReviewed-by: Christoph Hellwig <hch@lst.de>\nReviewed-by: Bart Van Assche <bart.vanassche@sandisk.com>\nFixes: fb3269b (\"qla2xxx: Add selective command queuing\")\nSigned-off-by: Himanshu Madhani <himanshu.madhani@qlogic.com>\nSigned-off-by: Nicholas Bellinger <nab@linux-iscsi.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/5327c7dbd1a7fd980608f44789076a636e5ee5fc"},{"sha":"8e7199c2c50fff1969302643171eaa33f1ca148f","author":{"email":"62e7e355d5d8400fa8384448796af0bf6be4ffae@collabora.com","name":"Daniel Stone"},"message":"component: remove device from master match list on failed add\n\nCalling component_add() may result in the completion of a set of\ndevices, which will try to bring up a master. In bringing the master\nup, we populate its match array with the current set of children.\n\nIf binding any of the devices fails, component_add() itself will fail,\nfree the struct component entry, and return to the caller. The\nnow-freed entry is never removed from the master's match array, and\nwill later be used in a futile attempt to bind to freed memory.\n\nBring component_add's behaviour on failure to bring up a master into\nline with component_del by removing the (to-be-freed) component from\nthe master's match array.\n\nThe specific case which broke was:\n  - rockchip_drm_drv adds a component master\n  - dwhdmi_rockchip adds a child component in probe (master incomplete)\n  - rockchip_drm_vop adds two children in probe, which completes the\n    set\n  - inside component_add, we try to bring up the master, having\n    populated the master's match array, and fail with EPROBE_DEFER from\n    dwhdmi_rockchip; we delete the putative component\n  - rockchip_drm_vop's probe fails and returns EPROBE_DEFER\n  - we later re-probe rockchip_drm_vop and add the component; the\n    master is complete, so we attempt to bring it up again\n  - walking the match array, we find the previous child, whose master\n    pointer doesn't match (as it has been freed in the meantime)\n  - rockchip_drm_vop probe fails, and will never be attempted again\n\nFixes: ffc30b74fd6d01588bd3fdebc3b1acc0857e6fc8\nSigned-off-by: Daniel Stone <daniels@collabora.com>\nCc: Russell King <rmk+kernel@arm.linux.org.uk>\nCc: Thierry Reding <treding@nvidia.com>\nCc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/8e7199c2c50fff1969302643171eaa33f1ca148f"},{"sha":"7bf29d3af6807d2a97a8b7d4627104a8da9bcdcb","author":{"email":"cbbc2a491dd609dc667a5c30620606c73351583d@nvidia.com","name":"Jon Hunter"},"message":"irqchip/gic: Only populate set_affinity for the root controller\n\nSetting the affinity of an IRQ, it only applicable for the root\ninterrupt controller and so only populate this operator for the root\ncontroller.\n\nAcked-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/7bf29d3af6807d2a97a8b7d4627104a8da9bcdcb"},{"sha":"389a00d3ad02a06b5d6d692cce76fed6a3dae8b4","author":{"email":"cbbc2a491dd609dc667a5c30620606c73351583d@nvidia.com","name":"Jon Hunter"},"message":"irqchip/gic: Only set the EOImodeNS bit for the root controller\n\nEOImode1 is only used for the root controller and hence only the root\ncontroller uses the eoimode1 functions for handling interrupts. However,\nif the root controller supports EOImode1, then the EOImodeNS bit will be\nset for all GICs, enabling EOImode1. This is not what we want and this\ncauses interrupts on non-root GICs to only be dropped in priority but\nnever deactivated. Therefore, only set the EOImodeNS bit for the root\ncontroller.\n\nAcked-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/389a00d3ad02a06b5d6d692cce76fed6a3dae8b4"},{"sha":"1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596","author":{"email":"8bd0e356a5a4b5d27635ccc7ca7434429e8fba05@caviumnetworks.com","name":"Tirumalesh Chalamarla"},"message":"irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor\n\nThe ARM GICv3 specification mentions the need for dsb after a read\nfrom the ICC_IAR1_EL1 register:\n\n\t4.1.1 Physical CPU Interface:\n\tThe effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1\n\ton the state of a returned INTID are not guaranteed\n\tto be visible until after the execution of a DSB.\n\nNot having this could result in missed interrupts, so let's add the\nrequired barrier.\n\n[Marc: fixed commit message]\n\nAcked-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596"},{"sha":"f4d3d504198d464e406171cfa554a59bd4773d79","author":{"email":"53566a40310e7120a373d88c94d924839fd4b1fa@bmw-carit.de","name":"Daniel Wagner"},"message":"mips: Differentiate between 32 and 64 bit ELF header\n\nDepending on the configuration either the 32 or 64 bit version of\nelf_check_arch() is defined. parse_crash_elf{32|64}_headers() does\nsome basic verification of the ELF header via\nvmcore_elf{32|64}_check_arch() which happen to map to elf_check_arch().\nSince the implementation 32 and 64 bit version of elf_check_arch()\ndiffer, we use the wrong type:\n\n   In file included from include/linux/elf.h:4:0,\n                    from fs/proc/vmcore.c:13:\n   fs/proc/vmcore.c: In function 'parse_crash_elf64_headers':\n>> arch/mips/include/asm/elf.h:228:23: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]\n     struct elfhdr *__h = (hdr);     \\\n                          ^\n   include/linux/crash_dump.h:41:37: note: in expansion of macro 'elf_check_arch'\n    #define vmcore_elf64_check_arch(x) (elf_check_arch(x) || vmcore_elf_check_arch_cross(x))\n                                        ^\n   fs/proc/vmcore.c:1015:4: note: in expansion of macro 'vmcore_elf64_check_arch'\n      !vmcore_elf64_check_arch(&ehdr) ||\n       ^\n\nTherefore, we rather define vmcore_elf{32|64}_check_arch() as a\nbasic machine check and use it also in binfm_elf?32.c as well.\n\nSigned-off-by: Daniel Wagner <daniel.wagner@bmw-carit.de>\nSuggested-by: Maciej W. Rozycki <macro@imgtec.com>\nReviewed-by: Maciej W. Rozycki <macro@imgtec.com>\nReported-by: Fengguang Wu <fengguang.wu@intel.com>\nCc: linux-kernel@vger.kernel.org\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/12529/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/f4d3d504198d464e406171cfa554a59bd4773d79"},{"sha":"bf60e592a1af4d6f65dd54593250183f14360eed","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"mmc: sdhci: Allow override of mmc host operations\n\nIn the past, fixes for specific hardware devices were implemented\nin sdhci using quirks.  That approach is no longer accepted because\nthe growing number of quirks was starting to make the code difficult\nto understand and maintain.\n\nOne alternative to quirks, is to allow drivers to override the default\nmmc host operations.  This patch makes it easy to do that, and it is\nneeded for a subsequent bug fix, for which separate patches are\nprovided.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nCc: stable@vger.kernel.org # v4.4+\nSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/bf60e592a1af4d6f65dd54593250183f14360eed"},{"sha":"8d28b7a72fe18bcdcdb047243ba8fec36b149955","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"mmc: sdhci: Allow override of get_cd() called from sdhci_request()\n\nDrivers may need to provide their own get_cd() mmc host op, but\ncurrently the internals of the current op (sdhci_get_cd()) are\nprovided by sdhci_do_get_cd() which is also called from\nsdhci_request().\n\nTo allow override of the get_cd functionality, change sdhci_request()\nto call ->get_cd() instead of sdhci_do_get_cd().\n\nNote, in the future the call to ->get_cd() will likely be removed\nfrom sdhci_request() since most drivers don't need actually it.\nHowever this change is being done now to facilitate a subsequent\nbug fix.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nCc: stable@vger.kernel.org # v4.4+\nSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/8d28b7a72fe18bcdcdb047243ba8fec36b149955"},{"sha":"163cbe31e5163459908a41a2b4e0d33a28fd557a","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"mmc: sdhci-pci: Fix card detect race for Intel BXT/APL\n\nIntel BXT/APL use a card detect GPIO however the host controller\nwill not enable bus power unless it's card detect also reflects\nthe presence of a card.  Unfortunately those 2 things race which\ncan result in commands not starting, after which the controller\ndoes nothing and there is a 10 second wait for the driver's\n10-second timer to timeout.\n\nThat is fixed by having the driver look also at the present state\nregister to determine if the card is present.  Consequently, provide\na 'get_cd' mmc host operation for BXT/APL that does that.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nCc: stable@vger.kernel.org # v4.4+\nSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/163cbe31e5163459908a41a2b4e0d33a28fd557a"},{"sha":"6a645dd87a5a506779810d7d9935c25fc2ef4687","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"mmc: sdhci-acpi: Fix card detect race for Intel BXT/APL\n\nIntel BXT/APL use a card detect GPIO however the host controller\nwill not enable bus power unless it's card detect also reflects\nthe presence of a card.  Unfortunately those 2 things race which\ncan result in commands not starting, after which the controller\ndoes nothing and there is a 10 second wait for the driver's\n10-second timer to timeout.\n\nThat is fixed by having the driver look also at the present state\nregister to determine if the card is present.  Consequently, provide\na 'get_cd' mmc host operation for BXT/APL that does that.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nCc: stable@vger.kernel.org # v4.4+\nSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/6a645dd87a5a506779810d7d9935c25fc2ef4687"},{"sha":"49b245efab4498575379a36cfab9d7373df3b69a","author":{"email":"00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de","name":"Thomas Gleixner"},"message":"Merge tag 'gic-fixes-4.5-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent\n\nPull GIC fixes from Marc for 4.5-rc4:\n\n- Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode)\n- One fix addressing possible missed interrupts on GICv3","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/49b245efab4498575379a36cfab9d7373df3b69a"},{"sha":"0986d97741150b307775d56f587a73ea873a4f4d","author":{"email":"49712f635b03c16d7f4c43df70e49ec8c565813d@de.ibm.com","name":"Christian Borntraeger"},"message":"s390: fix DAT off memory access, e.g. on kdump\n\ncommit 204ee2c56431 (\"s390/irqflags: optimize irq restore\") optimized\nirqrestore to really only care about interrupts and adapted the\nremaining low level users. One spot (memcpy_real) was not touched,\nthough - fix it. Otherwise a kdump kernel will fail while reading\nthe old kernel. As we re-enable irqs with a non-standard function\nwe have to tell lockdep about that.\n\nFixes: 204ee2c56431 (\"s390/irqflags: optimize irq restore\")\nSigned-off-by: Christian Borntraeger <borntraeger@de.ibm.com>\nSigned-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/0986d97741150b307775d56f587a73ea873a4f4d"},{"sha":"020bf042e5b397479c1174081b935d0ff15d1a64","author":{"email":"9e6a0bb809a7918e8f27f36fc1281e79ae9e5bd0@de.ibm.com","name":"Stefan Haberland"},"message":"s390/dasd: prevent incorrect length error under z/VM after PAV changes\n\nThe channel checks the specified length and the provided amount of\ndata for CCWs and provides an incorrect length error if the size does\nnot match. Under z/VM with simulation activated the length may get\nchanged. Having the suppress length indication bit set is stated as\ngood CCW coding practice and avoids errors under z/VM.\n\nCc: stable@vger.kernel.org\nSigned-off-by: Stefan Haberland <stefan.haberland@de.ibm.com>\nSigned-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/020bf042e5b397479c1174081b935d0ff15d1a64"},{"sha":"9d862ababb609439c5d6987f6d3ddd09e703aa0b","author":{"email":"9e6a0bb809a7918e8f27f36fc1281e79ae9e5bd0@de.ibm.com","name":"Stefan Haberland"},"message":"s390/dasd: fix refcount for PAV reassignment\n\nAdd refcount to the DASD device when a summary unit check worker is\nscheduled. This prevents that the device is set offline with worker\nin place.\n\nCc: stable@vger.kernel.org\nSigned-off-by: Stefan Haberland <stefan.haberland@de.ibm.com>\nSigned-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/9d862ababb609439c5d6987f6d3ddd09e703aa0b"},{"sha":"f6c9b160233f9b5afe926b91b55589b706076640","author":{"email":"8dcf0f69152f32f23184f83357a3731522e56b9c@de.ibm.com","name":"Heiko Carstens"},"message":"s390/diag: avoid lockdep recursion\n\nThe diagnose tracer will indirectly call back into the lockdep code\nwhen lockdep does not expect it (arch_spinlock). This causes lockdep\nto disable itself and therefore we don't have a working lock\ndependency validator anymore.\n\nThis patch effectively disables tracing of diag 0x9c and 0x44 if\nlockdep is enabled.  If however lockdep is enabled spinlocks are\nmainly implemented using a trylock variant, which will not issue any\ndiag 0x9c or 0x44. So this change has hardly any effect on tracing\nexcept when arch_spinlock and friends are explicitly used.\n\nReported-and-Tested-by: David Hildenbrand <dahi@linux.vnet.ibm.com>\nSigned-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>\nReviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>\nAcked-by: Martin Schwidefsky <schwidefsky@de.ibm.com>\nSigned-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/f6c9b160233f9b5afe926b91b55589b706076640"},{"sha":"3c5b1d92b3b02be07873d611a27950addff544d3","author":{"email":"8bd0e356a5a4b5d27635ccc7ca7434429e8fba05@caviumnetworks.com","name":"Tirumalesh Chalamarla"},"message":"arm64: KVM: Configure TCR_EL2.PS at runtime\n\nSetting TCR_EL2.PS to 40 bits is wrong on systems with less that\nless than 40 bits of physical addresses. and breaks KVM on systems\nwhere the RAM is above 40 bits.\n\nThis patch uses ID_AA64MMFR0_EL1.PARange to set TCR_EL2.PS dynamically,\njust like we already do for VTCR_EL2.PS.\n\n[Marc: rewrote commit message, patch tidy up]\n\nReviewed-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/3c5b1d92b3b02be07873d611a27950addff544d3"},{"sha":"111f2b87326199a736c3469265763a6be6e5528f","author":{"email":"13fbd79c3d390e5d6585a21e11ff5ec1970cff0c@japko.eu","name":"Krzysztof Adamski"},"message":"pinctrl: sunxi: H3 requires irq_read_needs_mux\n\nIt seems that on H3, just like on A10, when GPIOs are configured as\nexternal interrupt data registers does not contain their value.  When\nvalue is read, GPIO function must be temporary switched to input for\nreads.\n\nSigned-off-by: Krzysztof Adamski <k@japko.eu>\nAcked-by: Chen-Yu Tsai <wens@csie.org>\nAcked-by: Maxime Ripard <maxime.ripard@free-electrons.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/111f2b87326199a736c3469265763a6be6e5528f"},{"sha":"e972c37459c813190461dabfeaac228e00aae259","author":{"email":"9cd9d802d23c0ed5e224beabf4ae4a5c478746ef@linaro.org","name":"Linus Walleij"},"message":"ARM: 8519/1: ICST: try other dividends than 1\n\nSince the dawn of time the ICST code has only supported divide\nby one or hang in an eternal loop. Luckily we were always dividing\nby one because the reference frequency for the systems using\nthe ICSTs is 24MHz and the [min,max] values for the PLL input\nif [10,320] MHz for ICST307 and [6,200] for ICST525, so the loop\nwill always terminate immediately without assigning any divisor\nfor the reference frequency.\n\nBut for the code to make sense, let's insert the missing i++\n\nReported-by: David Binderman <dcb314@hotmail.com>\nCc: stable@vger.kernel.org\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/e972c37459c813190461dabfeaac228e00aae259"},{"sha":"f070d6715509dafc0af223577c896fe3d204ca88","author":{"email":"4acbb9f2b7a6c35ffe616198daf840632ad3a067@apm.com","name":"Suman Tripathi"},"message":"libahci: Implement the capability to override the generic ahci interrupt handler.\n\nThis patch implements the capability to override the generic AHCI\ninterrupt handler so that specific ahci drivers can implement their\nown custom interrupt handler routines.  It also exports\nahci_handle_port_intr so that custom irq_handler implementations can\nuse it.\n\ntj: s/ahci_irq_handler/irq_handler/ and updated description.\n\nSigned-off-by: Suman Tripathi <stripathi@apm.com>\nSigned-off-by: Tejun Heo <tj@kernel.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/f070d6715509dafc0af223577c896fe3d204ca88"},{"sha":"d867b95f965457b9e85fb061ef8e3fdc029116ed","author":{"email":"4acbb9f2b7a6c35ffe616198daf840632ad3a067@apm.com","name":"Suman Tripathi"},"message":"ata: Remove the AHCI_HFLAG_EDGE_IRQ support from libahci.\n\nThe flexibility to override the irq handles in the LLD's are already\npresent, so controllers implementing a edge trigger latch can\nimplement their own interrupt handler inside the driver.  This patch\nremoves the AHCI_HFLAG_EDGE_IRQ support from libahci and moves edge\nirq handling to ahci_xgene.\n\ntj: Minor update to description.\n\nSigned-off-by: Suman Tripathi <stripathi@apm.com>\nSigned-off-by: Tejun Heo <tj@kenrel.org>","distinct":false,"url":"https://api.github.com/repos/linuxppc/linux/commits/d867b95f965457b9e85fb061ef8e3fdc029116ed"}]}