{"action":"created","issue":{"url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/182","repository_url":"https://api.github.com/repos/clash-lang/clash-compiler","labels_url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/182/labels{/name}","comments_url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/182/comments","events_url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/182/events","html_url":"https://github.com/clash-lang/clash-compiler/issues/182","id":188263990,"number":182,"title":"Clash compiler generates wrong systemverilog (missing type in types.sv)","user":{"login":"idzardh","id":23360481,"avatar_url":"https://avatars.githubusercontent.com/u/23360481?v=3","gravatar_id":"","url":"https://api.github.com/users/idzardh","html_url":"https://github.com/idzardh","followers_url":"https://api.github.com/users/idzardh/followers","following_url":"https://api.github.com/users/idzardh/following{/other_user}","gists_url":"https://api.github.com/users/idzardh/gists{/gist_id}","starred_url":"https://api.github.com/users/idzardh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/idzardh/subscriptions","organizations_url":"https://api.github.com/users/idzardh/orgs","repos_url":"https://api.github.com/users/idzardh/repos","events_url":"https://api.github.com/users/idzardh/events{/privacy}","received_events_url":"https://api.github.com/users/idzardh/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2016-11-09T14:44:20Z","updated_at":"2016-11-18T09:30:13Z","closed_at":null,"body":"I tested all three HDL's and only the systemverilog compiler outputs code that gives an error in QuestaSim. The error generated by questasim is as follows:\r\n\r\n`** Error: ./Testbench_v1_types.sv (954): Failed to find name 'array_of_3_logic_vector_1_to_lv' in specified scope`\r\n\r\nIt also generates the same error for two more locations. It appears as though the whole declaration of this signal is missing, which is strange as the error is not reported in VHDL or Verilog. \r\n\r\nThis is were the error occurs:\r\n\r\n ```systemverilog\r\nfunction array_of_3_array_of_3_logic_vector_1 array_of_3_array_of_3_logic_vector_1_cons(Testbench_v1_types::array_of_3_logic_vector_1 x,logic [0:2][0:0] xs [0:1]);\r\n    array_of_3_array_of_3_logic_vector_1_cons[0] = Testbench_v1_types::array_of_3_logic_vector_1_to_lv(x);\r\n    array_of_3_array_of_3_logic_vector_1_cons[1:2] = xs;\r\n  endfunction\r\n```\r\n\r\n"},"comment":{"url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/comments/261486940","html_url":"https://github.com/clash-lang/clash-compiler/issues/182#issuecomment-261486940","issue_url":"https://api.github.com/repos/clash-lang/clash-compiler/issues/182","id":261486940,"user":{"login":"idzardh","id":23360481,"avatar_url":"https://avatars.githubusercontent.com/u/23360481?v=3","gravatar_id":"","url":"https://api.github.com/users/idzardh","html_url":"https://github.com/idzardh","followers_url":"https://api.github.com/users/idzardh/followers","following_url":"https://api.github.com/users/idzardh/following{/other_user}","gists_url":"https://api.github.com/users/idzardh/gists{/gist_id}","starred_url":"https://api.github.com/users/idzardh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/idzardh/subscriptions","organizations_url":"https://api.github.com/users/idzardh/orgs","repos_url":"https://api.github.com/users/idzardh/repos","events_url":"https://api.github.com/users/idzardh/events{/privacy}","received_events_url":"https://api.github.com/users/idzardh/received_events","type":"User","site_admin":false},"created_at":"2016-11-18T09:30:13Z","updated_at":"2016-11-18T09:30:13Z","body":"I have made a more elaborate example that displays the bug, the code is as follows:\r\n\r\n```haskell\r\nmodule Test where\r\n\r\nimport CLaSH.Prelude\r\n\r\ndummyMealyT :: (Vec 4 ( Vec 3 Bool ), Vec 4 ( Vec 3 (BitVector 22, BitVector 22), Unsigned 4 ))\r\n            -> Bit -> BitVector 32 -> (Bit, (Unsigned 4, BitVector 3, BitVector 32))\r\n\r\ndummyMealyT (conf1, conf2) st addrIn = (resp, outp)\r\n  where\r\n    dest = slice d31 d10 addrIn\r\n    (outp, resp) = ((rId,rFrag, addrIn), rSel)\r\n\r\n    (rId, rFrag, rSel) = foldl g (0, 000, 0) $ zipWith3 f conf1 conf2 (repeat dest)\r\n      where\r\n        g x y = if bit2bool (trd y) then y else x\r\n\r\n        f conf1p (conf2a, conf2b) dest = addId $ zipWith3 comp conf1p conf2a (repeat dest)\r\n          where\r\n            comp conf1pp (conf2aa, conf2ab) dest = bool2bit $ conf1pp && conf2aa <= dest && conf2ab >= dest\r\n            addId vB = (conf2b, v2bv vB, reduceOr vB)\r\n\r\nconf1 = replicate d2 ( False :> True :> False :> Nil ) ++ replicate d2 ( True :> True :> False :> Nil )\r\n\r\nconf2 = zip conf3 conf4\r\n\r\nconf3 = map truncAddr $ a :> b :> c :> d :> Nil\r\n  where\r\n    truncAddr = map (\\(x,y) -> (truncateLSB x, truncateLSB y))\r\n    truncateLSB vec = slice d31 d10 (fromIntegral vec :: BitVector 32)\r\n    a = ((0,2047) :> (2048,4095) :> (4096,6143) :> Nil)\r\n    b = ((6144,8191) :> (8192,10239) :> (10240,12287) :> Nil)\r\n    c = ((12288,14335) :> (14336,16383) :> (16384,18431) :> Nil)\r\n    d = ((18432,20479) :> (20480,22527) :> (22528,24575) :> Nil)\r\n\r\nconf4 = (1::Unsigned 4) :> 2 :> 3 :> 4 :> Nil\r\n\r\ntrd (a,b,c) = c\r\n\r\nbool2bit bool = if bool then 1 else 0\r\n\r\nbit2bool bit = 1==bit\r\n\r\ntopEntity = mealy (dummyMealyT (conf1, conf2)) (0::Bit)\r\n```\r\n\r\nThe generated SV is compiled using QuestaSim 10.4c (64 bits). The first file that needs to be compiled is the types file, but it gives the same error as mentioned before. (This time on line 124)"}}
{"actor":{"display_login":"idzardh"}}