{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/183","repository_url":"https://api.github.com/repos/ucb-bar/rocket-chip","labels_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/183/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/183/comments","events_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/183/events","html_url":"https://github.com/ucb-bar/rocket-chip/issues/183","id":168449946,"number":183,"title":"Rocket frontend mask logic change of behavior","user":{"login":"ccelio","id":788854,"avatar_url":"https://avatars.githubusercontent.com/u/788854?v=3","gravatar_id":"","url":"https://api.github.com/users/ccelio","html_url":"https://github.com/ccelio","followers_url":"https://api.github.com/users/ccelio/followers","following_url":"https://api.github.com/users/ccelio/following{/other_user}","gists_url":"https://api.github.com/users/ccelio/gists{/gist_id}","starred_url":"https://api.github.com/users/ccelio/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ccelio/subscriptions","organizations_url":"https://api.github.com/users/ccelio/orgs","repos_url":"https://api.github.com/users/ccelio/repos","events_url":"https://api.github.com/users/ccelio/events{/privacy}","received_events_url":"https://api.github.com/users/ccelio/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2016-07-30T05:11:26Z","updated_at":"2016-07-30T06:02:24Z","closed_at":null,"body":"Introduced by commit https://github.com/ucb-bar/rocket/commit/d91be2b545ea0eb704bf3c2b02b5d200f27426fa#diff-dbf1307484c9f6974955adde94a99967, the behavior of the masking logic has changed (https://github.com/ucb-bar/rocket-chip/blob/master/rocket/src/main/scala/frontend.scala#L128):\r\n\r\n````scala\r\nio.cpu.resp.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Up(fetchWidth)+log2Up(coreInstBytes)-1, log2Up(coreInstBytes))\r\n````\r\n\r\nFor `fetchWidth=1`, `coreInstBytes=4`, that reduces to\r\n\r\n> mask := UInt(1) << s2_pc(1+2-1, 2)\r\n> mask := 1 << pc(2,2)\r\n\r\nThis means `mask` can be 0.\r\n\r\nThe old behavior, for `fetchWidth = 1`, was for `mask` to be set to UInt(1) (as the one instruction will always be valid if imem.valid is true).\r\n\r\nIs the changed behavior intentional?\r\n\r\n"},"comment":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/comments/236346264","html_url":"https://github.com/ucb-bar/rocket-chip/issues/183#issuecomment-236346264","issue_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/183","id":236346264,"user":{"login":"aswaterman","id":1031106,"avatar_url":"https://avatars.githubusercontent.com/u/1031106?v=3","gravatar_id":"","url":"https://api.github.com/users/aswaterman","html_url":"https://github.com/aswaterman","followers_url":"https://api.github.com/users/aswaterman/followers","following_url":"https://api.github.com/users/aswaterman/following{/other_user}","gists_url":"https://api.github.com/users/aswaterman/gists{/gist_id}","starred_url":"https://api.github.com/users/aswaterman/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/aswaterman/subscriptions","organizations_url":"https://api.github.com/users/aswaterman/orgs","repos_url":"https://api.github.com/users/aswaterman/repos","events_url":"https://api.github.com/users/aswaterman/events{/privacy}","received_events_url":"https://api.github.com/users/aswaterman/received_events","type":"User","site_admin":false},"created_at":"2016-07-30T06:02:24Z","updated_at":"2016-07-30T06:02:24Z","body":"No; the problem is log2Up (it would have noisily failed using log2Ceil).\nWill fix.\n\nOn Friday, July 29, 2016, Christopher Celio <notifications@github.com>\nwrote:\n\n> Introduced by commit ucb-bar/rocket@d91be2b\n> #diff-dbf1307484c9f6974955adde94a99967\n> <https://github.com/ucb-bar/rocket/commit/d91be2b545ea0eb704bf3c2b02b5d200f27426fa#diff-dbf1307484c9f6974955adde94a99967>,\n> the behavior of the masking logic has changed (\n> https://github.com/ucb-bar/rocket-chip/blob/master/rocket/src/main/scala/frontend.scala#L128\n> ):\n>\n> io.cpu.resp.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Up(fetchWidth)+log2Up(coreInstBytes)-1, log2Up(coreInstBytes))\n>\n> For fetchWidth=1, coreInstBytes=4, that reduces to\n>\n> mask := UInt(1) << s2_pc(1+2-1, 2)\n> mask := 1 << pc(2,2)\n>\n> This means mask can be 0.\n>\n> The old behavior, for fetchWidth = 1, was for mask to be set to UInt(1)\n> (as the one instruction will always be valid if imem.valid is true).\n>\n> Is the changed behavior intentional?\n>\n> —\n> You are receiving this because you are subscribed to this thread.\n> Reply to this email directly, view it on GitHub\n> <https://github.com/ucb-bar/rocket-chip/issues/183>, or mute the thread\n> <https://github.com/notifications/unsubscribe-auth/AA-7wvWnQYfb0nUDBtwQ0jm2cckNf44yks5qat0AgaJpZM4JYuqw>\n> .\n>\n"}}
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