{"push_id":927077646,"size":308,"distinct_size":308,"ref":"refs/heads/master","head":"3861d784b1a470570a0098ac5c25d79e3073c0d9","before":"8356431bf8df6d47255d6a74ca9dce53d75265c7","commits":[{"sha":"6768146aeff0bd67a68ec6e0438667d505971449","author":{"email":"1d31b11c1b92bf5d043d36edfe7174db39a6b891@ossystems.com.br","name":"Otavio Salvador"},"message":"cgtqmx6eval: Fix defconfig name\n\nAfter the conversion to SPL the defconfig was renamed, so adjust it.\n\nSigned-off-by: Otavio Salvador <otavio@ossystems.com.br>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/6768146aeff0bd67a68ec6e0438667d505971449"},{"sha":"29bc24ec4f9f159b3fdaf9c85cce89504a54782a","author":{"email":"679188261afeb60eb822cd934fd7b46a48ddd743@freescale.com","name":"Fabio Estevam"},"message":"mx6sxsabresd: Fix Ethernet PHY reset sequence\n\nSince commit 59370f3fcd1350 (\"net: phy: delay only if reset handler is\nregistered\") Ethernet is no longer functional.\n\nThis commit does not have an issue in itself, but it revelead a problem\nwith the Ethernet initialization.\n\nFix this by calling enable_fec_anatop_clock() earlier and also\nby adding a 10ms reset delay as recommended in the AR8031 datasheet.\n\nSuggested-by: Jörg Krause <joerg.krause@embedded.rocks>\nSigned-off-by: Fabio Estevam <fabio.estevam@freescale.com>\nReviewed-by: Stefano Babic <sbabic@denx.de>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/29bc24ec4f9f159b3fdaf9c85cce89504a54782a"},{"sha":"9f74ebe1e4138dde40bc6dcbc858276ec7f0c7b2","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"imx: mx7: enable CONFIG_FSL_CLK\n\nThis commit \"677f970bc62a661690b3431543d5a5d5e682ba70\" introduce a new\nmacro \"CONFIG_FSL_CLK\" that get_clocks() should not be limited by ESDHC.\n\nBut that patch missed to enable it for i.MX7. THis patch enables\nCONFIG_FSL_CLK to let get_clocks work.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nCc: Adrian Alonso <aalonso@freescale.com>\nCc: Stefano Babic <sbabic@denx.de>\nCc: Fabio Estevam <fabio.estevam@freescale.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/9f74ebe1e4138dde40bc6dcbc858276ec7f0c7b2"},{"sha":"0ff47e590bb50978f3cb397e6b04f82702bfe954","author":{"email":"fd3fb11d20dd2b55b441515e5cc120796bf92f11@myspectrum.nl","name":"Jeroen Hofstee"},"message":"imx: mx6: add missing return value\n\ncc: Peng Fan <Peng.Fan@freescale.com>\nSigned-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>\nReviewed-by: Peng Fan <Peng.Fan@freescale.com>\nReviewed-by: Stefano Babic <sbabic@denx.de>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/0ff47e590bb50978f3cb397e6b04f82702bfe954"},{"sha":"0c890879fe2a5731df7aee3dd38e455008fa9977","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"imx: mx6: fix reg base address when runtime usage\n\nShould use parenthese to wrap the macro definition, otherwise\nwe will encounter error like the following:\n\n\"\nif (base_addr != LCDIF1_BASE_ADDR) {\n    puts(\"Wrong LCD interface!\\n\");\n    return -EINVAL;\n}\n\"\n\nWithout this patch, we will always encounter \"Wrong LCD interface\".\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nCc: Stefano Babic <sbabic@denx.de>\nReviewed-by: Stefano Babic <sbabic@denx.de>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/0c890879fe2a5731df7aee3dd38e455008fa9977"},{"sha":"8555dd88cd1a7b5dd1e76c111fe635a92223b98b","author":{"email":"df74735e5e8e4da139876d19d7450f461d604b9f@synopsys.com","name":"Alexey Brodkin"},"message":"axs10x: add support of generic EHCI USB 2.0 controller\n\nThis commit adds support of USB 2.0 storage media on AXS10x boards.\n\nSigned-off-by: Alexey Brodkin <abrodkin@synopsys.com>\nCc: Marek Vasut <marex@denx.de>\nCc: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/8555dd88cd1a7b5dd1e76c111fe635a92223b98b"},{"sha":"a0ae380b3c32254a6462674cfbfdd763d10bca41","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE\n\nCurrently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the\nreturn value of dev_get_addr(), it creates potential size mismatch\nas dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can\nbe either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change\nOF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>\nReviewed-by: Stefan Roese <sr@denx.de>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/a0ae380b3c32254a6462674cfbfdd763d10bca41"},{"sha":"c5c5c201fe37a02e9edf99b0a2ba9353d9d55ddf","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: Fix PCI UART compatible string for crownbay and galileo\n\nWith recent ns16550 driver changes, we only changed the legacy UART\n(at I/O port 0x3f8) compatible string, but forgot to change the PCI\nUART compatible string. Now fix it.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/c5c5c201fe37a02e9edf99b0a2ba9353d9d55ddf"},{"sha":"4932443d260d23c882e48eefcc66a83dfca7ee5a","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: Move i8254_init() to x86_cpu_init_f()\n\nRight now i8254_init() is called from timer_init() in the tsc timer\ndriver. But actually i8254 and tsc are completely different things.\nSince tsc timer has been converted to driver model, we should find\na new place that is appropriate for U-Boot to call i8254_init(),\nwhich is now x86_cpu_init_f().\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/4932443d260d23c882e48eefcc66a83dfca7ee5a"},{"sha":"2317cf0970318a7f992acf968540dfcd6ff90f7b","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"common: Remove timer_init() call for x86\n\nWith driver model timer support, there should not be an explict\ncall to timer_init(). Remove this call for x86.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/2317cf0970318a7f992acf968540dfcd6ff90f7b"},{"sha":"9bf76c21e0248d06ad7e804b1a95d6cd0bc5f14f","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE\n\nNORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>\nTested-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/9bf76c21e0248d06ad7e804b1a95d6cd0bc5f14f"},{"sha":"efe2d80cca4822ce6c435993e01467eeee8babfb","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: Clean up ivybridge/chrome Kconfig options\n\nThere are some options which are never used, and also some options\nwhich are selected by others but have never been a Kconfg option.\nClean these up.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>\nTested-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/efe2d80cca4822ce6c435993e01467eeee8babfb"},{"sha":"d475d59020af32bd5b55ca48a5bc73213e53a7c8","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: Remove CPU_INTEL_SOCKET_RPGA989\n\nThis Kconfig option name indicates it has something to do with cpu\nsocket, however it is actually not the case. Remove it and move\noptions inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>\nTested-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/d475d59020af32bd5b55ca48a5bc73213e53a7c8"},{"sha":"789fa275b3750e60c60cb3d18eabc9467892c257","author":{"email":"0f584745b714e230c31946b740db1d21d0507567@gmail.com","name":"Bin Meng"},"message":"x86: Remove HAVE_ACPI_RESUME\n\nThese are currently dead codes. Until we have complete ACPI support,\nwe don't know if it works or not. Remove to avoid confusion.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nAcked-by: Simon Glass <sjg@chromium.org>\nTested-by: Simon Glass <sjg@chromium.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/789fa275b3750e60c60cb3d18eabc9467892c257"},{"sha":"cbc1a91afb7fb0f096453e5574bc5c0719c6c9c4","author":{"email":"9fa1be1a5b5729e4c6b404f34c9ce49ff4882fd8@redhat.com","name":"Hans de Goede"},"message":"sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs\n\nAccording to the datasheets the max speed of AHB1 is 276 MHz, so\nsetting it to PLL6 / 3 which gives us 200MHz everywhere is fine,\nand gives us a nice speed-up in certain workloads.\n\nSuggested-by: Chen-Yu Tsai <wens@csie.org>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>\nAcked-by: Ian Campbell <ijc@hellion.org.uk>\nTested-by: Chen-Yu Tsai <wens@csie.org>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/cbc1a91afb7fb0f096453e5574bc5c0719c6c9c4"},{"sha":"762e24a07871aec34fb3b5169dee309eb353861d","author":{"email":"e4e7070eaf13f3dc11d2da51c237464bfbcdcf71@gmail.com","name":"vishnupatekar"},"message":"sunxi: Add Machine Support for A83T SOC\n\nAllwinner A83T is octa-core cortex-a7 SOC.\nThis enables support for A83T.\n\nSMP is not yet supported.\n\nSigned-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\nReviewed-by: Hans de Goede <hdegoede@redhat.com>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/762e24a07871aec34fb3b5169dee309eb353861d"},{"sha":"d5a3357f1bdf24a2c5df9bc219b963c09dd6c6b3","author":{"email":"e4e7070eaf13f3dc11d2da51c237464bfbcdcf71@gmail.com","name":"vishnupatekar"},"message":"sunxi: Add support for UART0 in PB pin group on A83T\n\nOn A83T, PB9,PB10 are UART0 pins.\nOn allwinner A83T Dev board(h8homlet), this uart0 serial connector\nis exposed.\n\nSigned-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\nReviewed-by: Hans de Goede <hdegoede@redhat.com>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/d5a3357f1bdf24a2c5df9bc219b963c09dd6c6b3"},{"sha":"813c7372bbb5b8939c0e0ef04d1d16d97e489d75","author":{"email":"e4e7070eaf13f3dc11d2da51c237464bfbcdcf71@gmail.com","name":"vishnupatekar"},"message":"sunxi: power: axp818: add support for axp818 driver\n\nAXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board.\nIt's registers are different and calculating reg config is different than\nthat of earlier axp power ICs.\n\nDCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment.\nall other voltages can be added subsequently.\nAXP datasheet is uploaded to wiki:\nhttp://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf\n\nSigned-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\nReviewed-by: Hans de Goede <hdegoede@redhat.com>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/813c7372bbb5b8939c0e0ef04d1d16d97e489d75"},{"sha":"95ab8fee8a5b1782d554be9565584eb29e7da0ce","author":{"email":"e4e7070eaf13f3dc11d2da51c237464bfbcdcf71@gmail.com","name":"vishnupatekar"},"message":"sunxi: power: enabled support for axp818\n\nEnabled support for AXP818 in SPL and u-boot.\nDCDC1, DCDC2, DCDC3 and DCSC5 are enabled.\n\nSigned-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\nReviewed-by: Hans de Goede <hdegoede@redhat.com>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/95ab8fee8a5b1782d554be9565584eb29e7da0ce"},{"sha":"f542948b1e8cd53d6e48e38bae6e305233b9d7a3","author":{"email":"e4e7070eaf13f3dc11d2da51c237464bfbcdcf71@gmail.com","name":"vishnupatekar"},"message":"sunxi: clk: add basic clocks for A83T\n\nAdd basic clocks pll1, pll5, and some default values from allwinner u-boot.\n\nSigned-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\n[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,\nfixing the mmc support not working\n[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to\nstabilize, fixing cold-booting directly from sdcard not working\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>","distinct":true,"url":"https://api.github.com/repos/uniphier/u-boot-unph/commits/f542948b1e8cd53d6e48e38bae6e305233b9d7a3"}]}