{"push_id":1443070524,"size":2,"distinct_size":2,"ref":"refs/heads/cm-14.1","head":"bc27d099d581ea59e5ccaab39f6b2deb54eb27ce","before":"1920b3496c95be1e73dd6882801501523614de44","commits":[{"sha":"5836826a208dee402d3820ec7068108e27daf318","author":{"name":"Tony Truong","email":"ae59414b9c21833369532308da89684a378f748d@codeaurora.org"},"message":"msm: pcie: add additional latency for PCIe switch case\n\nAdd the latency PCIe endpoint required before PCI framework scans\nbus, when PCIe switch exists.\n\nChange-Id: Ia567ccc217e7060c113b318c1bfb87e36b68cd93\nSigned-off-by: Yan He <yanhe@codeaurora.org>\nSigned-off-by: Tony Truong <truong@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/CyanogenMod/android_kernel_xiaomi_msm8996/commits/5836826a208dee402d3820ec7068108e27daf318"},{"sha":"bc27d099d581ea59e5ccaab39f6b2deb54eb27ce","author":{"name":"Tony Truong","email":"ae59414b9c21833369532308da89684a378f748d@codeaurora.org"},"message":"msm: pcie: add support to get PCIe PHY init sequence from DT\n\nPCIe PHY varies between each chipset. Thus, the PHY init sequence on\neach of these chipsets are also different. Therefore, add the support\nto read PCIe PHY init sequence from devicetree.\n\nChange-Id: I21c2ce2b7d3bf1541a5d3580db4bc40497701095\nSigned-off-by: Tony Truong <truong@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/CyanogenMod/android_kernel_xiaomi_msm8996/commits/bc27d099d581ea59e5ccaab39f6b2deb54eb27ce"}]}
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