{"action":"created","issue":{"url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/103","repository_url":"https://api.github.com/repos/openrisc/orpsoc-cores","labels_url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/103/labels{/name}","comments_url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/103/comments","events_url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/103/events","html_url":"https://github.com/openrisc/orpsoc-cores/issues/103","id":167157674,"number":103,"title":"No pin assignment of JTAG_TAP for de0_nano","user":{"login":"zavax2005","id":17891776,"avatar_url":"https://avatars.githubusercontent.com/u/17891776?v=3","gravatar_id":"","url":"https://api.github.com/users/zavax2005","html_url":"https://github.com/zavax2005","followers_url":"https://api.github.com/users/zavax2005/followers","following_url":"https://api.github.com/users/zavax2005/following{/other_user}","gists_url":"https://api.github.com/users/zavax2005/gists{/gist_id}","starred_url":"https://api.github.com/users/zavax2005/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/zavax2005/subscriptions","organizations_url":"https://api.github.com/users/zavax2005/orgs","repos_url":"https://api.github.com/users/zavax2005/repos","events_url":"https://api.github.com/users/zavax2005/events{/privacy}","received_events_url":"https://api.github.com/users/zavax2005/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":1,"created_at":"2016-07-23T00:49:22Z","updated_at":"2016-07-23T21:59:02Z","closed_at":null,"body":"I couldn't find pin assignment of JTAG_TAP for de0_nano from orpsoc-cores/systems/de0_nano/data/pinmap.tcl. Does that mean I couldn't use OpenOCD to write program to RAM via JTAG?\r\n\r\nThis seems to explain the trouble I'm running into now:\r\n\r\n- I was able to build de0_nano.sof with fusesoc build command.\r\n- I was able to upload the bitstream to the de0_nano board using quartus_pgm command\r\n- OpenOCD could connect to the board and or1k_elf_gdb also could connect to the OpenOCD.\r\n- After I uploaded a sample LED blinking program through GDB, nothing happened on the board.\r\n\r\nHowever\r\n\r\n- In order to verify the LED blinking program is valid, I instead used a pre-built de0_nano_orconf2013.sof image from opencores.org. The same LED blinking program started to work on the board.\r\n\r\nDid I miss anything during those steps, or am I completely wrong? Thanks in advance.\r\n\r\n-Xueming"},"comment":{"url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/comments/234742849","html_url":"https://github.com/openrisc/orpsoc-cores/issues/103#issuecomment-234742849","issue_url":"https://api.github.com/repos/openrisc/orpsoc-cores/issues/103","id":234742849,"user":{"login":"olofk","id":2194902,"avatar_url":"https://avatars.githubusercontent.com/u/2194902?v=3","gravatar_id":"","url":"https://api.github.com/users/olofk","html_url":"https://github.com/olofk","followers_url":"https://api.github.com/users/olofk/followers","following_url":"https://api.github.com/users/olofk/following{/other_user}","gists_url":"https://api.github.com/users/olofk/gists{/gist_id}","starred_url":"https://api.github.com/users/olofk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/olofk/subscriptions","organizations_url":"https://api.github.com/users/olofk/orgs","repos_url":"https://api.github.com/users/olofk/repos","events_url":"https://api.github.com/users/olofk/events{/privacy}","received_events_url":"https://api.github.com/users/olofk/received_events","type":"User","site_admin":false},"created_at":"2016-07-23T21:59:02Z","updated_at":"2016-07-23T21:59:02Z","body":"The OpenRISC debug system needs to connect to a JTAG controller in the FPGA. For some SoCs, we use the jtag_tap as a JTAG controller, and in those cases we need to connect to FPGA I/O pins. For the de0 nano SoC however, the debug system is connected to an internal Altera JTAG controller in the FPGA which is called altera_virtual_jtag here. This controller is connected to the dedicated JTAG pins on the FPGA (which is the same interface that is used for example by SignalTap). Therefore we don't need any specific pin mappings for the JTAG pins, as this is hard wired in the FPGA\r\n\r\nOn the de0 nano board, the dedicated FPGA JTAG pins are then connected to a chip which translates the JTAG commands to USB, using the USB Blaster protocol. It is this way we use to connect OpenOCD to the OpenRISC.\r\n\r\nAbout your problem with not getting the LED blinker running, I have a theory why it's not working. When the CPU is started, it starts to execute the program that is stored in the built-in boot ROM. The default boot ROM for the de0_nano SoC is set up to load a program from the SPI Flash to memory and execute this. In your case, there probably isn't any program in the SPI Flash, and since I have not implemented a fallback mechanism, nothing at all happens.\r\n\r\nIf my theory is correct we could get around this by using another boot ROM that just tries to execute directly from RAM instead. With this boot ROM, you can connect to the CPU with a debugger, upload your program, and when you reset the CPU, it will execute.\r\n\r\nTry building with `usesoc build de0_nano --bootrom_file=~/.local/share/orpsoc-cores/systems/de0_nano/sw/clear_r3_and_jump_to_0x100.vh` and see if that helps.\r\n\r\nA better long term solution would probably be to improve the default boot loader to execute from RAM if nothing is found in the SPI Flash. I'll try to fix that\r\n"}}
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