{"push_id":1130558447,"size":5,"distinct_size":5,"ref":"refs/heads/test4","head":"b9151e486c0d5a449fdb965ef99f25f939a677bf","before":"f6b2bd797ab5f0f910a8a22046123fb3990f1c9a","commits":[{"sha":"a8ac05cf7b6c9f0940b99e1b174e494ac2edf09b","author":{"email":"1a2f18c7887fc8d384193bb926e616097dea5b69@google.com","name":"JP Abgrall"},"message":"ARM: fault: assume no context when IRQs are disabled during data abort.\n\nBail out early if IRQs are disabled in do_page_fault or else\n  [14415.157266] BUG: sleeping function called from invalid context at arch/arm/mm/fault.c:301\n\nRussell King's idea from\n  http://comments.gmane.org/gmane.linux.ports.arm.omap/59256\n\nSigned-off-by: JP Abgrall <jpa@google.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/kernel-copyleft/commits/a8ac05cf7b6c9f0940b99e1b174e494ac2edf09b"},{"sha":"1c496cfd1a91fdc75cfd043b1f9354a0692b57b1","author":{"email":"b07d7e22a002c36e256b78f51f1f0db608e62a13@arm.com","name":"Lorenzo Pieralisi"},"message":"ARM: mm: rename jump labels in v7_flush_dcache_all function\n\nThis patch renames jump labels in v7_flush_dcache_all in order to define\na specific flush cache levels entry point.\n\nTODO: factor out the level flushing loop if considered worthwhile and\n      define the input registers requirements.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/kernel-copyleft/commits/1c496cfd1a91fdc75cfd043b1f9354a0692b57b1"},{"sha":"d045c3ce1ee651442aa7f83136b9f53b796b11f3","author":{"email":"5b4d8dc9ea337fff5fd1729321eda9873ade0b09@xxxxxx","name":"Santosh Shilimkar"},"message":"ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API\n\nThe ARMv7 processor setup function __v7_setup() cleans and invalidates the\nCPU cache before enabling MMU to start the CPU with a clean CPU local cache.\n\nBut on ARMv7 architectures like Cortex-[A15/A8], this code will end\nup flushing the L2 caches(up to level of Coherency) which is undesirable\nand expensive. The setup functions are used in the CPU hotplug scenario too\nand hence flushing all cache levels should be avoided.\n\nThis patch replaces the cache flushing call with the newly introduced\nv7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and\ninvalidated when a processors executes __v7_setup which is the expected\nbehavior.\n\nFor processors like A9 and A5 where the L2 cache is an outer one the\nbehavior should be unchanged.\n\nSigned-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/kernel-copyleft/commits/d045c3ce1ee651442aa7f83136b9f53b796b11f3"},{"sha":"461046ab89666571aa110db50d3f27ab0a9e42fe","author":{"email":"331be22c6b63ca3e0a03d408c2d906b1b02cd5f2@cmpxchg.org","name":"Johannes Weiner"},"message":"arch: mm: do not invoke OOM killer on kernel fault OOM\n\nKernel faults are expected to handle OOM conditions gracefully (gup,\nuaccess etc.), so they should never invoke the OOM killer.  Reserve this\nfor faults triggered in user context when it is the only option.\n\nMost architectures already do this, fix up the remaining few.\n\nSigned-off-by: Johannes Weiner <hannes@cmpxchg.org>\nReviewed-by: Michal Hocko <mhocko@suse.cz>\nAcked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>\nCc: David Rientjes <rientjes@google.com>\nCc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>\nCc: azurIt <azurit@pobox.sk>\nSigned-off-by: Andrew Morton <akpm@linux-foundation.org>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/kernel-copyleft/commits/461046ab89666571aa110db50d3f27ab0a9e42fe"},{"sha":"b9151e486c0d5a449fdb965ef99f25f939a677bf","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs\n\nflush_cache_louis flushes the D-side caches to the point of unification\ninner-shareable. On uniprocessor CPUs, this is defined as zero and\ntherefore no flushing will take place. Rather than invent a new interface\nfor UP systems, instead use our SMP_ON_UP patching code to read the\nLoUU from the CLIDR instead.\n\nCc: <stable@vger.kernel.org>\nCc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>\nTested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/kernel-copyleft/commits/b9151e486c0d5a449fdb965ef99f25f939a677bf"}]}
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