{"push_id":1439061314,"size":9,"distinct_size":9,"ref":"refs/heads/master","head":"d9d04527c79f0f7d9186272866526e871ef4ac6f","before":"3e5de27e940d00d8d504dfb96625fb654f641509","commits":[{"sha":"10c77dba40ff58fc03587b3b60725bb7fd723183","author":{"name":"Ben Hutchings","email":"9c85637c38b80821c7bd8a03bde7b59da81ab77d@decadent.org.uk"},"message":"powerpc/boot: Fix build failure in 32-bit boot wrapper\n\nOPAL is not callable from 32-bit mode and the assembly code for it\nmay not even build (depending on how binutils was configured).\n\nReferences: https://buildd.debian.org/status/fetch.php?pkg=linux&arch=powerpcspe&ver=4.8.7-1&stamp=1479203712\nFixes: 656ad58ef19e (\"powerpc/boot: Add OPAL console to epapr wrappers\")\nCc: stable@vger.kernel.org # v4.8+\nSigned-off-by: Ben Hutchings <ben@decadent.org.uk>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/10c77dba40ff58fc03587b3b60725bb7fd723183"},{"sha":"dd7b2f035ec41a409f7a7cec7aabc0ec0eacf476","author":{"name":"Benjamin Herrenschmidt","email":"58942ee662d0fe5d44043b40ceefc845bad5a84d@kernel.crashing.org"},"message":"powerpc/mm: Fix lazy icache flush on pre-POWER5\n\nOn 64-bit CPUs with no-execute support and non-snooping icache, such as\n970 or POWER4, we have a software mechanism to ensure coherency of the\ncache (using exec faults when needed).\n\nThis was broken due to a logic error when the code was rewritten\nfrom assembly to C, previously the assembly code did:\n\n  BEGIN_FTR_SECTION\n         mr      r4,r30\n         mr      r5,r7\n         bl      hash_page_do_lazy_icache\n  END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)\n\nWhich tests that:\n   (cpu_features & (NOEXECUTE | COHERENT_ICACHE)) == NOEXECUTE\n\nWhich says that the current cpu does have NOEXECUTE, but does not have\nCOHERENT_ICACHE.\n\nFixes: 91f1da99792a (\"powerpc/mm: Convert 4k hash insert to C\")\nFixes: 89ff725051d1 (\"powerpc/mm: Convert __hash_page_64K to C\")\nFixes: a43c0eb8364c (\"powerpc/mm: Convert 4k insert from asm to C\")\nCc: stable@vger.kernel.org # v4.5+\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nReviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n[mpe: Change log verbosification]\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/dd7b2f035ec41a409f7a7cec7aabc0ec0eacf476"},{"sha":"5102981212454998d549273ff9847f19e97a1794","author":{"name":"Stephan Mueller","email":"5286f633a2b8438ae9d362bedb5d5c56dfca07cb@chronox.de"},"message":"crypto: drbg - prevent invalid SG mappings\n\nWhen using SGs, only heap memory (memory that is valid as per\nvirt_addr_valid) is allowed to be referenced. The CTR DRBG used to\nreference the caller-provided memory directly in an SG. In case the\ncaller provided stack memory pointers, the SG mapping is not considered\nto be valid. In some cases, this would even cause a paging fault.\n\nThe change adds a new scratch buffer that is used unconditionally to\ncatch the cases where the caller-provided buffer is not suitable for\nuse in an SG. The crypto operation of the CTR DRBG produces its output\nwith that scratch buffer and finally copies the content of the\nscratch buffer to the caller's buffer.\n\nThe scratch buffer is allocated during allocation time of the CTR DRBG\nas its access is protected with the DRBG mutex.\n\nSigned-off-by: Stephan Mueller <smueller@chronox.de>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/5102981212454998d549273ff9847f19e97a1794"},{"sha":"66bf093772040ae8b864d2cf953f2c73005f7815","author":{"name":"Harsh Jain","email":"aacdf4b51be7ada8297361c86eac9d8aca9e530d@chelsio.com"},"message":"crypto: chcr - Fix memory corruption\n\nFix memory corruption done by  *((u32 *)dec_key + k)\n operation.\n\nSigned-off-by: Jitendra Lulla <JLULLA@chelsio.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/66bf093772040ae8b864d2cf953f2c73005f7815"},{"sha":"57891633eeef60e732e045731cf20e50ee80acb4","author":{"name":"David Michael","email":"824593e020de1c43bbf90ef0fec97a42f2b32aa0@coreos.com"},"message":"crypto: rsa - Add Makefile dependencies to fix parallel builds\n\nBoth asn1 headers are included by rsa_helper.c, so rsa_helper.o\nshould explicitly depend on them.\n\nSigned-off-by: David Michael <david.michael@coreos.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/57891633eeef60e732e045731cf20e50ee80acb4"},{"sha":"409bf7f8a02ef88db5a0f2cdcf9489914f4b8508","author":{"name":"Andrew Donnellan","email":"88f9fbfa5a7fc0c41e284752e169a16d1d6535b0@au1.ibm.com"},"message":"powerpc/eeh: Fix deadlock when PE frozen state can't be cleared\n\nIn eeh_reset_device(), we take the pci_rescan_remove_lock immediately after\nafter we call eeh_reset_pe() to reset the PCI controller. We then call\neeh_clear_pe_frozen_state(), which can return an error. In this case, we\nbail out of eeh_reset_device() without calling pci_unlock_rescan_remove().\n\nAdd a call to pci_unlock_rescan_remove() in the eeh_clear_pe_frozen_state()\nerror path so that we don't cause a deadlock later on.\n\nReported-by: Pradipta Ghosh <pradghos@in.ibm.com>\nFixes: 78954700631f (\"powerpc/eeh: Avoid I/O access during PE reset\")\nCc: stable@vger.kernel.org # v3.16+\nSigned-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>\nAcked-by: Russell Currey <ruscur@russell.cc>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/409bf7f8a02ef88db5a0f2cdcf9489914f4b8508"},{"sha":"dadc4a1bb9f0095343ed9dd4f1d9f3825d7b3e45","author":{"name":"Nicholas Piggin","email":"f05c04607627fe5da053d74c5f6ef1dc9d849ab6@gmail.com"},"message":"powerpc/64: Fix placement of .text to be immediately following .head.text\n\nDo not introduce any additional alignment. Placement of text section\nwill be set by fixed section macros. Without this, output section\nalignment defaults to 4096, which makes BookE text section start at\n0x1000 when it is expected to start at 0x100.\n\nThis was introduced by commit 57f266497d81 (\"powerpc: Use gas sections\nfor arranging exception vectors\") and was caught with the scripted head\nsection checker (not yet merged).\n\nFixes: 57f266497d81 (\"powerpc: Use gas sections for arranging exception vectors\")\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/dadc4a1bb9f0095343ed9dd4f1d9f3825d7b3e45"},{"sha":"ef3263e35e26eb1061260131c4d6d579eea21f85","author":{"name":"Linus Torvalds","email":"ead7104581934751970e9decb2db5deb20a9e407@linux-foundation.org"},"message":"Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6\n\nPull crypto fixes from Herbert Xu:\n \"This fixes the following issues:\n\n   - Intermittent build failure in RSA\n\n   - Memory corruption in chelsio crypto driver\n\n   - Regression in DRBG due to vmalloced stack\"\n\n* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:\n  crypto: rsa - Add Makefile dependencies to fix parallel builds\n  crypto: chcr - Fix memory corruption\n  crypto: drbg - prevent invalid SG mappings","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/ef3263e35e26eb1061260131c4d6d579eea21f85"},{"sha":"d9d04527c79f0f7d9186272866526e871ef4ac6f","author":{"name":"Linus Torvalds","email":"ead7104581934751970e9decb2db5deb20a9e407@linux-foundation.org"},"message":"Merge tag 'powerpc-4.9-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux\n\nPull powerpc fixes from Michael Ellerman:\n \"Four fixes, the first for code we merged this cycle and three that are\n  also going to stable:\n\n   - On 64-bit Book3E we were not placing the .text section where we\n     said we would in the asm.\n\n   - We broke building the boot wrapper on some 32-bit toolchains.\n\n   - Lazy icache flushing was broken on pre-POWER5 machines.\n\n   - One of the error paths in our EEH code would lead to a deadlock.\n\n  Thanks to: Andrew Donnellan, Ben Hutchings, Benjamin Herrenschmidt,\n  Nicholas Piggin\"\n\n* tag 'powerpc-4.9-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:\n  powerpc/64: Fix placement of .text to be immediately following .head.text\n  powerpc/eeh: Fix deadlock when PE frozen state can't be cleared\n  powerpc/mm: Fix lazy icache flush on pre-POWER5\n  powerpc/boot: Fix build failure in 32-bit boot wrapper","distinct":true,"url":"https://api.github.com/repos/torvalds/linux/commits/d9d04527c79f0f7d9186272866526e871ef4ac6f"}]}
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