{"push_id":1219077168,"size":1,"distinct_size":1,"ref":"refs/heads/improved","head":"9dcd2c98f58eb94ac7f321dc4e1a1c6b58647156","before":"ed1486c9d9f34b78136f1e3801267796456faff6","commits":[{"sha":"9dcd2c98f58eb94ac7f321dc4e1a1c6b58647156","author":{"name":"Peromage","email":"908b20e990b6062499e26270020dd1c0cf9ba6a0@outlook.com"},"message":"separate ram dumping and register dumping","distinct":true,"url":"https://api.github.com/repos/Peromage/Verilog_Practice/commits/9dcd2c98f58eb94ac7f321dc4e1a1c6b58647156"}]}
{"actor":{"display_login":"Peromage"}}