{"action":"created","issue":{"url":"https://api.github.com/repos/chipsec/chipsec/issues/110","repository_url":"https://api.github.com/repos/chipsec/chipsec","labels_url":"https://api.github.com/repos/chipsec/chipsec/issues/110/labels{/name}","comments_url":"https://api.github.com/repos/chipsec/chipsec/issues/110/comments","events_url":"https://api.github.com/repos/chipsec/chipsec/issues/110/events","html_url":"https://github.com/chipsec/chipsec/pull/110","id":184140446,"number":110,"title":"Modify SPI Protected Range Masks to ignore reserved bits","user":{"login":"timevortex","id":9387602,"avatar_url":"https://avatars.githubusercontent.com/u/9387602?v=3","gravatar_id":"","url":"https://api.github.com/users/timevortex","html_url":"https://github.com/timevortex","followers_url":"https://api.github.com/users/timevortex/followers","following_url":"https://api.github.com/users/timevortex/following{/other_user}","gists_url":"https://api.github.com/users/timevortex/gists{/gist_id}","starred_url":"https://api.github.com/users/timevortex/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/timevortex/subscriptions","organizations_url":"https://api.github.com/users/timevortex/orgs","repos_url":"https://api.github.com/users/timevortex/repos","events_url":"https://api.github.com/users/timevortex/events{/privacy}","received_events_url":"https://api.github.com/users/timevortex/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2016-10-20T05:46:58Z","updated_at":"2016-10-26T07:19:44Z","closed_at":null,"pull_request":{"url":"https://api.github.com/repos/chipsec/chipsec/pulls/110","html_url":"https://github.com/chipsec/chipsec/pull/110","diff_url":"https://github.com/chipsec/chipsec/pull/110.diff","patch_url":"https://github.com/chipsec/chipsec/pull/110.patch"},"body":"The current masks include reserved bits for calculations when they shouldn't be included according to the documentation. Bit 30:29 and bit 14:13 are reserved according to \"21.1.13 PR0—Protected Range 0 Register\" on page 730 of http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8-series-chipset-pch-datasheet.pdf\r\n\r\nOnly Bit 16:28 should be exposed from PCH_RCBA_SPI_PR0_PRL_MASK:\r\n- Old = 0x7FFF0000 = 0111 1111 1111 1111 0000 0000 0000 0000\r\n- New = 0x1FFF0000 = 0001 1111 1111 1111 0000 0000 0000 0000\r\n\r\nOnly bit 0:12 should be exposed from PCH_RCBA_SPI_PR0_PRB_MASK:\r\n- Old = 0x00007FFF = 0000 0000 0000 0000 01111 1111 1111 1111\r\n- New = 0x00001FFF = 0000 0000 0000 0000 0001 1111 1111 1111"},"comment":{"url":"https://api.github.com/repos/chipsec/chipsec/issues/comments/256268677","html_url":"https://github.com/chipsec/chipsec/pull/110#issuecomment-256268677","issue_url":"https://api.github.com/repos/chipsec/chipsec/issues/110","id":256268677,"user":{"login":"c7zero","id":6956764,"avatar_url":"https://avatars.githubusercontent.com/u/6956764?v=3","gravatar_id":"","url":"https://api.github.com/users/c7zero","html_url":"https://github.com/c7zero","followers_url":"https://api.github.com/users/c7zero/followers","following_url":"https://api.github.com/users/c7zero/following{/other_user}","gists_url":"https://api.github.com/users/c7zero/gists{/gist_id}","starred_url":"https://api.github.com/users/c7zero/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/c7zero/subscriptions","organizations_url":"https://api.github.com/users/c7zero/orgs","repos_url":"https://api.github.com/users/c7zero/repos","events_url":"https://api.github.com/users/c7zero/events{/privacy}","received_events_url":"https://api.github.com/users/c7zero/received_events","type":"User","site_admin":false},"created_at":"2016-10-26T07:19:44Z","updated_at":"2016-10-26T07:19:44Z","body":"This issue is also resolved by PR #114 . I'd like to get rid of PCH_RCBA_SPI_PR0_PRL_MASK/PCH_RCBA_SPI_PR0_PRB_MASK constants at all. When using XML config, chipsec.chipset.get_register_field( self.cs, pr_name, pr_j, 'PRB' ) will take care of the size of the PRB field. Same with PRL."}}
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