{"push_id":1056175743,"size":4,"distinct_size":4,"ref":"refs/heads/devel","head":"9f1219194a456f45643ed775ba6fa378ddfb42c1","before":"c2d0be4b5394d9fe7b7adc401820a1869807ea29","commits":[{"sha":"9a1270f40150fc6822d19aae1dd9a6639232d1fb","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":"modules/*/wb_acq_core/*: optimize FSM counters to pass 250MHz constraint\n\nThis basically changes the counter to bottom-up,\ninstead of top-down, better distributes the\noperations on clock cycle (manual retiming) and\ncut some asynchronous paths.","distinct":true,"url":"https://api.github.com/repos/lnls-dig/bpm-gw/commits/9a1270f40150fc6822d19aae1dd9a6639232d1fb"},{"sha":"4aa25ba33e526aba364ca1a446fb257088b5ae8b","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":"testbench/*/wb_acq_core_test/**/*: enlarge DDR3 mem space for TEST #16\n\nThis is necessary so we avoid dealing with\nDDR3 address wraparound issues with trigger tests\nin simulation. This is done in software and not\nsimulated here. Hopefully, one day, this test will\nbe incorporated here.","distinct":true,"url":"https://api.github.com/repos/lnls-dig/bpm-gw/commits/4aa25ba33e526aba364ca1a446fb257088b5ae8b"},{"sha":"d6f254ecba41e967ff3a602cce138c5971e33028","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":"syn/afc_v3/*/dbe_bpm2/*: change all IP cores to -2 speed grade","distinct":true,"url":"https://api.github.com/repos/lnls-dig/bpm-gw/commits/d6f254ecba41e967ff3a602cce138c5971e33028"},{"sha":"9f1219194a456f45643ed775ba6fa378ddfb42c1","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":" syn/afc_v3/*/dbe_bpm2/*: use phys_opt_design with retiming option\n\nThis option gives us timing closure without\nincreasing \"too much\" of the implementation\ntime: increase from 30 minutes to 60 minutes.\n\nThis must be fixed in later commits when\nthe difficult paths should be relaxed. Basically\nthe following regs (wb_acq_core) are problematic:\n\n1) Counters \"pre_trig_cnt\" and \"post_trig_cnt\"\n   located in acq_fsm module\n2) Counter \"fifo_valid_in_cnt\" locate in\n   acq_fc_fifo module","distinct":true,"url":"https://api.github.com/repos/lnls-dig/bpm-gw/commits/9f1219194a456f45643ed775ba6fa378ddfb42c1"}]}