{"push_id":1191335119,"size":9,"distinct_size":9,"ref":"refs/heads/master","head":"fbf73dc674a46bfdb3b58cb5c2f2daafe2c80fcd","before":"9f3e6f672ff426158f8a67578c35f6a4bc0c54fc","commits":[{"sha":"6af925d002e4d3bbcf678021791fef8887f0ad70","author":{"name":"Zachary Turner","email":"8eb50e0e9adf1181ea7c0e90037815a870ea54ae@google.com"},"message":"Disable hash verification of enums.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274639 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/6af925d002e4d3bbcf678021791fef8887f0ad70"},{"sha":"380cae497782b82876b95c1b264705ef2cab4c06","author":{"name":"Zachary Turner","email":"8eb50e0e9adf1181ea7c0e90037815a870ea54ae@google.com"},"message":"Add a default parameter for getRegisteredOptions.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274640 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/380cae497782b82876b95c1b264705ef2cab4c06"},{"sha":"27d0b07d7374c27267a3c43c58cfa10ea16b4519","author":{"name":"Michael Kuperstein","email":"03ce15697219703fd50a2fdabb7e1a0083bf664b@google.com"},"message":"[TTI] The cost model should not assume vector casts get completely scalarized\n\nThe cost model should not assume vector casts get completely scalarized, since\non targets that have vector support, the common case is a partial split up to\nthe legal vector size. So, when a vector cast  gets split, the resulting casts\nend up legal and cheap.\n\nInstead of pessimistically assuming scalarization, base TTI can use the costs\nthe concrete TTI provides for the split vector, plus a fudge factor to account\nfor the cost of the split itself. This fudge factor is currently 1 by default,\nexcept on AMDGPU where inserts and extracts are considered free.\n\nDifferential Revision: http://reviews.llvm.org/D21251\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274642 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/27d0b07d7374c27267a3c43c58cfa10ea16b4519"},{"sha":"b1fd7784581ea9745b78e66f3d3287d3388b29c5","author":{"name":"Tim Shen","email":"27d4088a4e3928abba38098f2c71c2e0f4440135@gmail.com"},"message":"[DAGCombiner] Fix visitSTORE to continue processing current SDNode, if findBetterNeighborChains doesn't actually CombineTo it.\n\nSummary:\nfindBetterNeighborChains may or may not find a better chain for each node it finds, which include the node (\"St\") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed.\n\nThis fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase.\n\nReviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner\n\nSubscribers: mehdi_amini, nemanjai, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D21692\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274644 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/b1fd7784581ea9745b78e66f3d3287d3388b29c5"},{"sha":"e01e124d9577d35e64630c94b5efb566b2bd1d4f","author":{"name":"Kit Barton","email":"44c3dd063bf7332d624069108ab960dd93b80add@ca.ibm.com"},"message":"Ensure all uses of permute instructions feed vector stores\n\nThere is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions.\nIn this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed.\n\nThe fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions.\n\nThis problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735).\n\nTest case based on the original problem reported.\n\nPhabricator Review: http://reviews.llvm.org/D21802\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274645 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/e01e124d9577d35e64630c94b5efb566b2bd1d4f"},{"sha":"57794acb8818579be99db993a6f59f91c06f74e4","author":{"name":"Zachary Turner","email":"8eb50e0e9adf1181ea7c0e90037815a870ea54ae@google.com"},"message":"[pdb] Round trip the PDB stream between YAML and binary PDB.\n\nThis gets writing of the PDB stream working.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274647 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/57794acb8818579be99db993a6f59f91c06f74e4"},{"sha":"72d1f349152a816d33da855667f4f3a9e62ac22c","author":{"name":"Simon Pilgrim","email":"db8c5b2fddd32fdb1f502114e8f7338e95f99ca1@redking.me.uk"},"message":"[X86][SSE] Fixed typo in insertps lowering.\n\nWe were checking for 2 insertions (which is caught earlier in the pattern matching loop) instead of the case where we have no insertions.\n\nTurns out this code never fires as we always try to lower to insertps after trying to lower to blendps, which would catch these cases - I'm about to make some changes to support combining to insertps which could cause this to fire so I don't want to remove it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274648 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/72d1f349152a816d33da855667f4f3a9e62ac22c"},{"sha":"02e45e22bcb63bc2fab03b1b86257b8ac31533e1","author":{"name":"Piotr Padlewski","email":"7a667d16a784fbec23ae60ea955c0b41d612d665@google.com"},"message":"NFC changed names in FunctionImport\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274649 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/02e45e22bcb63bc2fab03b1b86257b8ac31533e1"},{"sha":"fbf73dc674a46bfdb3b58cb5c2f2daafe2c80fcd","author":{"name":"Elliot Colp","email":"826a0768ed41babef7eb9783730c95b8331d96f6@ca.ibm.com"},"message":"[SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotate\n\nOn SystemZ, shift and rotate instructions only use the bottom 6 bits of the shift/rotate amount.\nTherefore, if the amount is ANDed with an immediate mask that has all of the bottom 6 bits set, we\ncan remove the AND operation entirely.\n\nDifferential Revision: http://reviews.llvm.org/D21854\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274650 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/fbf73dc674a46bfdb3b58cb5c2f2daafe2c80fcd"}]}
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