{"push_id":1321856929,"size":5,"distinct_size":5,"ref":"refs/heads/master","head":"8ae53e7b23e7b2b9268ee5de1d65956994009593","before":"c954c90b6e915e123b04d45197cc34cc149131a4","commits":[{"sha":"09233125e108ad981709ac4d19574685ad24fd0f","author":{"name":"Dylan McKay","email":"88a58bf7623d66efc60922202f3be402a5945864@gmail.com"},"message":"[AVR] Add AVRMCTargetDesc.cpp\n\nSummary:\nThis adds the AVRMCTargetDesc file in tree. It allows creation of the\ncore classes used in the backend.\n\nReviewers: arsenm, kparzysz\n\nSubscribers: wdng, beanz, mgorny\n\nDifferential Revision: https://reviews.llvm.org/D25023\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282597 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/09233125e108ad981709ac4d19574685ad24fd0f"},{"sha":"656d7617820cedf63c69fec024553e10f39ac069","author":{"name":"Dylan McKay","email":"88a58bf7623d66efc60922202f3be402a5945864@gmail.com"},"message":"[AVR] Import the LLVM namespace inside AVRMCTargetDesc.cpp\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282598 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/656d7617820cedf63c69fec024553e10f39ac069"},{"sha":"dc6ef6788d5f10dc9420e58880e7a0e217d47613","author":{"name":"Nirav Dave","email":"e5fe09cb04eb873e6b01e3b4b0812f816df536f9@google.com"},"message":"In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.\n\n  Simplify Consecutive Merge Store Candidate Search\n\n  Now that address aliasing is much less conservative, push through\n  simplified store merging search which only checks for parallel stores\n  through the chain subgraph. This is cleaner as the separation of\n  non-interfering loads/stores from the store-merging logic.\n\n  Whem merging stores, search up the chain through a single load, and\n  finds all possible stores by looking down from through a load and a\n  TokenFactor to all stores visited. This improves the quality of the\n  output SelectionDAG and generally the output CodeGen (with some\n  exceptions).\n\n  Additional Minor Changes:\n\n    1. Finishes removing unused AliasLoad code\n    2. Unifies the the chain aggregation in the merged stores across\n       code paths\n    3. Re-add the Store node to the worklist after calling\n       SimplifyDemandedBits.\n    4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is\n       arbitrary, but seemed sufficient to not cause regressions in\n       tests.\n\n  This finishes the change Matt Arsenault started in r246307 and\n  jyknight's original patch.\n\n  Many tests required some changes as memory operations are now\n  reorderable. Some tests relying on the order were changed to use\n  volatile memory operations\n\n  Noteworthy tests:\n\n    CodeGen/AArch64/argument-blocks.ll -\n      It's not entirely clear what the test_varargs_stackalign test is\n      supposed to be asserting, but the new code looks right.\n\n    CodeGen/AArch64/arm64-memset-inline.lli -\n    CodeGen/AArch64/arm64-stur.ll -\n    CodeGen/ARM/memset-inline.ll -\n      The backend now generates *worse* code due to store merging\n      succeeding, as we do do a 16-byte constant-zero store efficiently.\n\n    CodeGen/AArch64/merge-store.ll -\n      Improved, but there still seems to be an extraneous vector insert\n      from an element to itself?\n\n    CodeGen/PowerPC/ppc64-align-long-double.ll -\n      Worse code emitted in this case, due to the improved store->load\n      forwarding.\n\n    CodeGen/X86/dag-merge-fast-accesses.ll -\n    CodeGen/X86/MergeConsecutiveStores.ll -\n    CodeGen/X86/stores-merging.ll -\n    CodeGen/Mips/load-store-left-right.ll -\n      Restored correct merging of non-aligned stores\n\n    CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -\n      Improved. Correctly merges buffer_store_dword calls\n\n    CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -\n      Improved. Sidesteps loading a stored value and merges two stores\n\n    CodeGen/X86/pr18023.ll -\n      This test has been removed, as it was asserting incorrect\n      behavior. Non-volatile stores *CAN* be moved past volatile loads,\n      and now are.\n\n    CodeGen/X86/vector-idiv.ll -\n    CodeGen/X86/vector-lzcnt-128.ll -\n      It's basically impossible to tell what these tests are actually\n      testing. But, looks like the code got better due to the memory\n      operations being recognized as non-aliasing.\n\n    CodeGen/X86/win32-eh.ll -\n      Both loads of the securitycookie are now merged.\n\n    CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll -\n      This test appears to work but no longer exhibits the spill\n      behavior.\n\nReviewers: arsenm, hfinkel, tstellarAMD, nhaehnle, jyknight\n\nSubscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, resistor, tstellarAMD, t.p.northover, spatel\n\nDifferential Revision: https://reviews.llvm.org/D14834\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282600 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/dc6ef6788d5f10dc9420e58880e7a0e217d47613"},{"sha":"ee32aed4e9701e9a888932fde60b25284c663046","author":{"name":"Marina Yatsina","email":"af709bb6febfec324889647ca7f854f7ccb1a2d2@intel.com"},"message":"[x86] Accept 'retn' as an alias to 'ret[lqw]'\\'ret' (At&t\\Intel)\n\nImplement 'retn' simply by aliasing it to the relevant 'ret' instruction\n\nCommit on behalf of coby\n\nDifferential Revision: https://reviews.llvm.org/D24346\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282601 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/ee32aed4e9701e9a888932fde60b25284c663046"},{"sha":"8ae53e7b23e7b2b9268ee5de1d65956994009593","author":{"name":"Dylan McKay","email":"88a58bf7623d66efc60922202f3be402a5945864@gmail.com"},"message":"[AVR] Rename the builtin calling convention names\n\n'BUILTIN' is clearer than 'RT' in this context.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282602 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/8ae53e7b23e7b2b9268ee5de1d65956994009593"}]}
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