{"push_id":1468468528,"size":4,"distinct_size":4,"ref":"refs/heads/riscv-next","head":"8eb2dc553b7f7063677ccaee72352d783932a958","before":"fa9b560d6dfd291321ef4123830b68639b20a5df","commits":[{"sha":"87903eafb083abbf330c22fbf941fcbad700c098","author":{"name":"Jim Wilson","email":"15130754f79c0fca07c05e6312bf5e2defd41281@linaro.org"},"message":"Fix bugs with float compare and Inf operands.\n\n\tsim/aarch64/\n\t* simulator.c (set_flags_for_float_compare): Add code to handle Inf.\n\tAdd comment to document NaN issue.\n\t(set_flags_for_double_compare): Likewise.\n\n\tsim/testsuite/sim/aarch64/\n\t* fcmp.s: New.","distinct":true,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/87903eafb083abbf330c22fbf941fcbad700c098"},{"sha":"cb8604c57c4911f8d5deaaa48e6e084a09f4e6c4","author":{"name":"Palmer Dabbelt","email":"da5bafab56f66b7236a8991f0e01aad56ae901eb@dabbelt.com"},"message":"RISC-V GDB Port\n\nChangeLog:\n\n* New RISC-V GDB port","distinct":true,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/cb8604c57c4911f8d5deaaa48e6e084a09f4e6c4"},{"sha":"fa925c3f8dcb910024ad8ada9c885980dd50307d","author":{"name":"Palmer Dabbelt","email":"da5bafab56f66b7236a8991f0e01aad56ae901eb@dabbelt.com"},"message":"Add the RISC-V opcode generator\n\n[I'm not actually sure what to do here, so I'm open to suggestions]\n\nWe used a tool to generate include/riscv-opcodes/riscv-opc.h (as well as\nother formats of the RISC-V ISA encoding tables that aren't used by\nBinutils or GDB such as LaTeX).  The output from this tool was\noriginally committed, but it's better to have the tool that generates\nthis somewhere as well.  I believe there were comments about this on our\noriginal port patchset, but I must have forgotten about them at some\npoint, sorry!  It's lived at\n\n  http://www.github.com/riscv/riscv-opcodes/\n\nfor a while and will continue to remain there, I'll sync any changes\nbetween there and binutils.  I think this is the best model, since\nriscv-opcodes is used by multiple projects.  I looked and saw that other\nports have opcode generators and run them manually, so I've only added a\nREADME to describe how this is run.\n\nopcodes/ChangeLog\n\n2016-12-21  Palmer Dabbelt <palmer@dabbelt.com>\n\n        * riscv-opcodes/.gitignore: New file.\n        * riscv-opcodes/README: Likewise.\n        * riscv-opcodes/all-opcodes: Likewise.\n        * riscv-opcodes/parse-opcodes: Likewise.","distinct":true,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/fa925c3f8dcb910024ad8ada9c885980dd50307d"},{"sha":"8eb2dc553b7f7063677ccaee72352d783932a958","author":{"name":"Kito Cheng","email":"f93772bc21b5d952128864918dec866e61c263ac@gmail.com"},"message":"Add Q extension, regenerate from riscv-opcodes\n\nAdd support for the RISC-V Q extension\n\nThe RISC-V ISA manual defines a Q instruction set extension that enables\nhardware support for quad precision IEEE floating point.  This patch\nenables support for the Q extension: it declares the Q instruction\nencoding macros, adds support for the various Q instructions to the\nencoding table, whitelists \"q\" as an ISA extension, and sets\nFLOAT_ABI_QUAD when the Q extension is enabled.\n\ngas/ChangeLog\n\n2016-12-21  Kito Cheng <kito.cheng@gmail.com>\n\n        * config/tc-riscv.c (riscv_set_arch): Whitelist the \"q\" ISA\n        extension.\n        (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is\n        enabled and no other ABI is specified.\n\ninclude/ChangeLog\n\n2016-12-21  Kito Cheng <kito.cheng@gmail.com>\n\n        * opcode/riscv-opc.h: Regenerated.\n\nopcodes/ChangeLog\n\n2016-12-21  Kito Cheng <kito.cheng@gmail.com>\n\n        * opcodes/riscv-opc.c (riscv-opcodes): Add support for the \"q\" ISA\n        extension.","distinct":true,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/8eb2dc553b7f7063677ccaee72352d783932a958"}]}
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