{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/549","repository_url":"https://api.github.com/repos/ucb-bar/chisel","labels_url":"https://api.github.com/repos/ucb-bar/chisel/issues/549/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel/issues/549/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel/issues/549/events","html_url":"https://github.com/ucb-bar/chisel/issues/549","id":108501952,"number":549,"title":"Support for asynchronous resets in Verilog backend","user":{"login":"jwright6323","id":463543,"avatar_url":"https://avatars.githubusercontent.com/u/463543?v=3","gravatar_id":"","url":"https://api.github.com/users/jwright6323","html_url":"https://github.com/jwright6323","followers_url":"https://api.github.com/users/jwright6323/followers","following_url":"https://api.github.com/users/jwright6323/following{/other_user}","gists_url":"https://api.github.com/users/jwright6323/gists{/gist_id}","starred_url":"https://api.github.com/users/jwright6323/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jwright6323/subscriptions","organizations_url":"https://api.github.com/users/jwright6323/orgs","repos_url":"https://api.github.com/users/jwright6323/repos","events_url":"https://api.github.com/users/jwright6323/events{/privacy}","received_events_url":"https://api.github.com/users/jwright6323/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/ucb-bar/chisel/labels/Feature%20Request","name":"Feature Request","color":"ededed"},{"url":"https://api.github.com/repos/ucb-bar/chisel/labels/Verilog%20backend","name":"Verilog backend","color":"bfdadc"}],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-09-26T23:18:30Z","updated_at":"2016-02-08T09:48:25Z","closed_at":null,"body":"It appears that Chisel does not support asynchronous resets. Can you add an option to use asynchronous resets in generated Verilog? This would help with our pin-limited designs (among others). An option to select the polarity of reset would also be useful, as most libraries only contain flops with active-low async reset/set pins.\r\n\r\nThanks,\r\nJohn"},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/comments/181280802","html_url":"https://github.com/ucb-bar/chisel/issues/549#issuecomment-181280802","issue_url":"https://api.github.com/repos/ucb-bar/chisel/issues/549","id":181280802,"user":{"login":"mcieplucha","id":16589813,"avatar_url":"https://avatars.githubusercontent.com/u/16589813?v=3","gravatar_id":"","url":"https://api.github.com/users/mcieplucha","html_url":"https://github.com/mcieplucha","followers_url":"https://api.github.com/users/mcieplucha/followers","following_url":"https://api.github.com/users/mcieplucha/following{/other_user}","gists_url":"https://api.github.com/users/mcieplucha/gists{/gist_id}","starred_url":"https://api.github.com/users/mcieplucha/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mcieplucha/subscriptions","organizations_url":"https://api.github.com/users/mcieplucha/orgs","repos_url":"https://api.github.com/users/mcieplucha/repos","events_url":"https://api.github.com/users/mcieplucha/events{/privacy}","received_events_url":"https://api.github.com/users/mcieplucha/received_events","type":"User","site_admin":false},"created_at":"2016-02-08T09:48:25Z","updated_at":"2016-02-08T09:48:25Z","body":"Hello,\r\n\r\nPlease find some comments how asynchronous resets in generated code should be implemented, to make sure that ASIC synthesis rules are not violated.\r\n\r\n1. In the design resettable and non-resettable flops may exist together. It is important that these flops are described in separated ```always``` blocks.\r\n2. The asynchronous reset condition must be the very first in the ```always``` block and it must constain only reset signal (e.g. ```if (rst)``` or ```if (~rst_n)```).\r\n3. Asynchronous reset signal should not be used for any logic outside ```always``` block (e.g. ```assign a = (rst) ? 1'b0 : b;``` is prohibited).\r\n4. Reset polarity selection option is welcome, please note it is highly unlikely that both polarities coexist in single design. \r\n\r\nBelow is an example how generated code should look like:\r\n```verilog\r\nalways @(posedge clk or negedge rst_n)\r\nbegin\r\n  if (~rst_n) begin //async-resettable flops\r\n    flop1 <= FLOP1_RESET_VALUE;\r\n    flop2 <= FLOP2_RESET_VALUE;\r\n    //all async resettable flops\r\n  end else //other conditions\r\nend\r\n\r\nalways @(posedge clk)\r\nbegin\r\n  if (rst) begin //sync-resettable flops (rst may be a local signal or any condition)\r\n    flopA <= FLOPA_RESET_VALUE;\r\n    flopB <= FLOPB_RESET_VALUE;\r\n    //all other flops\r\n  end else //other conditions\r\n    //...\r\n  flopC <= flopC_next; //this flop has no sync or async reset\r\nend\r\n```\r\n\r\nRegards,\r\nMarek Ciepłucha\r\n\r\n\r\n\r\n\r\n\r\n\r\n"}}