{"push_id":1003111926,"size":1000,"distinct_size":1360,"ref":"refs/heads/jenkins","head":"772306c7f67b2030dd3a29c5722b2f727e247f4a","before":"19e25bf76bc43097b7325a8921e2d72a0102c65b","commits":[{"sha":"3038e8984df2be35a7164043ec6d385e32e26238","author":{"email":"67ce69700661ea856134ddb10419a330e5f037d7@vmware.com","name":"Charmaine Lee"},"message":"gallium/st: add pipe_context::generate_mipmap()\n\nThis patch adds a new interface to support hardware mipmap generation.\nPIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify\nif this new interface is supported; if not supported, the state tracker will\nfallback to mipmap generation by rendering/texturing.\n\nv2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers\nv3: add format to the generate_mipmap interface to allow mipmap generation\n    using a format other than the resource format\nv4: fix return type of trace_context_generate_mipmap()\n\nReviewed-by: Brian Paul <brianp@vmware.com>\nReviewed-by: Roland Scheidegger <sroland@vmware.com>\nReviewed-by: Jose Fonseca <jfonseca@vmware.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/3038e8984df2be35a7164043ec6d385e32e26238"},{"sha":"78e628ae43015a2a8b6a1d7339eb7eb63ab56848","author":{"email":"67ce69700661ea856134ddb10419a330e5f037d7@vmware.com","name":"Charmaine Lee"},"message":"svga: add num-generate-mipmap HUD query\n\nThe actual increment of the num-generate-mipmap counter will be done\nin a subsequent patch when hw generate mipmap is supported.\n\nReviewed-by: Brian Paul <brianp@vmware.com>\nReviewed-by: Jose Fonseca <jfonseca@vmware.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/78e628ae43015a2a8b6a1d7339eb7eb63ab56848"},{"sha":"6303231a1ddf646b05c43c6bbc7fa71314ebb3fc","author":{"email":"67ce69700661ea856134ddb10419a330e5f037d7@vmware.com","name":"Charmaine Lee"},"message":"svga: add DXGenMips command support\n\nFor those formats that support hw mipmap generation, use the\nDXGenMips command. Otherwise fallback to the mipmap generation utility.\n\nTested with piglit, OpenGL apps (Heaven, Turbine, Cinebench)\n\nv2: make sure the texture surface was created with the render target bind flag\n    set relocation flag to SVGA_RELOC_WRITE for the texture surface\n\nReviewed-by: Brian Paul <brianp@vmware.com>\nReviewed-by: Jose Fonseca <jfonseca@vmware.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/6303231a1ddf646b05c43c6bbc7fa71314ebb3fc"},{"sha":"dc96a18d24409102e36cdfd7de0552f66c3925bf","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"radeonsi: don't miss changes to SPI_TMPRING_SIZE\n\nI'm not sure about the consequences of this bug, but it's definitely\ndangerous.\n\nThis applies to SI, CIK, VI.\n\nCc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/dc96a18d24409102e36cdfd7de0552f66c3925bf"},{"sha":"e94ef885bb71b46aba4517523ebb63c0d4b36c4b","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"st/mesa: use surface format to generate mipmaps when available\n\nThis fixes the recently posted mipmap + texture views piglit test.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nCc: \"11.0 11.1\" <mesa-stable@lists.freedesktop.org>\nReviewed-by: Roland Scheidegger <sroland@vmware.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/e94ef885bb71b46aba4517523ebb63c0d4b36c4b"},{"sha":"7a521ddf36b3d1f7b81604341fcda26c60809c9b","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nvc0: allow fragment shader inputs to use indirect indexing\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/7a521ddf36b3d1f7b81604341fcda26c60809c9b"},{"sha":"37b67db6ae34fb6586d640a7a1b6232f091dd812","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nvc0/ir: be careful about propagating very large offsets into const load\n\nIndirect constbuf indexing works by using very large offsets. However if\nan indirect constbuf index load is const-propagated, it becomes a very\nlarge const offset. Take that into account when legalizing the SSA by\nmoving the high parts of that offset into the file index. Also disallow\nvery large (or small) indices on most other instructions.\n\nThis fixes regressions in ubo_array_indexing/*-two-arrays piglit tests.\n\nFixes: abd326e81b (nv50/ir: propagate indirect loads into instructions)\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/37b67db6ae34fb6586d640a7a1b6232f091dd812"},{"sha":"e231f59b6d5b12035a8041305c3a732d39a39c19","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nv50/ir: only use FILE_LOCAL_MEMORY for temp arrays that use indirection\n\nPreviously we were treating any indirect temp array usage to mean that\neverything should end up in lmem. The MemoryOpt pass would clean a lot\nof that up later, but in the meanwhile we would lose a lot of\nopportunity for optimization.\n\nThis helps a lot of Metro 2033 Redux and a handful of KSP shaders:\n\ntotal instructions in shared programs : 6288373 -> 6261517 (-0.43%)\ntotal gprs used in shared programs    : 944051 -> 945131 (0.11%)\ntotal local used in shared programs   : 54116 -> 54116 (0.00%)\n\nA typical case is for register usage to double and for instructions to\nhalve. A future commit can also optimize local memory usage size to be\nreduced with better packing.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/e231f59b6d5b12035a8041305c3a732d39a39c19"},{"sha":"fffb559129dd1ae978ec7f9ba30b4ae97a5ebbcc","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nv50/ir: rebase indirect temp arrays to 0, so that we use less lmem space\n\nReduces local memory usage in a lot of Metro 2033 Redux and a few KSP\nshaders:\n\ntotal local used in shared programs   : 54116 -> 30372 (-43.88%)\n\nProbably modest advantage to execution, but it's an imporant\nprerequisite to dropping some of the TGSI optimizations done by the\nstate tracker.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/fffb559129dd1ae978ec7f9ba30b4ae97a5ebbcc"},{"sha":"22ac1f692228d8c44155bfa637c8e34356c7e0b7","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965: Add state bit to trigger re-emission of color calculator state.\n\nThis will be used on Gen8+ to make sure that the color calculator\nstate pointers are re-emitted when switching back to the 3D pipeline\nafter some GPGPU workload due to a hardware workaround.  There are\nother state bits already defined that could be used to achieve the\nsame effect but they all cause a ton of unrelated state to be\nre-emitted (e.g. BRW_NEW_STATE_BASE_ADDRESS), so just define a new\none, state bits are cheap.\n\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/22ac1f692228d8c44155bfa637c8e34356c7e0b7"},{"sha":"044acb9256046bebec890cac7e42043754459fc2","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.\n\nThis hardware bug can cause a hang on context restore while the\ncurrent pipeline is set to GPGPU (BDWGFX HSD 1909593).  In addition to\nclearing the valid bit, mark the CC state as dirty to make sure that\nthe CC indirect state pointer is re-emitted when we switch back to the\n3D pipeline.\n\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/044acb9256046bebec890cac7e42043754459fc2"},{"sha":"18c76551ee425b981efefc61f663a7781df17882","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen6-7: Implement stall and flushes required prior to switching pipelines.\n\nSwitching the current pipeline while it's not completely idle or the\nread and write caches aren't flushed can lead to corruption.  Fixes\nmisrendering of at least the following Khronos CTS test:\n\n ES31-CTS.shader_image_load_store.basic-allTargets-store-fs\n\nThe stall and flushes are no longer required on Gen8+.\n\nv2: Emit PIPE_CONTROL with non-zero post-sync op before the write\n    cache flush on SNB due to hardware bug. (Ken)\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93323\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/18c76551ee425b981efefc61f663a7781df17882"},{"sha":"635be1402c485b154ab1bf23e5448827364e70a5","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.\n\nAFAIK brw_emit_select_pipeline() is only called once during context\ninit on Gen4-5, at which point the pipeline is likely to be already\nidle so it may just happen to work by luck regardless of the MI_FLUSH.\n\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/635be1402c485b154ab1bf23e5448827364e70a5"},{"sha":"c8df0e7bf35cbab649c8d0e0205746293e686ce3","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipeline.\n\nThis hardware bug can supposedly lead to a hang on IVB and VLV.\n\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/c8df0e7bf35cbab649c8d0e0205746293e686ce3"},{"sha":"0556b87de4302195402ade43f400e859d9bfad0e","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen7.5+: Disable resource streamer during GPGPU workloads.\n\nThe RS and hardware binding tables are only supported on the 3D\npipeline and can lead to corruption if left enabled during a GPGPU\nworkload.  Disable it when switching to the GPGPU (or media) pipeline\nand re-enable it when switching back to the 3D pipeline.\n\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/0556b87de4302195402ade43f400e859d9bfad0e"},{"sha":"cf96bce0ca8b2d6b5d4641efea1f2feedc024957","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"glsl: mark explicit uniforms as explicit in other stages too\n\nIf shader declares uniform explicit location in one stage but\nimplicit in another, explicit location should be used. Patch marks\nimplicit uniforms as explicit if they were explicit in previous stage.\nThis makes sure that we don't treat them implicit later when assigning\nlocations.\n\nFixes following CTS test:\n   ES31-CTS.explicit_uniform_location.uniform-loc-implicit-in-some-stages3\n\nv2: move check to cross_validate_globals (Timothy)\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nReviewed-by: Timothy Arceri <timothy.arceri@collabora.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/cf96bce0ca8b2d6b5d4641efea1f2feedc024957"},{"sha":"bb6612f06b8320911d9f86f7463f823e76969f15","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"nir/builder: Add a nir_build_ivec4() convenience helper.\n\nnir_build_ivec4 is more readable and succinct than using nir_build_imm\ndirectly, even if you have C99.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/bb6612f06b8320911d9f86f7463f823e76969f15"},{"sha":"824d82025d0bff9841647942aca501fba16fc1a9","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"i965: Make an is_scalar boolean in brw_compile_vs().\n\nShorter than compiler->scalar_stage[MESA_SHADER_VERTEX], which can\nhelp with line-wrapping.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/824d82025d0bff9841647942aca501fba16fc1a9"},{"sha":"a3500f943e2c61c0aed043108132f35b79d16676","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"i965: Make add_const_offset_to_base() work at the shader level.\n\nThis makes it a pass, hiding the parameter structs and block callbacks\nso it's simpler to work with.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/a3500f943e2c61c0aed043108132f35b79d16676"},{"sha":"3657cbf24f3b0baf7e3382e572d97a36b0ed4103","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"i965: Apply add_const_offset_to_base for vec4 VS inputs too.\n\nThis shouldn't hurt anything, and I'm about to introduce a pass that\nwill want it.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/aphogat/mesa/commits/3657cbf24f3b0baf7e3382e572d97a36b0ed4103"}]}