{"push_id":922530193,"size":43,"distinct_size":43,"ref":"refs/heads/master","head":"5512b9a18d09102353a0548273c413340fe3b8ff","before":"7321e3fb3d6015e51bcfb207d4236e6768c86b1e","commits":[{"sha":"f124911f7a6ec79c44e71a3dccac8733c8ded458","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[X86] Make hasFP constant time\n\nWe need a frame pointer if there is a push/pop sequence after the\nprologue in order to unwind the stack.  Scanning the instructions to\nfigure out if this happened made hasFP not constant-time which is a\nviolation of expectations.  Let's compute this up-front and reuse that\ncomputation when we need it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256730 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/f124911f7a6ec79c44e71a3dccac8733c8ded458"},{"sha":"d149f59b51ee20d6ce0862d338dc4cfe172dd8ff","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[TableGen] Call llvm_shutdown on exit so that all the ManagedStatic objects in the support library will be deleted.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256732 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/d149f59b51ee20d6ce0862d338dc4cfe172dd8ff"},{"sha":"d8f59233d2bc9587950e22ed5294db6e9f1c9128","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[TableGen] Use some free space in Init to store the opcode for UnOpInit/BinOpInit/TernOpInit allowing those types to be a little smaller. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256733 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/d8f59233d2bc9587950e22ed5294db6e9f1c9128"},{"sha":"15d448c8644faec5904d8a66e4a8b24642248a14","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[TableGen] Fix a typo in r256733.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256734 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/15d448c8644faec5904d8a66e4a8b24642248a14"},{"sha":"ab99ec2ce71849d1976ac7497f671375a1900e97","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"Fix a horrible infloop in value tracking in the face of dead code.\n\nAmazingly, we just never triggered this without:\n1) Moving code around for MetadataTracking so that a certain *different*\n   amount of inlining occurs in the per-TU compile step.\n2) Then you LTO opt or clang with a bootstrap, and get inlining, loop\n   opts, and GVN line up everything *just* right.\n\nI don't really know how we didn't hit this before. We really need to be\nfuzz testing stuff, it shouldn't be hard to trigger. I'm working on\ncrafting a reduced nice test case, and will submit that when I have it,\nbut I want to get LTO build bots going again.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256735 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/ab99ec2ce71849d1976ac7497f671375a1900e97"},{"sha":"5b63de585b08b57632f5d80b2f1d133832e3e7f9","author":{"email":"74fee5f3d07282e9888d45848bd706a1b49fb0e6@intel.com","name":"Michael Zuckerman"},"message":"[AVX512] add PSRLV Intrinsic \n\nDifferential Revision: http://reviews.llvm.org/D15838\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256747 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/5b63de585b08b57632f5d80b2f1d133832e3e7f9"},{"sha":"0abac95f653ee93aabbb0c800701923f8f99eafd","author":{"email":"845dfb253b44f3c1b7a81c92ce834192f783cf87@imperial.ac.uk","name":"Jeroen Ketema"},"message":"[MC] Fix file name in file header\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256749 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/0abac95f653ee93aabbb0c800701923f8f99eafd"},{"sha":"ab0aa0e9d923296cd0e373d98b8586fe314b87f6","author":{"email":"74fee5f3d07282e9888d45848bd706a1b49fb0e6@intel.com","name":"Michael Zuckerman"},"message":"[AVX512] add PSRAW Intrinsic \n\nDifferential Revision: http://reviews.llvm.org/D15850\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256751 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/ab0aa0e9d923296cd0e373d98b8586fe314b87f6"},{"sha":"09816bb5493ff7d0645dc5b254a18a6c0d0a4078","author":{"email":"74fee5f3d07282e9888d45848bd706a1b49fb0e6@intel.com","name":"Michael Zuckerman"},"message":"[AVX512] add PSRAD and PSRAQ Intrinsic\n\nDifferential Revision: http://reviews.llvm.org/D15851\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256754 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/09816bb5493ff7d0645dc5b254a18a6c0d0a4078"},{"sha":"98732e397c55abc7a214dd2d4f09a08a24382f35","author":{"email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com","name":"Nicolai Haehnle"},"message":"AMDGPU: Avoid assertions after SGPR spilling failed\n\nSummary:\nThe comment explains it: emitError does not necessarily exit the compilation\nprocess, and then using NoRegister leads to assertions later on.\nThis generates incorrect code, of course, but the user should know to not use\nthe result when an error has been emitted.\n\nIt would be nice to have a test-case for this inside the LLVM repository,\nbut llc exits on error. shader-db tests trigger the underlying issue at least\non Tonga.\n\nReviewers: arsenm, tstellarAMD, mareko\n\nSubscribers: arsenm, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D15826\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256757 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/98732e397c55abc7a214dd2d4f09a08a24382f35"},{"sha":"7f410b17a792c624d2b939fa56285f8eb8cba184","author":{"email":"25bde77e144fcca55ce01543af70cbcf516b8a17@microsoft.com","name":"Joseph Tremoulet"},"message":"[WinEH] Update CoreCLR EH state numbering\n\nSummary:\nFix the CLR state numbering to generate correct tables, and update the lit\ntest to verify them.\n\nThe CLR numbering assigns one state number to each catchpad and\ncleanuppad.\n\nIt also computes two tree-like relations over states:\n 1) Each state has a \"HandlerParentState\", which is the state of the next\n    outer handler enclosing this state's handler (same as nearest ancestor\n    per the ParentPad linkage on EH pads, but skipping over catchswitches).\n 2) Each state has a \"TryParentState\", which:\n    a) for a catchpad that's not the last handler on its catchswitch, is\n       the state of the next catchpad on that catchswitch.\n    b) for all other pads, is the state of the pad whose try region is the\n       next outer try region enclosing this state's try region.  The \"try\n       regions are not present as such in the IR, but will be inferred\n       based on the placement of invokes and pads which reach each other\n       by exceptional exits.\n\nCatchswitches do not get their own states, but each gets mapped to the\nstate of its first catchpad.\n\nTable generation requires each state's \"unwind dest\" state to have a lower\nstate number than the given state.\n\nSince HandlerParentState can be computed as a function of a pad's\nParentPad, and TryParentState can be computed as a function of its unwind\ndest and the TryParentStates of its children, the CLR state numbering\nalgorithm first computes HandlerParentState in a top-down pass, then\ncomputes TryParentState in a bottom-up pass.\n\nAlso reword some comments/names in the CLR EH table generation to make the\ndistinction between the different kinds of \"parent\" clear.\n\n\nReviewers: rnk, andrew.w.kaylor, majnemer\n\nSubscribers: AndyAyers, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D15325\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256760 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/7f410b17a792c624d2b939fa56285f8eb8cba184"},{"sha":"9e83b9f4a1101a4d30b462ee22d734e000163ea3","author":{"email":"3b9de09f2ff76afe9f0ad4fcae4ff68f52ec7fc4@mxc.ca","name":"Nick Lewycky"},"message":"Fix comment in typo. NFC\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256761 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/9e83b9f4a1101a4d30b462ee22d734e000163ea3"},{"sha":"f34e40f4b44a0d76665830948586e2c6e07a8b75","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[LICM] Don't insert instructions after a catchswitch when performing loop promotion\n\nInserting after a catchswitch results in verifier errors, bail out on\npromotion if a catchswitch is a loop exit.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256763 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/f34e40f4b44a0d76665830948586e2c6e07a8b75"},{"sha":"d84e2865f64b93c520e11ff15c4dce9aabfcad33","author":{"email":"4331068bbad41c501a7c6852c30dcaa9fbd59061@playstation.sony.com","name":"Paul Robinson"},"message":"Clang-format my previous change (r256313)\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256764 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/d84e2865f64b93c520e11ff15c4dce9aabfcad33"},{"sha":"a1c12525dcbaa0c116d8e308a4f68718ed32ca4c","author":{"email":"9565d5ba9b10989b5d5fd7d4f78c517d963f506d@codeaurora.org","name":"Geoff Berry"},"message":"[AArch64] Optimize some simple TBZ/TBNZ cases.\n\nSummary:\nAdd some AArch64 dag combines to optimize some simple TBZ/TBNZ cases:\n\n (tbz (and x, m), b) -> (tbz x, b)\n (tbz (shl x, c), b) -> (tbz x, b-c)\n (tbz (shr x, c), b) -> (tbz x, b+c)\n (tbz (xor x, -1), b) -> (tbnz x, b)\n\nReviewers: jmolloy, mcrosier, t.p.northover\n\nSubscribers: aemerson, rengolin, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D15702\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256765 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/a1c12525dcbaa0c116d8e308a4f68718ed32ca4c"},{"sha":"2a35fc6e65357d90f66edb06fdf326cfbe99ad00","author":{"email":"07e77dc2a1e0a0bf87262be222de4eb07b1d3ef1@codeaurora.org","name":"Haicheng Wu"},"message":"This is a test commit to check my commit access works.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256767 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/2a35fc6e65357d90f66edb06fdf326cfbe99ad00"},{"sha":"8c5b0b157eace81caa0bc7d2fb3f8edc1b172a2c","author":{"email":"07e77dc2a1e0a0bf87262be222de4eb07b1d3ef1@codeaurora.org","name":"Haicheng Wu"},"message":"Revert previous test commit.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256768 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/8c5b0b157eace81caa0bc7d2fb3f8edc1b172a2c"},{"sha":"3c91dc3b095552a64df3961b41a3caf6ebca57d3","author":{"email":"9361a4f80fb0ccc2eb0b7e22edda353a02c08036@apple.com","name":"Aditya Nandakumar"},"message":"Remove dead instructions before Redoing\n\nBefore reevaluating instructions, iterate over all instructions\nto be reevaluated and remove trivially dead instructions and if\nany of it's operands become trivially dead, mark it for deletion\nuntil all trivially dead instructions have been removed\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256773 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/3c91dc3b095552a64df3961b41a3caf6ebca57d3"},{"sha":"e27d3110651f72bdecc9d557b08692cb0b6abf00","author":{"email":"cebe363cee6d3fa04b2b89435790869c6de2f2fc@google.com","name":"Xinliang David Li"},"message":"Update documantation\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256774 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/e27d3110651f72bdecc9d557b08692cb0b6abf00"},{"sha":"c5273ddfecb6d5d8000d55f3e0aa1c93d492dd49","author":{"email":"85590917cb30a670bf23f5b4273617f8815d1e87@amd.com","name":"Tom Stellard"},"message":"AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td\n\nSummary: This was accidently moved to CIInstructions.td in r256282\n\nReviewers: cfang, arsenm\n\nSubscribers: arsenm, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D15763\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256775 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/daggerproject/dagger/commits/c5273ddfecb6d5d8000d55f3e0aa1c93d492dd49"}]}