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For non-POPCNT case, use newly added bit_count(3).\n\nReported by:\talc\nReviewed by:\talc, kib\nDifferential Revision:\thttps://reviews.freebsd.org/D6541","distinct":false,"url":"https://api.github.com/repos/yaneurabeya/freebsd/commits/45ae491494493d7935a06c1ad0e655d974d1cf22"},{"sha":"221ca14ee282d2a4c15a2e79f446f6d3e74f80b1","author":{"name":"ian","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"message":"Disable alignment faults on armv6, adjust various alignment-related macros\nto match the new state of affairs.  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Mostly this focuses on the big changes needed for setting the\nbus clock, because ESDHC is SDHCI v2.0 and USDHC is 3.0, and the number,\nlocation, and interpretation of clock divisor bits is vastly different\nbetween the two.  This doesn't get the device all the way to functioning\non ESDHC hardware yet, but it's much closer, now getting through all the\ncard detection and negotiation of capabilties and speed (but it eventually\nhangs on what appears to be a missing interrupt).\n\nAnother missing chunk of code for handling ESDHC's 32 bit command-and-mode\nregister using sdhci's pair of 16 bit writes is added.\n\nThis also does some leading whitespace cleanups and sorts some softc\nstruct members by size, and adds some comments (because when do I ever\ntouch code without adding comments?).","distinct":false,"url":"https://api.github.com/repos/yaneurabeya/freebsd/commits/9b1c09bf1ef8d2ffad172da432c3289d7af5bd1e"}]}
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