{"push_id":1426326315,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"ab827bdc355dcb484a215251f2baea18638c5b30","before":"2e72c7b920f2f024867eff25dd65de1f25ad9fd1","commits":[{"sha":"46cc79217bdffc64d38f6b225aec217cdeca561b","author":{"name":"Joerg Sonnenberger","email":"15530eab4154955ead80e91f28b8666787b42dad@bec.de"},"message":"Revert r287553: [CodeGenPrep] Skip merging empty case blocks\n\nIt results in assertions in lib/Analysis/BlockFrequencyInfoImpl.cpp line\n670 (\"Expected irreducible CFG\").\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288052 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/46cc79217bdffc64d38f6b225aec217cdeca561b"},{"sha":"ab827bdc355dcb484a215251f2baea18638c5b30","author":{"name":"Stanislav Mekhanoshin","email":"a18e16f06e746214956ec218bf08bc0265fef01f@amd.com"},"message":"[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies\n\nCodegen prepare sinks comparisons close to a user is we have only one register\nfor conditions. For AMDGPU we have many SGPRs capable to hold vector conditions.\nChanged BE to report we have many condition registers. That way IR LICM pass\nwould hoist an invariant comparison out of a loop and codegen prepare will not\nsink it.\n\nWith that done a condition is calculated in one block and used in another.\nCurrent behavior is to store workitem's condition in a VGPR using v_cndmask_b32\nand then restore it with yet another v_cmp instruction from that v_cndmask's\nresult. To mitigate the issue a propagation of source SGPR pair in place of v_cmp\nis implemented. Additional side effect of this is that we may consume less VGPRs\nat a cost of more SGPRs in case if holding of multiple conditions is needed, and\nthat is a clear win in most cases.\n\nDifferential Revision: https://reviews.llvm.org/D26114\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288053 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/ab827bdc355dcb484a215251f2baea18638c5b30"}]}
{"actor":{"display_login":"llvm-mirror"}}