{"push_id":1089684687,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"45f527a9128b3512ed9543f1a3d7a5e762d8b52e","before":"c41ec8290cfe67ad3ed3132b0b6e841ba72a0f1f","commits":[{"sha":"509827ae46d1a6f33ab23ac23dff810c0ade8b19","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions\nDifferential Revision: http://reviews.llvm.org/D18645\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268012 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/509827ae46d1a6f33ab23ac23dff810c0ade8b19"},{"sha":"57257b2fa7c9826c314735dab32c006c3bf75288","author":{"email":"9f30e08254c7a10e9893e2360716635c3149a80c@redking.me.uk","name":"Simon Pilgrim"},"message":"[InstCombine][SSE] Regenerated x86 pshufb tests\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268014 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/57257b2fa7c9826c314735dab32c006c3bf75288"},{"sha":"288df526cee4aba310faaabf76ed16fb40696a7c","author":{"email":"2d175e52f01d9525da3b8bc9f366b015e8756ac8@amd.com","name":"Nikolay Haustov"},"message":"AMDGPU/SI: Assembler: Unify parsing/printing of operands.\n\nSummary:\nThe goal is for each operand type to have its own parse function and\nat the same time share common code for tracking state as different\ninstruction types share operand types (e.g. glc/glc_flat, etc).\n\nIntroduce parseAMDGPUOperand which can parse any optional operand.\nDPP and Clamp/OMod have custom handling for now. Sam also suggested\nto have class hierarchy for operand types instead of table. This\ncan be done in separate change.\n\nRemove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps,\nparseMubufOptionalOps, parseDPPOptionalOps.\nReduce number of definitions of AsmOperand's and MatchClasses' by using common base class.\nRename AsmMatcher/InstPrinter methods accordingly.\nPrint immediate type when printing parsed immediate operand.\nUse 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3).\nUpdate tests.\n\nReviewers: tstellarAMD, SamWot, artem.tamazov\n\nSubscribers: qcolombet, arsenm, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D19584\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268015 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/288df526cee4aba310faaabf76ed16fb40696a7c"},{"sha":"45f527a9128b3512ed9543f1a3d7a5e762d8b52e","author":{"email":"9f30e08254c7a10e9893e2360716635c3149a80c@redking.me.uk","name":"Simon Pilgrim"},"message":"[InstCombine][SSE] Added x86 pshufb undef mask tests\n\nFIXME: We currently don't support folding constant pshufb shuffle masks containing undef elements.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268016 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/45f527a9128b3512ed9543f1a3d7a5e762d8b52e"}]}