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Code to work around Python 2.5 and lower isn't necessary.\n\nReviewers: ddunbar, echristo, delcypher, beanz\n\nSubscribers: llvm-commits, mehdi_amini\n\nDifferential Revision: https://reviews.llvm.org/D25209\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283169 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/6b3629eb077054e9a7e9a908f2647df6262d0dfe"},{"sha":"77893035dfec4b5066711b16bb3cd841f3157267","author":{"name":"Kyle Butt","email":"477d37cf5ac939d7e8c2d47b367cf6d6e47a866e@iteratee.net"},"message":"Revert \"Codegen: Tail-duplicate during placement.\"\n\nThis reverts commit ff234efbe23528e4f4c80c78057b920a51f434b2.\n\nCausing crashes on aarch64 build.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283172 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/77893035dfec4b5066711b16bb3cd841f3157267"},{"sha":"dc1ddc021dd688b1efda20e804f2d6f5133ba4ab","author":{"name":"Matt Arsenault","email":"becd9ebb08babd166e3a53b1fe2c83834aceaa25@amd.com"},"message":"AMDGPU: Factor SGPR spilling into separate functions\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283175 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/dc1ddc021dd688b1efda20e804f2d6f5133ba4ab"},{"sha":"548c83d3557db7971cf971fd5cc841be6b36cc90","author":{"name":"Matt Arsenault","email":"becd9ebb08babd166e3a53b1fe2c83834aceaa25@amd.com"},"message":"AMDGPU: Refactor indirect vector lowering\n\nAllow inserting multiple instructions in the\nexpanded loop.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283177 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/548c83d3557db7971cf971fd5cc841be6b36cc90"},{"sha":"bd79a5935d0f77a222e8699788b64b1e1dda8b84","author":{"name":"Kostya Serebryany","email":"929ea1a85e127c0f9ffdb8680cf24d3fc1a6e9ce@google.com"},"message":"[libFuzzer] change the probabilities so that we choose only the inputs that are known to be minimal inputs for at least one coverage feature (works only with -shrink=1 for now)\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283178 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/bd79a5935d0f77a222e8699788b64b1e1dda8b84"},{"sha":"e17aeaefbf31bd49103aff6530b4e7d484a5be7c","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[X86] Add MOV8rm_NOREX to switch in isReallyTriviallyReMaterializable to match MOV8rm.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283184 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/e17aeaefbf31bd49103aff6530b4e7d484a5be7c"},{"sha":"eedfbe031308c3d32d3ddc8db90fe92db22b7bb2","author":{"name":"Kostya Serebryany","email":"929ea1a85e127c0f9ffdb8680cf24d3fc1a6e9ce@google.com"},"message":"[libFuzzer] remove dfsan support and some related stale code. This is not being used and as is is pretty weak anyway\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283187 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/eedfbe031308c3d32d3ddc8db90fe92db22b7bb2"},{"sha":"40960f63616f62c8ac52eeeddf68bdb441b8be3e","author":{"name":"Michal Gorny","email":"7d5fd82d402780a99cd4f237ecee3ca3d2f069de@gentoo.org"},"message":"[cmake] Use separate doctrees to prevent races between Sphinx instances\n\nUse separate doctrees between different Sphinx builders in order to\nprevent race condition issues due to multiple Sphinx instances accessing\nthe same doctree cache in parallel.\n\nBug: https://llvm.org/bugs/show_bug.cgi?id=23781\n\nDifferential Revision: https://reviews.llvm.org/D23755\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283188 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/40960f63616f62c8ac52eeeddf68bdb441b8be3e"},{"sha":"aeddc35a35c55f487977d7609060225e03e2028b","author":{"name":"Michal Gorny","email":"7d5fd82d402780a99cd4f237ecee3ca3d2f069de@gentoo.org"},"message":"[cmake] Reintroduce (ldconfig-compatible) SOVERSIONs on shared libraries\n\nReintroduce versioning of shared libraries via SOVERSION, addressing\nthe issues with the previous design, since Gentoo is relying\non shared-split install of LLVM. The SOVERSIONs were originally\nintroduced in r229720 for all libraries, and removed in r252093 in favor\nof custom SONAME. As far as I understand, the major concern with the old\nversioning was that the used versions were incompatible with ldconfig.\n\nHaving considered that, this commit introduce SOVERSIONS with the\nfollowing considerations:\n\n1. SOVERSIONs are formed of major & minor version concatenated -- i.e.\nfor 4.0 its .so.40. This matches the common practice where the first\nversion number indicates ABI breakage, and therefore fixes the issues\nwith ldconfig. Additionally, VERSION with the remaining verion\ncomponents appended is used, however this is not strictly necessary.\n\n2. The versioning is only applied to libraries with no explicit SONAME\nspecified -- i.e. it won't apply to libLLVM but only to the split\nlibraries. It will also apply to libraries installed by the subprojects.\n\n3. The versioning is only done on *nix systems, Darwin excluded. This\nmatches the current use of SONAME.\n\nDifferential Revision: https://reviews.llvm.org/D24757\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283189 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/aeddc35a35c55f487977d7609060225e03e2028b"},{"sha":"d0e875cdad4ad13facadf6d1219bde72527158c9","author":{"name":"Nemanja Ivanovic","email":"5474874556cbb906c5bde8536be8eed5432b6068@gmail.com"},"message":"[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions\n\nThis patch corresponds to review:\nhttps://reviews.llvm.org/D23155\n\nThis patch removes the VSHRC register class (based on D20310) and adds\nexploitation of the Power9 sub-word integer loads into VSX registers as well\nas vector sign extensions.\nThe new instructions are useful for a few purposes:\n\n    Int to Fp conversions of 1 or 2-byte values loaded from memory\n    Building vectors of 1 or 2-byte integers with values loaded from memory\n    Storing individual 1 or 2-byte elements from integer vectors\n\nThis patch implements all of those uses.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283190 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/d0e875cdad4ad13facadf6d1219bde72527158c9"},{"sha":"02ede7e72c525fe5ea0ace314d4da01fce4174a3","author":{"name":"Nemanja Ivanovic","email":"5474874556cbb906c5bde8536be8eed5432b6068@gmail.com"},"message":"Fix a test case failure on Apple PPC.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283191 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/02ede7e72c525fe5ea0ace314d4da01fce4174a3"},{"sha":"a074ac8dd76b759884c99f5a0af8085b9b24cb27","author":{"name":"Sjoerd Meijer","email":"e61d26d7b22812bc830b6bcb514eb0ea42e5abe6@arm.com"},"message":"Consistent fp denormal mode names. NFC.\n\nThis fixes the inconsistency of the fp denormal option names: in LLVM this was\nDenormalType, but in Clang this is DenormalMode which seems better.\n\nDifferential Revision: https://reviews.llvm.org/D24906\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283192 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/a074ac8dd76b759884c99f5a0af8085b9b24cb27"},{"sha":"1390211bdb86e7a3f7f9c43e8a31eb280a455e97","author":{"name":"George Rimar","email":"4f1e9f067cb1f528bdd5c61b67a67d4a3f7472a3@accesssoftek.com"},"message":"[Object/ELF] - Avoid possible crash in getExtendedSymbolTableIndex().\n\nWhen using broken input object found using AFL,\ngetExtendedSymbolTableIndex() crashed because ShndxTable\nwas empty as object does not contain SHT_SYMTAB_SHNDX section.\n\nDifferential revision: https://reviews.llvm.org/D25189\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283196 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/1390211bdb86e7a3f7f9c43e8a31eb280a455e97"},{"sha":"e1a1a529457159f0cef5644d38421f82b5537805","author":{"name":"whitequark","email":"48d24ebbce5e6b720cc000f8cf22fc3544499278@whitequark.org"},"message":"[SelectionDAG] Fix calling convention in expansion of ?MULO.\n\nThe SMULO/UMULO DAG nodes, when not directly supported by the target,\nexpand to a multiplication twice as wide. In case that the resulting\ntype is not legal, an __mul?i3 intrinsic is used. Since the type is\nnot legal, the legalizer cannot directly call the intrinsic with\nthe wide arguments; instead, it \"pre-lowers\" them by splitting them\nin halves.\n\nThe \"pre-lowering\" code in essence made assumptions about\nthe calling convention, specifically that i(N*2) values will be\nsplit into two iN values and passed in consecutive registers in\nlittle-endian order. This, naturally, breaks on a big-endian system,\nsuch as our OR1K out-of-tree backend.\n\nThanks to James Miller <james@aatch.net> for help in debugging.\n\nDifferential Revision: https://reviews.llvm.org/D25223\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283203 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/e1a1a529457159f0cef5644d38421f82b5537805"},{"sha":"cd988cd5813bc9d89a11824e1f00b666603826a3","author":{"name":"George Rimar","email":"4f1e9f067cb1f528bdd5c61b67a67d4a3f7472a3@accesssoftek.com"},"message":"[Object/ELF] - Do not crash on invalid sh_offset value of REL[A] section.\n\nPreviously code would access invalid memory and may crash,\npatch fixes the issue.\n\nDifferential revision: https://reviews.llvm.org/D25187\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283204 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/cd988cd5813bc9d89a11824e1f00b666603826a3"},{"sha":"c072c50d24235f40c9d2f0b63caf1db580d36a20","author":{"name":"Simon Dardis","email":"2cadd7fe860cffe179363c66eef45424daae0f62@imgtec.com"},"message":"[mips][fastisel] Consider soft-float an unsupported floating point mode\n\nTreat soft-float as unsupported for fast-isel. Additionally, ensure we check\nthat lowering f32 arguments also considers the case of soft-float mode.\n\nReviewers: ehostunreach, vkalintiris, zoran.jovanovic\n\nDifferential Review: https://reviews.llvm.org/D24505\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283209 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/c072c50d24235f40c9d2f0b63caf1db580d36a20"},{"sha":"94ec1e3c4f12bbb35094e8ef3e37a682cb2c927d","author":{"name":"Nemanja Ivanovic","email":"5474874556cbb906c5bde8536be8eed5432b6068@gmail.com"},"message":"[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set\n\nThis patch corresponds to review:\n\nThe newly added VSX D-Form (register + offset) memory ops target the upper half\nof the VSX register set. The existing ones target the lower half. In order to\nunify these and have the ability to target all the VSX registers using D-Form\noperations, this patch defines Pseudo-ops for the loads/stores which are\nexpanded post-RA. The expansion then choses the correct opcode based on the\nregister that was allocated for the operation.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283212 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/94ec1e3c4f12bbb35094e8ef3e37a682cb2c927d"},{"sha":"61e54f80bc81c3c51789a158ba7ab238c4b89e5e","author":{"name":"Andrey Bokhanko","email":"802d20c10a985de622f6a521f96c86793c530f15@gmail.com"},"message":"Fix IntegerType::MAX_INT_BITS value\n\nIntegerType::MAX_INT_BITS is apparently not in sync with Type::SubclassData\nsize. This patch fixes this.\n\nDifferential Revision: https://reviews.llvm.org/D24814\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283215 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/61e54f80bc81c3c51789a158ba7ab238c4b89e5e"},{"sha":"1ca4cdc3c6c512230fbb600bd1b0bee9a355814a","author":{"name":"Rafael Espindola","email":"2cb6c78767a4200908f6aafbbd9b2dbabf89e63d@gmail.com"},"message":"Remove duplicated typedef. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283216 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/1ca4cdc3c6c512230fbb600bd1b0bee9a355814a"},{"sha":"22b0358c425b8cd2343566655182c2d032794cec","author":{"name":"Anna Thomas","email":"6ab69d5d0413b53c075e34a831dd9f590ea00ac1@azul.com"},"message":"[RS4GC] Handle ShuffleVector instruction in findBasePointer\n\nSummary:\nThis patch modifies the findBasePointer to handle the shufflevector instruction.\n\nTests run: RS4GC tests, local downstream tests.\n\nReviewers: reames, sanjoy\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D25197\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283219 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/arsenm/llvm/commits/22b0358c425b8cd2343566655182c2d032794cec"}]}
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